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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
434 lines
11 KiB
C
434 lines
11 KiB
C
![]() |
/*
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* Copyright (C) 2013, Lars-Peter Clausen <lars@metafoo.de>
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* JZ4740 DMAC support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/mach-jz4740/dma.h>
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#include "virt-dma.h"
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#define JZ_DMA_NR_CHANS 6
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struct jz4740_dma_sg {
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dma_addr_t addr;
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unsigned int len;
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};
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struct jz4740_dma_desc {
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struct virt_dma_desc vdesc;
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enum dma_transfer_direction direction;
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bool cyclic;
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unsigned int num_sgs;
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struct jz4740_dma_sg sg[];
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};
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struct jz4740_dmaengine_chan {
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struct virt_dma_chan vchan;
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struct jz4740_dma_chan *jz_chan;
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dma_addr_t fifo_addr;
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struct jz4740_dma_desc *desc;
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unsigned int next_sg;
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};
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struct jz4740_dma_dev {
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struct dma_device ddev;
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struct jz4740_dmaengine_chan chan[JZ_DMA_NR_CHANS];
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};
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static struct jz4740_dmaengine_chan *to_jz4740_dma_chan(struct dma_chan *c)
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{
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return container_of(c, struct jz4740_dmaengine_chan, vchan.chan);
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}
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static struct jz4740_dma_desc *to_jz4740_dma_desc(struct virt_dma_desc *vdesc)
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{
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return container_of(vdesc, struct jz4740_dma_desc, vdesc);
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}
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static struct jz4740_dma_desc *jz4740_dma_alloc_desc(unsigned int num_sgs)
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{
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return kzalloc(sizeof(struct jz4740_dma_desc) +
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sizeof(struct jz4740_dma_sg) * num_sgs, GFP_ATOMIC);
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}
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static enum jz4740_dma_width jz4740_dma_width(enum dma_slave_buswidth width)
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{
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switch (width) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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return JZ4740_DMA_WIDTH_8BIT;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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return JZ4740_DMA_WIDTH_16BIT;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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return JZ4740_DMA_WIDTH_32BIT;
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default:
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return JZ4740_DMA_WIDTH_32BIT;
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}
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}
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static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
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{
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if (maxburst <= 1)
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return JZ4740_DMA_TRANSFER_SIZE_1BYTE;
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else if (maxburst <= 3)
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return JZ4740_DMA_TRANSFER_SIZE_2BYTE;
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else if (maxburst <= 15)
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return JZ4740_DMA_TRANSFER_SIZE_4BYTE;
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else if (maxburst <= 31)
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return JZ4740_DMA_TRANSFER_SIZE_16BYTE;
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return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
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}
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static int jz4740_dma_slave_config(struct dma_chan *c,
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const struct dma_slave_config *config)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_config jzcfg;
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switch (config->direction) {
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case DMA_MEM_TO_DEV:
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jzcfg.flags = JZ4740_DMA_SRC_AUTOINC;
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jzcfg.transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
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chan->fifo_addr = config->dst_addr;
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break;
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case DMA_DEV_TO_MEM:
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jzcfg.flags = JZ4740_DMA_DST_AUTOINC;
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jzcfg.transfer_size = jz4740_dma_maxburst(config->src_maxburst);
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chan->fifo_addr = config->src_addr;
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break;
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default:
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return -EINVAL;
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}
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jzcfg.src_width = jz4740_dma_width(config->src_addr_width);
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jzcfg.dst_width = jz4740_dma_width(config->dst_addr_width);
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jzcfg.mode = JZ4740_DMA_MODE_SINGLE;
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jzcfg.request_type = config->slave_id;
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jz4740_dma_configure(chan->jz_chan, &jzcfg);
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return 0;
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}
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static int jz4740_dma_terminate_all(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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unsigned long flags;
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LIST_HEAD(head);
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spin_lock_irqsave(&chan->vchan.lock, flags);
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jz4740_dma_disable(chan->jz_chan);
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chan->desc = NULL;
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vchan_get_all_descriptors(&chan->vchan, &head);
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spin_unlock_irqrestore(&chan->vchan.lock, flags);
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vchan_dma_desc_free_list(&chan->vchan, &head);
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return 0;
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}
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static int jz4740_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg)
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{
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struct dma_slave_config *config = (struct dma_slave_config *)arg;
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switch (cmd) {
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case DMA_SLAVE_CONFIG:
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return jz4740_dma_slave_config(chan, config);
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case DMA_TERMINATE_ALL:
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return jz4740_dma_terminate_all(chan);
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default:
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return -ENOSYS;
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}
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}
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static int jz4740_dma_start_transfer(struct jz4740_dmaengine_chan *chan)
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{
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dma_addr_t src_addr, dst_addr;
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struct virt_dma_desc *vdesc;
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struct jz4740_dma_sg *sg;
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jz4740_dma_disable(chan->jz_chan);
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if (!chan->desc) {
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vdesc = vchan_next_desc(&chan->vchan);
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if (!vdesc)
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return 0;
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chan->desc = to_jz4740_dma_desc(vdesc);
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chan->next_sg = 0;
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}
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if (chan->next_sg == chan->desc->num_sgs)
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chan->next_sg = 0;
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sg = &chan->desc->sg[chan->next_sg];
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if (chan->desc->direction == DMA_MEM_TO_DEV) {
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src_addr = sg->addr;
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dst_addr = chan->fifo_addr;
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} else {
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src_addr = chan->fifo_addr;
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dst_addr = sg->addr;
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}
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jz4740_dma_set_src_addr(chan->jz_chan, src_addr);
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jz4740_dma_set_dst_addr(chan->jz_chan, dst_addr);
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jz4740_dma_set_transfer_count(chan->jz_chan, sg->len);
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chan->next_sg++;
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jz4740_dma_enable(chan->jz_chan);
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return 0;
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}
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static void jz4740_dma_complete_cb(struct jz4740_dma_chan *jz_chan, int error,
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void *devid)
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{
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struct jz4740_dmaengine_chan *chan = devid;
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spin_lock(&chan->vchan.lock);
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if (chan->desc) {
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if (chan->desc && chan->desc->cyclic) {
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vchan_cyclic_callback(&chan->desc->vdesc);
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} else {
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if (chan->next_sg == chan->desc->num_sgs) {
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chan->desc = NULL;
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vchan_cookie_complete(&chan->desc->vdesc);
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}
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}
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}
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jz4740_dma_start_transfer(chan);
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spin_unlock(&chan->vchan.lock);
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}
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static void jz4740_dma_issue_pending(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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unsigned long flags;
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spin_lock_irqsave(&chan->vchan.lock, flags);
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if (vchan_issue_pending(&chan->vchan) && !chan->desc)
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jz4740_dma_start_transfer(chan);
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spin_unlock_irqrestore(&chan->vchan.lock, flags);
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}
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static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg(
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struct dma_chan *c, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_desc *desc;
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struct scatterlist *sg;
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unsigned int i;
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desc = jz4740_dma_alloc_desc(sg_len);
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if (!desc)
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return NULL;
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for_each_sg(sgl, sg, sg_len, i) {
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desc->sg[i].addr = sg_dma_address(sg);
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desc->sg[i].len = sg_dma_len(sg);
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}
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desc->num_sgs = sg_len;
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desc->direction = direction;
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desc->cyclic = false;
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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}
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static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
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struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_desc *desc;
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unsigned int num_periods, i;
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if (buf_len % period_len)
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return NULL;
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num_periods = buf_len / period_len;
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desc = jz4740_dma_alloc_desc(num_periods);
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if (!desc)
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return NULL;
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for (i = 0; i < num_periods; i++) {
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desc->sg[i].addr = buf_addr;
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desc->sg[i].len = period_len;
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buf_addr += period_len;
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}
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desc->num_sgs = num_periods;
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desc->direction = direction;
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desc->cyclic = true;
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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}
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static size_t jz4740_dma_desc_residue(struct jz4740_dmaengine_chan *chan,
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struct jz4740_dma_desc *desc, unsigned int next_sg)
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{
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size_t residue = 0;
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unsigned int i;
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residue = 0;
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for (i = next_sg; i < desc->num_sgs; i++)
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residue += desc->sg[i].len;
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if (next_sg != 0)
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residue += jz4740_dma_get_residue(chan->jz_chan);
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return residue;
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}
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static enum dma_status jz4740_dma_tx_status(struct dma_chan *c,
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dma_cookie_t cookie, struct dma_tx_state *state)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct virt_dma_desc *vdesc;
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enum dma_status status;
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unsigned long flags;
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status = dma_cookie_status(c, cookie, state);
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if (status == DMA_SUCCESS || !state)
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return status;
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spin_lock_irqsave(&chan->vchan.lock, flags);
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vdesc = vchan_find_desc(&chan->vchan, cookie);
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if (cookie == chan->desc->vdesc.tx.cookie) {
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state->residue = jz4740_dma_desc_residue(chan, chan->desc,
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chan->next_sg);
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} else if (vdesc) {
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state->residue = jz4740_dma_desc_residue(chan,
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to_jz4740_dma_desc(vdesc), 0);
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} else {
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state->residue = 0;
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}
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spin_unlock_irqrestore(&chan->vchan.lock, flags);
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return status;
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}
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static int jz4740_dma_alloc_chan_resources(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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chan->jz_chan = jz4740_dma_request(chan, NULL);
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if (!chan->jz_chan)
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return -EBUSY;
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jz4740_dma_set_complete_cb(chan->jz_chan, jz4740_dma_complete_cb);
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return 0;
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}
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static void jz4740_dma_free_chan_resources(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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vchan_free_chan_resources(&chan->vchan);
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jz4740_dma_free(chan->jz_chan);
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chan->jz_chan = NULL;
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}
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static void jz4740_dma_desc_free(struct virt_dma_desc *vdesc)
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{
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kfree(container_of(vdesc, struct jz4740_dma_desc, vdesc));
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}
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static int jz4740_dma_probe(struct platform_device *pdev)
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{
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struct jz4740_dmaengine_chan *chan;
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struct jz4740_dma_dev *dmadev;
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struct dma_device *dd;
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unsigned int i;
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int ret;
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dmadev = devm_kzalloc(&pdev->dev, sizeof(*dmadev), GFP_KERNEL);
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if (!dmadev)
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return -EINVAL;
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dd = &dmadev->ddev;
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dma_cap_set(DMA_SLAVE, dd->cap_mask);
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dma_cap_set(DMA_CYCLIC, dd->cap_mask);
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dd->device_alloc_chan_resources = jz4740_dma_alloc_chan_resources;
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dd->device_free_chan_resources = jz4740_dma_free_chan_resources;
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dd->device_tx_status = jz4740_dma_tx_status;
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dd->device_issue_pending = jz4740_dma_issue_pending;
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dd->device_prep_slave_sg = jz4740_dma_prep_slave_sg;
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dd->device_prep_dma_cyclic = jz4740_dma_prep_dma_cyclic;
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dd->device_control = jz4740_dma_control;
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dd->dev = &pdev->dev;
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dd->chancnt = JZ_DMA_NR_CHANS;
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INIT_LIST_HEAD(&dd->channels);
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for (i = 0; i < dd->chancnt; i++) {
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chan = &dmadev->chan[i];
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chan->vchan.desc_free = jz4740_dma_desc_free;
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vchan_init(&chan->vchan, dd);
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}
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ret = dma_async_device_register(dd);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, dmadev);
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return 0;
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}
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static int jz4740_dma_remove(struct platform_device *pdev)
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{
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struct jz4740_dma_dev *dmadev = platform_get_drvdata(pdev);
|
||
|
|
||
|
dma_async_device_unregister(&dmadev->ddev);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static struct platform_driver jz4740_dma_driver = {
|
||
|
.probe = jz4740_dma_probe,
|
||
|
.remove = jz4740_dma_remove,
|
||
|
.driver = {
|
||
|
.name = "jz4740-dma",
|
||
|
.owner = THIS_MODULE,
|
||
|
},
|
||
|
};
|
||
|
module_platform_driver(jz4740_dma_driver);
|
||
|
|
||
|
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
|
||
|
MODULE_DESCRIPTION("JZ4740 DMA driver");
|
||
|
MODULE_LICENSE("GPLv2");
|