2019-05-23 09:14:49 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2016-06-26 17:37:08 +00:00
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/*
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* Performance counter support for POWER9 processors.
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*
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* Copyright 2009 Paul Mackerras, IBM Corporation.
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* Copyright 2013 Michael Ellerman, IBM Corporation.
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* Copyright 2016 Madhavan Srinivasan, IBM Corporation.
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*/
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#define pr_fmt(fmt) "power9-pmu: " fmt
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#include "isa207-common.h"
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2016-12-02 00:35:01 +00:00
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/*
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* Raw event encoding for Power9:
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*
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* 60 56 52 48 44 40 36 32
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
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* | | | | |
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2017-02-13 11:32:54 +00:00
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* | | *- IFM (Linux) | thresh start/stop -*
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2016-12-02 00:35:01 +00:00
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* | *- BHRB (Linux) *sm
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* *- EBB (Linux)
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*
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* 28 24 20 16 12 8 4 0
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* | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
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* [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ]
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* | | | | |
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* | | | | *- mark
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* | | *- L1/L2/L3 cache_sel |
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* | | |
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* | *- sampling mode for marked events *- combine
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* |
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* *- thresh_sel
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*
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* Below uses IBM bit numbering.
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*
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* MMCR1[x:y] = unit (PMCxUNIT)
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* MMCR1[24] = pmc1combine[0]
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* MMCR1[25] = pmc1combine[1]
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* MMCR1[26] = pmc2combine[0]
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* MMCR1[27] = pmc2combine[1]
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* MMCR1[28] = pmc3combine[0]
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* MMCR1[29] = pmc3combine[1]
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* MMCR1[30] = pmc4combine[0]
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* MMCR1[31] = pmc4combine[1]
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*
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* if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
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2017-02-13 11:32:54 +00:00
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* MMCR1[20:27] = thresh_ctl
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2016-12-02 00:35:01 +00:00
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* else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
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2017-02-13 11:32:54 +00:00
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* MMCR1[20:27] = thresh_ctl
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2016-12-02 00:35:01 +00:00
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* else
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* MMCRA[48:55] = thresh_ctl (THRESH START/END)
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*
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* if thresh_sel:
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* MMCRA[45:47] = thresh_sel
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*
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* if thresh_cmp:
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* MMCRA[9:11] = thresh_cmp[0:2]
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* MMCRA[12:18] = thresh_cmp[3:9]
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*
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2017-10-09 14:12:39 +00:00
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* MMCR1[16] = cache_sel[2]
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* MMCR1[17] = cache_sel[3]
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2016-12-02 00:35:01 +00:00
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*
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* if mark:
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* MMCRA[63] = 1 (SAMPLE_ENABLE)
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* MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
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* MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
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*
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* if EBB and BHRB:
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* MMCRA[32:33] = IFM
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*
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* MMCRA[SDAR_MODE] = sm
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*/
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2016-06-26 17:37:08 +00:00
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/*
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* Some power9 event codes.
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*/
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#define EVENT(_name, _code) _name = _code,
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enum {
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#include "power9-events-list.h"
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};
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#undef EVENT
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/* MMCRA IFM bits - POWER9 */
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#define POWER9_MMCRA_IFM1 0x0000000040000000UL
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#define POWER9_MMCRA_IFM2 0x0000000080000000UL
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#define POWER9_MMCRA_IFM3 0x00000000C0000000UL
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2019-05-11 02:42:17 +00:00
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#define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL
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2016-06-26 17:37:08 +00:00
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2020-08-07 10:05:00 +00:00
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extern u64 PERF_REG_EXTENDED_MASK;
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2018-03-04 11:56:27 +00:00
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/* Nasty Power9 specific hack */
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#define PVR_POWER9_CUMULUS 0x00002000
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2016-12-02 00:34:59 +00:00
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/* PowerISA v2.07 format attribute structure*/
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2022-03-07 23:14:14 +00:00
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extern const struct attribute_group isa207_pmu_format_group;
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2016-12-02 00:34:59 +00:00
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2020-09-23 07:14:53 +00:00
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static int p9_dd21_bl_ev[] = {
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2018-03-04 11:56:27 +00:00
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PM_MRK_ST_DONE_L2,
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PM_RADIX_PWC_L1_HIT,
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PM_FLOP_CMPL,
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PM_MRK_NTF_FIN,
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PM_RADIX_PWC_L2_HIT,
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PM_IFETCH_THROTTLE,
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PM_MRK_L2_TM_ST_ABORT_SISTER,
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PM_RADIX_PWC_L3_HIT,
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PM_RUN_CYC_SMT2_MODE,
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PM_TM_TX_PASS_RUN_INST,
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PM_DISP_HELD_SYNC_HOLD,
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};
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2020-09-23 07:14:53 +00:00
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static int p9_dd22_bl_ev[] = {
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2018-03-04 11:56:28 +00:00
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PM_DTLB_MISS_16G,
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PM_DERAT_MISS_2M,
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PM_DTLB_MISS_2M,
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PM_MRK_DTLB_MISS_1G,
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PM_DTLB_MISS_4K,
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PM_DERAT_MISS_1G,
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PM_MRK_DERAT_MISS_2M,
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PM_MRK_DTLB_MISS_4K,
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PM_MRK_DTLB_MISS_16G,
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PM_DTLB_MISS_64K,
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PM_MRK_DERAT_MISS_1G,
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PM_MRK_DTLB_MISS_64K,
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PM_DISP_HELD_SYNC_HOLD,
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PM_DTLB_MISS_16M,
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PM_DTLB_MISS_1G,
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PM_MRK_DTLB_MISS_16M,
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};
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2017-02-12 17:03:12 +00:00
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/* Table of alternatives, sorted by column 0 */
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static const unsigned int power9_event_alternatives[][MAX_ALT] = {
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2017-07-31 09:33:21 +00:00
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{ PM_BR_2PATH, PM_BR_2PATH_ALT },
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powerpc/perf: Fix power9 event alternatives
When scheduling a group of events, there are constraint checks done to
make sure all events can go in a group. Example, one of the criteria is
that events in a group cannot use the same PMC. But platform specific
PMU supports alternative event for some of the event codes. During
perf_event_open(), if any event group doesn't match constraint check
criteria, further lookup is done to find alternative event.
By current design, the array of alternatives events in PMU code is
expected to be sorted by column 0. This is because in
find_alternative() the return criteria is based on event code
comparison. ie. "event < ev_alt[i][0])". This optimisation is there
since find_alternative() can be called multiple times. In power9 PMU
code, the alternative event array is not sorted properly and hence there
is breakage in finding alternative events.
To work with existing logic, fix the alternative event array to be
sorted by column 0 for power9-pmu.c
Results:
With alternative events, multiplexing can be avoided. That is, for
example, in power9 PM_LD_MISS_L1 (0x3e054) has alternative event,
PM_LD_MISS_L1_ALT (0x400f0). This is an identical event which can be
programmed in a different PMC.
Before:
# perf stat -e r3e054,r300fc
Performance counter stats for 'system wide':
1057860 r3e054 (50.21%)
379 r300fc (49.79%)
0.944329741 seconds time elapsed
Since both the events are using PMC3 in this case, they are
multiplexed here.
After:
# perf stat -e r3e054,r300fc
Performance counter stats for 'system wide':
1006948 r3e054
182 r300fc
Fixes: 91e0bd1e6251 ("powerpc/perf: Add PM_LD_MISS_L1 and PM_BR_2PATH to power9 event list")
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Reviewed-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220419114828.89843-1-atrajeev@linux.vnet.ibm.com
2022-04-19 11:48:27 +00:00
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{ PM_INST_DISP, PM_INST_DISP_ALT },
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{ PM_RUN_CYC_ALT, PM_RUN_CYC },
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{ PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
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{ PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
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2017-02-12 17:03:12 +00:00
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};
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static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
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{
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int num_alt = 0;
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2017-07-31 08:02:41 +00:00
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num_alt = isa207_get_alternatives(event, alt,
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ARRAY_SIZE(power9_event_alternatives), flags,
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power9_event_alternatives);
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2017-02-12 17:03:12 +00:00
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return num_alt;
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}
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2021-04-08 07:45:04 +00:00
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static int power9_check_attr_config(struct perf_event *ev)
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{
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u64 val;
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u64 event = ev->attr.config;
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val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
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if (val == 0xC || isa3XX_check_attr_config(ev))
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return -EINVAL;
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return 0;
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}
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2016-06-26 17:37:09 +00:00
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GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
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GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
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GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
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2017-08-09 12:48:24 +00:00
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GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
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2016-06-26 17:37:09 +00:00
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GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
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GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
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GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
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2018-12-10 03:59:05 +00:00
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GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
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GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
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2016-06-26 17:37:09 +00:00
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CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
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CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
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CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
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CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
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CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
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CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
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CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
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CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
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CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
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CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
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CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
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2017-08-09 12:48:24 +00:00
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CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
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2016-06-26 17:37:09 +00:00
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CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
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CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
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static struct attribute *power9_events_attr[] = {
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GENERIC_EVENT_PTR(PM_CYC),
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GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
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GENERIC_EVENT_PTR(PM_CMPLU_STALL),
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GENERIC_EVENT_PTR(PM_INST_CMPL),
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2017-08-09 12:48:24 +00:00
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GENERIC_EVENT_PTR(PM_BR_CMPL),
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2016-06-26 17:37:09 +00:00
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GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
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GENERIC_EVENT_PTR(PM_LD_REF_L1),
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GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
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2018-12-10 03:59:05 +00:00
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GENERIC_EVENT_PTR(MEM_LOADS),
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GENERIC_EVENT_PTR(MEM_STORES),
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2016-06-26 17:37:09 +00:00
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CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
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CACHE_EVENT_PTR(PM_LD_REF_L1),
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CACHE_EVENT_PTR(PM_L1_PREF),
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CACHE_EVENT_PTR(PM_ST_MISS_L1),
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CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
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CACHE_EVENT_PTR(PM_INST_FROM_L1),
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CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
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CACHE_EVENT_PTR(PM_DATA_FROM_L3),
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CACHE_EVENT_PTR(PM_L3_PREF_ALL),
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CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
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2017-08-09 12:48:24 +00:00
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CACHE_EVENT_PTR(PM_BR_CMPL),
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2016-06-26 17:37:09 +00:00
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CACHE_EVENT_PTR(PM_DTLB_MISS),
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CACHE_EVENT_PTR(PM_ITLB_MISS),
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NULL
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};
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2022-03-07 23:14:14 +00:00
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static const struct attribute_group power9_pmu_events_group = {
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2016-06-26 17:37:09 +00:00
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.name = "events",
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.attrs = power9_events_attr,
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};
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2016-06-26 17:37:08 +00:00
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2016-12-02 00:35:01 +00:00
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PMU_FORMAT_ATTR(event, "config:0-51");
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PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
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PMU_FORMAT_ATTR(mark, "config:8");
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PMU_FORMAT_ATTR(combine, "config:10-11");
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PMU_FORMAT_ATTR(unit, "config:12-15");
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PMU_FORMAT_ATTR(pmc, "config:16-19");
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PMU_FORMAT_ATTR(cache_sel, "config:20-23");
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PMU_FORMAT_ATTR(sample_mode, "config:24-28");
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PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
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PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
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PMU_FORMAT_ATTR(thresh_start, "config:36-39");
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PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
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PMU_FORMAT_ATTR(sdar_mode, "config:50-51");
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|
|
|
|
|
|
|
static struct attribute *power9_pmu_format_attr[] = {
|
|
|
|
|
&format_attr_event.attr,
|
|
|
|
|
&format_attr_pmcxsel.attr,
|
|
|
|
|
&format_attr_mark.attr,
|
|
|
|
|
&format_attr_combine.attr,
|
|
|
|
|
&format_attr_unit.attr,
|
|
|
|
|
&format_attr_pmc.attr,
|
|
|
|
|
&format_attr_cache_sel.attr,
|
|
|
|
|
&format_attr_sample_mode.attr,
|
|
|
|
|
&format_attr_thresh_sel.attr,
|
|
|
|
|
&format_attr_thresh_stop.attr,
|
|
|
|
|
&format_attr_thresh_start.attr,
|
|
|
|
|
&format_attr_thresh_cmp.attr,
|
|
|
|
|
&format_attr_sdar_mode.attr,
|
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2022-03-07 23:14:14 +00:00
|
|
|
|
static const struct attribute_group power9_pmu_format_group = {
|
2016-12-02 00:35:01 +00:00
|
|
|
|
.name = "format",
|
|
|
|
|
.attrs = power9_pmu_format_attr,
|
|
|
|
|
};
|
|
|
|
|
|
2022-05-20 08:46:29 +00:00
|
|
|
|
static struct attribute *power9_pmu_caps_attrs[] = {
|
|
|
|
|
NULL
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct attribute_group power9_pmu_caps_group = {
|
|
|
|
|
.name = "caps",
|
|
|
|
|
.attrs = power9_pmu_caps_attrs,
|
|
|
|
|
};
|
|
|
|
|
|
2016-12-02 00:35:01 +00:00
|
|
|
|
static const struct attribute_group *power9_pmu_attr_groups[] = {
|
|
|
|
|
&power9_pmu_format_group,
|
|
|
|
|
&power9_pmu_events_group,
|
2022-05-20 08:46:29 +00:00
|
|
|
|
&power9_pmu_caps_group,
|
2016-12-02 00:35:01 +00:00
|
|
|
|
NULL,
|
|
|
|
|
};
|
|
|
|
|
|
2016-06-26 17:37:08 +00:00
|
|
|
|
static int power9_generic_events[] = {
|
|
|
|
|
[PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
|
|
|
|
|
[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
|
|
|
|
|
[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
|
|
|
|
|
[PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
|
2017-08-09 12:48:24 +00:00
|
|
|
|
[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
|
2016-06-26 17:37:08 +00:00
|
|
|
|
[PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
|
|
|
|
|
[PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
|
|
|
|
|
[PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static u64 power9_bhrb_filter_map(u64 branch_sample_type)
|
|
|
|
|
{
|
|
|
|
|
u64 pmu_bhrb_filter = 0;
|
|
|
|
|
|
|
|
|
|
/* BHRB and regular PMU events share the same privilege state
|
|
|
|
|
* filter configuration. BHRB is always recorded along with a
|
|
|
|
|
* regular PMU event. As the privilege state filter is handled
|
|
|
|
|
* in the basic PMC configuration of the accompanying regular
|
|
|
|
|
* PMU event, we ignore any separate BHRB specific request.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* No branch filter requested */
|
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
|
|
|
|
|
return pmu_bhrb_filter;
|
|
|
|
|
|
|
|
|
|
/* Invalid branch filter options - HW does not support */
|
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
|
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
|
|
if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
|
|
|
|
|
pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
|
|
|
|
|
return pmu_bhrb_filter;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Every thing else is unsupported */
|
|
|
|
|
return -1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void power9_config_bhrb(u64 pmu_bhrb_filter)
|
|
|
|
|
{
|
2019-05-11 02:42:17 +00:00
|
|
|
|
pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
|
|
|
|
|
|
2016-06-26 17:37:08 +00:00
|
|
|
|
/* Enable BHRB filter in PMU */
|
|
|
|
|
mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define C(x) PERF_COUNT_HW_CACHE_##x
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Table of generalized cache-related events.
|
|
|
|
|
* 0 means not supported, -1 means nonsensical, other values
|
|
|
|
|
* are event codes.
|
|
|
|
|
*/
|
2020-07-17 14:38:15 +00:00
|
|
|
|
static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
|
2016-06-26 17:37:08 +00:00
|
|
|
|
[ C(L1D) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
|
|
|
|
|
[ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = PM_ST_MISS_L1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_L1_PREF,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(L1I) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
|
|
|
|
|
[ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(LL) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
|
|
|
|
|
[ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
2018-06-10 14:27:02 +00:00
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
2016-06-26 17:37:08 +00:00
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
|
|
|
|
|
[ C(RESULT_MISS) ] = 0,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(DTLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = PM_DTLB_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(ITLB) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = 0,
|
|
|
|
|
[ C(RESULT_MISS) ] = PM_ITLB_MISS,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(BPU) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
2017-08-09 12:48:24 +00:00
|
|
|
|
[ C(RESULT_ACCESS) ] = PM_BR_CMPL,
|
2016-06-26 17:37:08 +00:00
|
|
|
|
[ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
[ C(NODE) ] = {
|
|
|
|
|
[ C(OP_READ) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_WRITE) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
[ C(OP_PREFETCH) ] = {
|
|
|
|
|
[ C(RESULT_ACCESS) ] = -1,
|
|
|
|
|
[ C(RESULT_MISS) ] = -1,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
#undef C
|
|
|
|
|
|
2016-12-02 00:35:01 +00:00
|
|
|
|
static struct power_pmu power9_pmu = {
|
|
|
|
|
.name = "POWER9",
|
|
|
|
|
.n_counter = MAX_PMU_COUNTERS,
|
|
|
|
|
.add_fields = ISA207_ADD_FIELDS,
|
2017-05-26 08:08:27 +00:00
|
|
|
|
.test_adder = ISA207_TEST_ADDER,
|
powerpc/perf: Add constraints for power9 l2/l3 bus events
In previous generation processors, both bus events and direct
events of performance monitoring unit can be individually
programmabled and monitored in PMCs.
But in Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank.
Patch enforce two contraints incase of L2/L3 bus events.
1)Any L2/L3 event when programmed is also expected to program corresponding
PMC4 event from that group.
2)PMC4 event should always been programmed first due to group constraint
logic limitation
For ex. consider these L3 bus events
PM_L3_PF_ON_CHIP_MEM (0x460A0),
PM_L3_PF_MISS_L3 (0x160A0),
PM_L3_CO_MEM (0x260A0),
PM_L3_PF_ON_CHIP_CACHE (0x360A0),
1) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r160A0,r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r160A0,r260A0,r360A0}" < >
2) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r260A0,r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r260A0,r360A0}" < >
3) This is an INVALID group for L3 Bus event monitoring,
since it is missing PMC4 event.
perf stat -e "{r360A0}" < >
And this is a VALID group for L3 Bus events:
perf stat -e "{r460A0,r360A0}" < >
Patch here implements group constraint logic suggested by Michael Ellerman.
Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-06-10 14:27:01 +00:00
|
|
|
|
.group_constraint_mask = CNST_CACHE_PMC4_MASK,
|
|
|
|
|
.group_constraint_val = CNST_CACHE_PMC4_VAL,
|
2016-12-02 00:35:01 +00:00
|
|
|
|
.compute_mmcr = isa207_compute_mmcr,
|
|
|
|
|
.config_bhrb = power9_config_bhrb,
|
|
|
|
|
.bhrb_filter_map = power9_bhrb_filter_map,
|
|
|
|
|
.get_constraint = isa207_get_constraint,
|
2017-02-12 17:03:12 +00:00
|
|
|
|
.get_alternatives = power9_get_alternatives,
|
2017-04-11 01:51:09 +00:00
|
|
|
|
.get_mem_data_src = isa207_get_mem_data_src,
|
|
|
|
|
.get_mem_weight = isa207_get_mem_weight,
|
2016-12-02 00:35:01 +00:00
|
|
|
|
.disable_pmc = isa207_disable_pmc,
|
|
|
|
|
.flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
|
|
|
|
|
.n_generic = ARRAY_SIZE(power9_generic_events),
|
|
|
|
|
.generic_events = power9_generic_events,
|
|
|
|
|
.cache_events = &power9_cache_events,
|
|
|
|
|
.attr_groups = power9_pmu_attr_groups,
|
|
|
|
|
.bhrb_nr = 32,
|
2020-08-07 10:05:00 +00:00
|
|
|
|
.capabilities = PERF_PMU_CAP_EXTENDED_REGS,
|
2021-04-08 07:45:04 +00:00
|
|
|
|
.check_attr_config = power9_check_attr_config,
|
2016-12-02 00:35:01 +00:00
|
|
|
|
};
|
|
|
|
|
|
2021-12-16 22:00:19 +00:00
|
|
|
|
int __init init_power9_pmu(void)
|
2016-06-26 17:37:08 +00:00
|
|
|
|
{
|
2016-12-02 00:35:00 +00:00
|
|
|
|
int rc = 0;
|
2018-03-04 11:56:27 +00:00
|
|
|
|
unsigned int pvr = mfspr(SPRN_PVR);
|
2016-06-26 17:37:08 +00:00
|
|
|
|
|
2022-07-07 14:37:17 +00:00
|
|
|
|
if (PVR_VER(pvr) != PVR_POWER9)
|
2016-06-26 17:37:08 +00:00
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
2018-03-04 11:56:27 +00:00
|
|
|
|
/* Blacklist events */
|
|
|
|
|
if (!(pvr & PVR_POWER9_CUMULUS)) {
|
|
|
|
|
if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
|
|
|
|
|
power9_pmu.blacklist_ev = p9_dd21_bl_ev;
|
|
|
|
|
power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
|
2018-03-04 11:56:28 +00:00
|
|
|
|
} else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) {
|
|
|
|
|
power9_pmu.blacklist_ev = p9_dd22_bl_ev;
|
|
|
|
|
power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev);
|
2018-03-04 11:56:27 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-08-07 10:05:00 +00:00
|
|
|
|
/* Set the PERF_REG_EXTENDED_MASK here */
|
|
|
|
|
PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
|
|
|
|
|
|
2018-07-05 08:47:00 +00:00
|
|
|
|
rc = register_power_pmu(&power9_pmu);
|
2016-06-26 17:37:08 +00:00
|
|
|
|
if (rc)
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
|
|
/* Tell userspace that EBB is supported */
|
|
|
|
|
cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|