2005-04-16 22:20:36 +00:00
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/*
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* (C) Copyright 2003-2004
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* Humboldt Solutions Ltd, adrian@humboldt.co.uk.
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* This is a combined i2c adapter and algorithm driver for the
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* MPC107/Tsi107 PowerPC northbridge and processors that include
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* the same I2C unit (8240, 8245, 85xx).
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*
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* Release 0.8
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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2008-06-30 23:01:26 +00:00
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#include <linux/of_platform.h>
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#include <linux/of_i2c.h>
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2005-10-29 18:07:23 +00:00
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2009-04-07 08:20:53 +00:00
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#include <linux/io.h>
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2005-04-16 22:20:36 +00:00
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#include <linux/fsl_devices.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
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#include <asm/mpc52xx.h>
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#include <sysdev/fsl_soc.h>
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2008-06-30 23:01:26 +00:00
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#define DRV_NAME "mpc-i2c"
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2009-04-07 08:20:53 +00:00
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#define MPC_I2C_FDR 0x04
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#define MPC_I2C_CR 0x08
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#define MPC_I2C_SR 0x0c
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#define MPC_I2C_DR 0x10
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2005-04-16 22:20:36 +00:00
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#define MPC_I2C_DFSRR 0x14
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#define CCR_MEN 0x80
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#define CCR_MIEN 0x40
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#define CCR_MSTA 0x20
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#define CCR_MTX 0x10
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#define CCR_TXAK 0x08
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#define CCR_RSTA 0x04
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#define CSR_MCF 0x80
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#define CSR_MAAS 0x40
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#define CSR_MBB 0x20
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#define CSR_MAL 0x10
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#define CSR_SRW 0x04
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#define CSR_MIF 0x02
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#define CSR_RXAK 0x01
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struct mpc_i2c {
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2009-04-07 08:20:54 +00:00
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struct device *dev;
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2005-04-26 01:32:12 +00:00
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void __iomem *base;
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2005-04-16 22:20:36 +00:00
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u32 interrupt;
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wait_queue_head_t queue;
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struct i2c_adapter adap;
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int irq;
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i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
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};
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struct mpc_i2c_divider {
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u16 divider;
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u16 fdr; /* including dfsrr */
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};
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struct mpc_i2c_match_data {
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void (*setclock)(struct device_node *node,
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struct mpc_i2c *i2c,
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u32 clock, u32 prescaler);
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u32 prescaler;
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2005-04-16 22:20:36 +00:00
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};
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2009-04-07 08:20:53 +00:00
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static inline void writeccr(struct mpc_i2c *i2c, u32 x)
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2005-04-16 22:20:36 +00:00
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{
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writeb(x, i2c->base + MPC_I2C_CR);
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}
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 13:55:46 +00:00
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static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
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2005-04-16 22:20:36 +00:00
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{
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struct mpc_i2c *i2c = dev_id;
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if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
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/* Read again to allow register to stabilise */
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i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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2009-02-06 14:00:37 +00:00
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wake_up(&i2c->queue);
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2005-04-16 22:20:36 +00:00
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}
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return IRQ_HANDLED;
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}
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2007-07-12 12:12:31 +00:00
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/* Sometimes 9th clock pulse isn't generated, and slave doesn't release
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* the bus, because it wants to send ACK.
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* Following sequence of enabling/disabling and sending start/stop generates
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* the pulse, so it's all OK.
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*/
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static void mpc_i2c_fixup(struct mpc_i2c *i2c)
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{
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writeccr(i2c, 0);
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udelay(30);
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writeccr(i2c, CCR_MEN);
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udelay(30);
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writeccr(i2c, CCR_MSTA | CCR_MTX);
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udelay(30);
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writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
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udelay(30);
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writeccr(i2c, CCR_MEN);
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udelay(30);
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}
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2005-04-16 22:20:36 +00:00
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static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
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{
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unsigned long orig_jiffies = jiffies;
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u32 x;
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int result = 0;
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2009-04-07 08:20:53 +00:00
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if (i2c->irq == NO_IRQ) {
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2005-04-16 22:20:36 +00:00
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while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
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schedule();
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if (time_after(jiffies, orig_jiffies + timeout)) {
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2009-04-07 08:20:54 +00:00
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dev_dbg(i2c->dev, "timeout\n");
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2007-08-14 16:37:14 +00:00
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writeccr(i2c, 0);
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2005-04-16 22:20:36 +00:00
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result = -EIO;
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break;
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}
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}
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x = readb(i2c->base + MPC_I2C_SR);
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writeb(0, i2c->base + MPC_I2C_SR);
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} else {
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/* Interrupt mode */
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2009-02-06 14:00:37 +00:00
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result = wait_event_timeout(i2c->queue,
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2009-03-28 20:34:43 +00:00
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(i2c->interrupt & CSR_MIF), timeout);
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2005-04-16 22:20:36 +00:00
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2009-02-06 14:00:37 +00:00
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if (unlikely(!(i2c->interrupt & CSR_MIF))) {
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2009-04-07 08:20:54 +00:00
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dev_dbg(i2c->dev, "wait timeout\n");
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2007-08-14 16:37:14 +00:00
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writeccr(i2c, 0);
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2005-04-16 22:20:36 +00:00
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result = -ETIMEDOUT;
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}
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x = i2c->interrupt;
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i2c->interrupt = 0;
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}
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if (result < 0)
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return result;
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if (!(x & CSR_MCF)) {
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2009-04-07 08:20:54 +00:00
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dev_dbg(i2c->dev, "unfinished\n");
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2005-04-16 22:20:36 +00:00
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return -EIO;
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}
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if (x & CSR_MAL) {
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2009-04-07 08:20:54 +00:00
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dev_dbg(i2c->dev, "MAL\n");
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2005-04-16 22:20:36 +00:00
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return -EIO;
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}
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if (writing && (x & CSR_RXAK)) {
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2009-04-07 08:20:54 +00:00
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dev_dbg(i2c->dev, "No RXAK\n");
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2005-04-16 22:20:36 +00:00
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/* generate stop */
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writeccr(i2c, CCR_MEN);
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return -EIO;
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}
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return 0;
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}
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i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
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#ifdef CONFIG_PPC_52xx
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static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
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{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
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{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
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{36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
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{52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
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{68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
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{96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
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{128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
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{176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
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{240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
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{320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
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{448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
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{640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
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{1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
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{1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
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{2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
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{4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
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{7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
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{10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
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};
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int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
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{
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const struct mpc52xx_i2c_divider *div = NULL;
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unsigned int pvr = mfspr(SPRN_PVR);
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u32 divider;
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int i;
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if (!clock)
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return -EINVAL;
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/* Determine divider value */
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divider = mpc52xx_find_ipb_freq(node) / clock;
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that
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* is equal to or lower than the requested speed.
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*/
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for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) {
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div = &mpc_i2c_dividers_52xx[i];
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/* Old MPC5200 rev A CPUs do not support the high bits */
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if (div->fdr & 0xc0 && pvr == 0x80822011)
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continue;
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if (div->divider >= divider)
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break;
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}
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|
|
|
|
|
|
|
|
|
return div ? (int)div->fdr : -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mpc_i2c_setclock_52xx(struct device_node *node,
|
|
|
|
|
struct mpc_i2c *i2c,
|
|
|
|
|
u32 clock, u32 prescaler)
|
|
|
|
|
{
|
|
|
|
|
int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler);
|
|
|
|
|
|
|
|
|
|
if (fdr < 0)
|
|
|
|
|
fdr = 0x3f; /* backward compatibility */
|
|
|
|
|
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
|
|
|
|
|
dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
|
|
|
|
|
}
|
|
|
|
|
#else /* !CONFIG_PPC_52xx */
|
|
|
|
|
static void mpc_i2c_setclock_52xx(struct device_node *node,
|
|
|
|
|
struct mpc_i2c *i2c,
|
|
|
|
|
u32 clock, u32 prescaler)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PPC_52xx*/
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_SOC
|
|
|
|
|
static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
|
|
|
|
|
{160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
|
|
|
|
|
{288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
|
|
|
|
|
{416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
|
|
|
|
|
{544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
|
|
|
|
|
{672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
|
|
|
|
|
{800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
|
|
|
|
|
{1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
|
|
|
|
|
{1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
|
|
|
|
|
{1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
|
|
|
|
|
{2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
|
|
|
|
|
{3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
|
|
|
|
|
{4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
|
|
|
|
|
{7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
|
|
|
|
|
{12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
|
|
|
|
|
{18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
|
|
|
|
|
{30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
|
|
|
|
|
{49152, 0x011e}, {61440, 0x011f}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
u32 mpc_i2c_get_sec_cfg_8xxx(void)
|
|
|
|
|
{
|
|
|
|
|
struct device_node *node = NULL;
|
|
|
|
|
u32 __iomem *reg;
|
|
|
|
|
u32 val = 0;
|
|
|
|
|
|
|
|
|
|
node = of_find_node_by_name(NULL, "global-utilities");
|
|
|
|
|
if (node) {
|
|
|
|
|
const u32 *prop = of_get_property(node, "reg", NULL);
|
|
|
|
|
if (prop) {
|
|
|
|
|
/*
|
|
|
|
|
* Map and check POR Device Status Register 2
|
|
|
|
|
* (PORDEVSR2) at 0xE0014
|
|
|
|
|
*/
|
|
|
|
|
reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
|
|
|
|
|
if (!reg)
|
|
|
|
|
printk(KERN_ERR
|
|
|
|
|
"Error: couldn't map PORDEVSR2\n");
|
|
|
|
|
else
|
|
|
|
|
val = in_be32(reg) & 0x00000080; /* sec-cfg */
|
|
|
|
|
iounmap(reg);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (node)
|
|
|
|
|
of_node_put(node);
|
|
|
|
|
|
|
|
|
|
return val;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
|
|
|
|
|
{
|
|
|
|
|
const struct mpc_i2c_divider *div = NULL;
|
|
|
|
|
u32 divider;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
if (!clock)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/* Determine proper divider value */
|
|
|
|
|
if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
|
|
|
|
|
prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
|
|
|
|
|
if (!prescaler)
|
|
|
|
|
prescaler = 1;
|
|
|
|
|
|
|
|
|
|
divider = fsl_get_sys_freq() / clock / prescaler;
|
|
|
|
|
|
|
|
|
|
pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
|
|
|
|
|
fsl_get_sys_freq(), clock, divider);
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We want to choose an FDR/DFSR that generates an I2C bus speed that
|
|
|
|
|
* is equal to or lower than the requested speed.
|
|
|
|
|
*/
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
|
|
|
|
|
div = &mpc_i2c_dividers_8xxx[i];
|
|
|
|
|
if (div->divider >= divider)
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return div ? (int)div->fdr : -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mpc_i2c_setclock_8xxx(struct device_node *node,
|
|
|
|
|
struct mpc_i2c *i2c,
|
|
|
|
|
u32 clock, u32 prescaler)
|
|
|
|
|
{
|
|
|
|
|
int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
|
|
|
|
|
|
|
|
|
|
if (fdr < 0)
|
|
|
|
|
fdr = 0x1031; /* backward compatibility */
|
|
|
|
|
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
|
|
|
|
|
writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
|
|
|
|
|
dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
|
|
|
|
|
clock, fdr >> 8, fdr & 0xff);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#else /* !CONFIG_FSL_SOC */
|
|
|
|
|
static void mpc_i2c_setclock_8xxx(struct device_node *node,
|
|
|
|
|
struct mpc_i2c *i2c,
|
|
|
|
|
u32 clock, u32 prescaler)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
|
}
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
|
|
|
#endif /* CONFIG_FSL_SOC */
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
static void mpc_i2c_start(struct mpc_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
/* Clear arbitration */
|
|
|
|
|
writeb(0, i2c->base + MPC_I2C_SR);
|
|
|
|
|
/* Start with MEN */
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void mpc_i2c_stop(struct mpc_i2c *i2c)
|
|
|
|
|
{
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_write(struct mpc_i2c *i2c, int target,
|
2009-04-07 08:20:53 +00:00
|
|
|
const u8 *data, int length, int restart)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
2008-01-27 17:14:52 +00:00
|
|
|
int i, result;
|
2005-04-16 22:20:36 +00:00
|
|
|
unsigned timeout = i2c->adap.timeout;
|
|
|
|
|
u32 flags = restart ? CCR_RSTA : 0;
|
|
|
|
|
|
|
|
|
|
/* Start with MEN */
|
|
|
|
|
if (!restart)
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
|
|
|
|
/* Start as master */
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
|
|
|
|
|
/* Write target byte */
|
|
|
|
|
writeb((target << 1), i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
2008-01-27 17:14:52 +00:00
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
for (i = 0; i < length; i++) {
|
|
|
|
|
/* Write data byte */
|
|
|
|
|
writeb(data[i], i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
2008-01-27 17:14:52 +00:00
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-16 22:20:36 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_read(struct mpc_i2c *i2c, int target,
|
2009-04-07 08:20:53 +00:00
|
|
|
u8 *data, int length, int restart)
|
2005-04-16 22:20:36 +00:00
|
|
|
{
|
|
|
|
|
unsigned timeout = i2c->adap.timeout;
|
2008-01-27 17:14:52 +00:00
|
|
|
int i, result;
|
2005-04-16 22:20:36 +00:00
|
|
|
u32 flags = restart ? CCR_RSTA : 0;
|
|
|
|
|
|
|
|
|
|
/* Start with MEN */
|
|
|
|
|
if (!restart)
|
|
|
|
|
writeccr(i2c, CCR_MEN);
|
|
|
|
|
/* Switch to read - restart */
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
|
|
|
|
|
/* Write target address byte - this time with the read flag set */
|
|
|
|
|
writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
|
|
|
|
|
|
2008-01-27 17:14:52 +00:00
|
|
|
result = i2c_wait(i2c, timeout, 1);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
if (length) {
|
|
|
|
|
if (length == 1)
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
|
|
|
|
|
else
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
|
|
|
|
|
/* Dummy read */
|
|
|
|
|
readb(i2c->base + MPC_I2C_DR);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < length; i++) {
|
2008-01-27 17:14:52 +00:00
|
|
|
result = i2c_wait(i2c, timeout, 0);
|
|
|
|
|
if (result < 0)
|
|
|
|
|
return result;
|
2005-04-16 22:20:36 +00:00
|
|
|
|
|
|
|
|
/* Generate txack on next to last byte */
|
|
|
|
|
if (i == length - 2)
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
|
|
|
|
|
/* Generate stop on last byte */
|
|
|
|
|
if (i == length - 1)
|
|
|
|
|
writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
|
|
|
|
|
data[i] = readb(i2c->base + MPC_I2C_DR);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return length;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
|
|
|
{
|
|
|
|
|
struct i2c_msg *pmsg;
|
|
|
|
|
int i;
|
|
|
|
|
int ret = 0;
|
|
|
|
|
unsigned long orig_jiffies = jiffies;
|
|
|
|
|
struct mpc_i2c *i2c = i2c_get_adapdata(adap);
|
|
|
|
|
|
|
|
|
|
mpc_i2c_start(i2c);
|
|
|
|
|
|
|
|
|
|
/* Allow bus up to 1s to become not busy */
|
|
|
|
|
while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
|
|
|
|
|
if (signal_pending(current)) {
|
2009-04-07 08:20:54 +00:00
|
|
|
dev_dbg(i2c->dev, "Interrupted\n");
|
2007-08-14 16:37:14 +00:00
|
|
|
writeccr(i2c, 0);
|
2005-04-16 22:20:36 +00:00
|
|
|
return -EINTR;
|
|
|
|
|
}
|
|
|
|
|
if (time_after(jiffies, orig_jiffies + HZ)) {
|
2009-04-07 08:20:54 +00:00
|
|
|
dev_dbg(i2c->dev, "timeout\n");
|
2007-07-12 12:12:31 +00:00
|
|
|
if (readb(i2c->base + MPC_I2C_SR) ==
|
|
|
|
|
(CSR_MCF | CSR_MBB | CSR_RXAK))
|
|
|
|
|
mpc_i2c_fixup(i2c);
|
2005-04-16 22:20:36 +00:00
|
|
|
return -EIO;
|
|
|
|
|
}
|
|
|
|
|
schedule();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0; ret >= 0 && i < num; i++) {
|
|
|
|
|
pmsg = &msgs[i];
|
2009-04-07 08:20:54 +00:00
|
|
|
dev_dbg(i2c->dev,
|
|
|
|
|
"Doing %s %d bytes to 0x%02x - %d of %d messages\n",
|
|
|
|
|
pmsg->flags & I2C_M_RD ? "read" : "write",
|
|
|
|
|
pmsg->len, pmsg->addr, i + 1, num);
|
2005-04-16 22:20:36 +00:00
|
|
|
if (pmsg->flags & I2C_M_RD)
|
|
|
|
|
ret =
|
|
|
|
|
mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
|
|
|
|
|
else
|
|
|
|
|
ret =
|
|
|
|
|
mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
|
|
|
|
|
}
|
|
|
|
|
mpc_i2c_stop(i2c);
|
|
|
|
|
return (ret < 0) ? ret : num;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static u32 mpc_functionality(struct i2c_adapter *adap)
|
|
|
|
|
{
|
|
|
|
|
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
|
|
|
|
}
|
|
|
|
|
|
2006-09-03 20:39:46 +00:00
|
|
|
static const struct i2c_algorithm mpc_algo = {
|
2005-04-16 22:20:36 +00:00
|
|
|
.master_xfer = mpc_xfer,
|
|
|
|
|
.functionality = mpc_functionality,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct i2c_adapter mpc_ops = {
|
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.name = "MPC adapter",
|
|
|
|
|
.algo = &mpc_algo,
|
2009-03-28 20:34:43 +00:00
|
|
|
.timeout = HZ,
|
2005-04-16 22:20:36 +00:00
|
|
|
};
|
|
|
|
|
|
2009-04-07 08:20:53 +00:00
|
|
|
static int __devinit fsl_i2c_probe(struct of_device *op,
|
|
|
|
|
const struct of_device_id *match)
|
2005-07-27 18:43:26 +00:00
|
|
|
{
|
|
|
|
|
struct mpc_i2c *i2c;
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
|
|
|
const u32 *prop;
|
|
|
|
|
u32 clock = 0;
|
|
|
|
|
int result = 0;
|
|
|
|
|
int plen;
|
2005-07-27 18:43:26 +00:00
|
|
|
|
2008-01-27 17:14:52 +00:00
|
|
|
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
|
|
|
|
|
if (!i2c)
|
2005-07-27 18:43:26 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
2009-04-07 08:20:54 +00:00
|
|
|
i2c->dev = &op->dev; /* for debug and error output */
|
|
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
init_waitqueue_head(&i2c->queue);
|
2005-07-27 18:43:26 +00:00
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
i2c->base = of_iomap(op->node, 0);
|
2005-07-27 18:43:26 +00:00
|
|
|
if (!i2c->base) {
|
2009-04-07 08:20:54 +00:00
|
|
|
dev_err(i2c->dev, "failed to map controller\n");
|
2005-07-27 18:43:26 +00:00
|
|
|
result = -ENOMEM;
|
|
|
|
|
goto fail_map;
|
|
|
|
|
}
|
|
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
i2c->irq = irq_of_parse_and_map(op->node, 0);
|
|
|
|
|
if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
|
|
|
|
|
result = request_irq(i2c->irq, mpc_i2c_isr,
|
|
|
|
|
IRQF_SHARED, "i2c-mpc", i2c);
|
|
|
|
|
if (result < 0) {
|
2009-04-07 08:20:54 +00:00
|
|
|
dev_err(i2c->dev, "failed to attach interrupt\n");
|
2008-06-30 23:01:26 +00:00
|
|
|
goto fail_request;
|
2005-07-27 18:43:26 +00:00
|
|
|
}
|
2008-06-30 23:01:26 +00:00
|
|
|
}
|
2009-04-07 08:20:53 +00:00
|
|
|
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
|
|
|
if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
|
|
|
|
|
prop = of_get_property(op->node, "clock-frequency", &plen);
|
|
|
|
|
if (prop && plen == sizeof(u32))
|
|
|
|
|
clock = *prop;
|
|
|
|
|
|
|
|
|
|
if (match->data) {
|
|
|
|
|
struct mpc_i2c_match_data *data =
|
|
|
|
|
(struct mpc_i2c_match_data *)match->data;
|
|
|
|
|
data->setclock(op->node, i2c, clock, data->prescaler);
|
|
|
|
|
} else {
|
|
|
|
|
/* Backwards compatibility */
|
|
|
|
|
if (of_get_property(op->node, "dfsrr", NULL))
|
|
|
|
|
mpc_i2c_setclock_8xxx(op->node, i2c,
|
|
|
|
|
clock, 0);
|
|
|
|
|
}
|
|
|
|
|
}
|
2008-06-30 23:01:26 +00:00
|
|
|
|
|
|
|
|
dev_set_drvdata(&op->dev, i2c);
|
2005-07-27 18:43:26 +00:00
|
|
|
|
|
|
|
|
i2c->adap = mpc_ops;
|
|
|
|
|
i2c_set_adapdata(&i2c->adap, i2c);
|
2008-06-30 23:01:26 +00:00
|
|
|
i2c->adap.dev.parent = &op->dev;
|
|
|
|
|
|
|
|
|
|
result = i2c_add_adapter(&i2c->adap);
|
|
|
|
|
if (result < 0) {
|
2009-04-07 08:20:54 +00:00
|
|
|
dev_err(i2c->dev, "failed to add adapter\n");
|
2005-07-27 18:43:26 +00:00
|
|
|
goto fail_add;
|
|
|
|
|
}
|
2008-06-30 23:01:26 +00:00
|
|
|
of_register_i2c_devices(&i2c->adap, op->node);
|
2005-07-27 18:43:26 +00:00
|
|
|
|
|
|
|
|
return result;
|
|
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
fail_add:
|
|
|
|
|
dev_set_drvdata(&op->dev, NULL);
|
|
|
|
|
free_irq(i2c->irq, i2c);
|
|
|
|
|
fail_request:
|
|
|
|
|
irq_dispose_mapping(i2c->irq);
|
2009-04-07 08:20:53 +00:00
|
|
|
iounmap(i2c->base);
|
2008-06-30 23:01:26 +00:00
|
|
|
fail_map:
|
2005-07-27 18:43:26 +00:00
|
|
|
kfree(i2c);
|
|
|
|
|
return result;
|
|
|
|
|
};
|
|
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
static int __devexit fsl_i2c_remove(struct of_device *op)
|
2005-07-27 18:43:26 +00:00
|
|
|
{
|
2008-06-30 23:01:26 +00:00
|
|
|
struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
|
2005-07-27 18:43:26 +00:00
|
|
|
|
|
|
|
|
i2c_del_adapter(&i2c->adap);
|
2008-06-30 23:01:26 +00:00
|
|
|
dev_set_drvdata(&op->dev, NULL);
|
2005-07-27 18:43:26 +00:00
|
|
|
|
2008-05-11 18:37:04 +00:00
|
|
|
if (i2c->irq != NO_IRQ)
|
2005-07-27 18:43:26 +00:00
|
|
|
free_irq(i2c->irq, i2c);
|
|
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
irq_dispose_mapping(i2c->irq);
|
2005-07-27 18:43:26 +00:00
|
|
|
iounmap(i2c->base);
|
|
|
|
|
kfree(i2c);
|
|
|
|
|
return 0;
|
|
|
|
|
};
|
|
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
static const struct of_device_id mpc_i2c_of_match[] = {
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
|
|
|
{.compatible = "mpc5200-i2c",
|
|
|
|
|
.data = &(struct mpc_i2c_match_data) {
|
|
|
|
|
.setclock = mpc_i2c_setclock_52xx,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{.compatible = "fsl,mpc5200b-i2c",
|
|
|
|
|
.data = &(struct mpc_i2c_match_data) {
|
|
|
|
|
.setclock = mpc_i2c_setclock_52xx,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{.compatible = "fsl,mpc5200-i2c",
|
|
|
|
|
.data = &(struct mpc_i2c_match_data) {
|
|
|
|
|
.setclock = mpc_i2c_setclock_52xx,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{.compatible = "fsl,mpc8313-i2c",
|
|
|
|
|
.data = &(struct mpc_i2c_match_data) {
|
|
|
|
|
.setclock = mpc_i2c_setclock_8xxx,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{.compatible = "fsl,mpc8543-i2c",
|
|
|
|
|
.data = &(struct mpc_i2c_match_data) {
|
|
|
|
|
.setclock = mpc_i2c_setclock_8xxx,
|
|
|
|
|
.prescaler = 2,
|
|
|
|
|
},
|
|
|
|
|
},
|
|
|
|
|
{.compatible = "fsl,mpc8544-i2c",
|
|
|
|
|
.data = &(struct mpc_i2c_match_data) {
|
|
|
|
|
.setclock = mpc_i2c_setclock_8xxx,
|
|
|
|
|
.prescaler = 3,
|
|
|
|
|
},
|
|
|
|
|
/* Backward compatibility */
|
|
|
|
|
},
|
|
|
|
|
{.compatible = "fsl-i2c", },
|
2008-06-30 23:01:26 +00:00
|
|
|
{},
|
|
|
|
|
};
|
i2c: i2c-mpc: make I2C bus speed configurable
This patch makes the I2C bus speed configurable by using the I2C node
property "clock-frequency". If the property is not defined, the old
fixed clock settings will be used for backward comptibility.
The generic I2C clock properties, especially the CPU-specific source
clock pre-scaler are defined via the OF match table:
static const struct of_device_id mpc_i2c_of_match[] = {
...
{.compatible = "fsl,mpc8543-i2c",
.data = &(struct fsl_i2c_match_data) {
.setclock = mpc_i2c_setclock_8xxx,
.prescaler = 2,
},
},
The "data" field defines the relevant I2C setclock function and the
relevant pre-scaler for the I2C source clock frequency.
It uses arch-specific tables and functions to determine resonable
Freqency Divider Register (fdr) values for MPC83xx, MPC85xx, MPC86xx,
MPC5200 and MPC5200B.
The i2c->flags field and the corresponding FSL_I2C_DEV_* definitions
have been removed as they are obsolete.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
2009-04-07 08:20:55 +00:00
|
|
|
|
2008-06-30 23:01:26 +00:00
|
|
|
MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
|
|
|
|
|
|
2008-04-22 20:16:49 +00:00
|
|
|
|
2005-07-27 18:43:26 +00:00
|
|
|
/* Structure for a device driver */
|
2008-06-30 23:01:26 +00:00
|
|
|
static struct of_platform_driver mpc_i2c_driver = {
|
|
|
|
|
.match_table = mpc_i2c_of_match,
|
|
|
|
|
.probe = fsl_i2c_probe,
|
|
|
|
|
.remove = __devexit_p(fsl_i2c_remove),
|
|
|
|
|
.driver = {
|
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
|
.name = DRV_NAME,
|
2005-11-09 22:32:44 +00:00
|
|
|
},
|
2005-07-27 18:43:26 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init fsl_i2c_init(void)
|
|
|
|
|
{
|
2008-06-30 23:01:26 +00:00
|
|
|
int rv;
|
|
|
|
|
|
|
|
|
|
rv = of_register_platform_driver(&mpc_i2c_driver);
|
|
|
|
|
if (rv)
|
2009-04-07 08:20:53 +00:00
|
|
|
printk(KERN_ERR DRV_NAME
|
2008-06-30 23:01:26 +00:00
|
|
|
" of_register_platform_driver failed (%i)\n", rv);
|
|
|
|
|
return rv;
|
2005-07-27 18:43:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void __exit fsl_i2c_exit(void)
|
|
|
|
|
{
|
2008-06-30 23:01:26 +00:00
|
|
|
of_unregister_platform_driver(&mpc_i2c_driver);
|
2005-07-27 18:43:26 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
module_init(fsl_i2c_init);
|
|
|
|
|
module_exit(fsl_i2c_exit);
|
|
|
|
|
|
2005-04-16 22:20:36 +00:00
|
|
|
MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
|
2009-04-07 08:20:53 +00:00
|
|
|
MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
|
|
|
|
|
"MPC824x/85xx/52xx processors");
|
2005-04-16 22:20:36 +00:00
|
|
|
MODULE_LICENSE("GPL");
|