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559 lines
15 KiB
C
559 lines
15 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
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*
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* Authors:
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* Serge Semin <Sergey.Semin@baikalelectronics.ru>
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* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
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*
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* Baikal-T1 CCU PLL interface driver
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*/
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#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
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#include <linux/kernel.h>
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#include <linux/printk.h>
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#include <linux/limits.h>
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#include <linux/bits.h>
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#include <linux/bitfield.h>
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#include <linux/slab.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/spinlock.h>
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#include <linux/regmap.h>
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#include <linux/iopoll.h>
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#include <linux/time64.h>
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#include <linux/rational.h>
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#include <linux/debugfs.h>
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#include "ccu-pll.h"
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#define CCU_PLL_CTL 0x000
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#define CCU_PLL_CTL_EN BIT(0)
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#define CCU_PLL_CTL_RST BIT(1)
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#define CCU_PLL_CTL_CLKR_FLD 2
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#define CCU_PLL_CTL_CLKR_MASK GENMASK(7, CCU_PLL_CTL_CLKR_FLD)
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#define CCU_PLL_CTL_CLKF_FLD 8
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#define CCU_PLL_CTL_CLKF_MASK GENMASK(20, CCU_PLL_CTL_CLKF_FLD)
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#define CCU_PLL_CTL_CLKOD_FLD 21
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#define CCU_PLL_CTL_CLKOD_MASK GENMASK(24, CCU_PLL_CTL_CLKOD_FLD)
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#define CCU_PLL_CTL_BYPASS BIT(30)
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#define CCU_PLL_CTL_LOCK BIT(31)
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#define CCU_PLL_CTL1 0x004
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#define CCU_PLL_CTL1_BWADJ_FLD 3
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#define CCU_PLL_CTL1_BWADJ_MASK GENMASK(14, CCU_PLL_CTL1_BWADJ_FLD)
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#define CCU_PLL_LOCK_CHECK_RETRIES 50
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#define CCU_PLL_NR_MAX \
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((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
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#define CCU_PLL_NF_MAX \
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((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
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#define CCU_PLL_OD_MAX \
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((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
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#define CCU_PLL_NB_MAX \
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((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
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#define CCU_PLL_FDIV_MIN 427000UL
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#define CCU_PLL_FDIV_MAX 3500000000UL
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#define CCU_PLL_FOUT_MIN 200000000UL
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#define CCU_PLL_FOUT_MAX 2500000000UL
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#define CCU_PLL_FVCO_MIN 700000000UL
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#define CCU_PLL_FVCO_MAX 3500000000UL
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#define CCU_PLL_CLKOD_FACTOR 2
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static inline unsigned long ccu_pll_lock_delay_us(unsigned long ref_clk,
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unsigned long nr)
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{
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u64 us = 500ULL * nr * USEC_PER_SEC;
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do_div(us, ref_clk);
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return us;
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}
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static inline unsigned long ccu_pll_calc_freq(unsigned long ref_clk,
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unsigned long nr,
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unsigned long nf,
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unsigned long od)
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{
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u64 tmp = ref_clk;
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do_div(tmp, nr);
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tmp *= nf;
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do_div(tmp, od);
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return tmp;
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}
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static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk,
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unsigned long nr)
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{
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unsigned long ud, ut;
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u32 val;
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ud = ccu_pll_lock_delay_us(ref_clk, nr);
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ut = ud * CCU_PLL_LOCK_CHECK_RETRIES;
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regmap_update_bits(pll->sys_regs, pll->reg_ctl,
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CCU_PLL_CTL_RST, CCU_PLL_CTL_RST);
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return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val,
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val & CCU_PLL_CTL_LOCK, ud, ut);
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}
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static int ccu_pll_enable(struct clk_hw *hw)
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{
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struct clk_hw *parent_hw = clk_hw_get_parent(hw);
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struct ccu_pll *pll = to_ccu_pll(hw);
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unsigned long flags;
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u32 val = 0;
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int ret;
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if (!parent_hw) {
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pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
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return -EINVAL;
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}
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regmap_read(pll->sys_regs, pll->reg_ctl, &val);
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if (val & CCU_PLL_CTL_EN)
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return 0;
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spin_lock_irqsave(&pll->lock, flags);
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regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN);
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ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw),
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FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1);
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spin_unlock_irqrestore(&pll->lock, flags);
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if (ret)
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pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
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return ret;
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}
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static void ccu_pll_disable(struct clk_hw *hw)
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{
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struct ccu_pll *pll = to_ccu_pll(hw);
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unsigned long flags;
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spin_lock_irqsave(&pll->lock, flags);
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regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0);
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spin_unlock_irqrestore(&pll->lock, flags);
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}
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static int ccu_pll_is_enabled(struct clk_hw *hw)
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{
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struct ccu_pll *pll = to_ccu_pll(hw);
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u32 val = 0;
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regmap_read(pll->sys_regs, pll->reg_ctl, &val);
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return !!(val & CCU_PLL_CTL_EN);
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}
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static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_pll *pll = to_ccu_pll(hw);
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unsigned long nr, nf, od;
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u32 val = 0;
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regmap_read(pll->sys_regs, pll->reg_ctl, &val);
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nr = FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1;
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nf = FIELD_GET(CCU_PLL_CTL_CLKF_MASK, val) + 1;
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od = FIELD_GET(CCU_PLL_CTL_CLKOD_MASK, val) + 1;
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return ccu_pll_calc_freq(parent_rate, nr, nf, od);
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}
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static void ccu_pll_calc_factors(unsigned long rate, unsigned long parent_rate,
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unsigned long *nr, unsigned long *nf,
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unsigned long *od)
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{
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unsigned long err, freq, min_err = ULONG_MAX;
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unsigned long num, denom, n1, d1, nri;
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unsigned long nr_max, nf_max, od_max;
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/*
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* Make sure PLL is working with valid input signal (Fdiv). If
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* you want to speed the function up just reduce CCU_PLL_NR_MAX.
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* This will cause a worse approximation though.
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*/
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nri = (parent_rate / CCU_PLL_FDIV_MAX) + 1;
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nr_max = min(parent_rate / CCU_PLL_FDIV_MIN, CCU_PLL_NR_MAX);
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/*
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* Find a closest [nr;nf;od] vector taking into account the
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* limitations like: 1) 700MHz <= Fvco <= 3.5GHz, 2) PLL Od is
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* either 1 or even number within the acceptable range (alas 1s
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* is also excluded by the next loop).
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*/
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for (; nri <= nr_max; ++nri) {
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/* Use Od factor to fulfill the limitation 2). */
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num = CCU_PLL_CLKOD_FACTOR * rate;
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denom = parent_rate / nri;
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/*
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* Make sure Fvco is within the acceptable range to fulfill
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* the condition 1). Note due to the CCU_PLL_CLKOD_FACTOR value
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* the actual upper limit is also divided by that factor.
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* It's not big problem for us since practically there is no
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* need in clocks with that high frequency.
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*/
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nf_max = min(CCU_PLL_FVCO_MAX / denom, CCU_PLL_NF_MAX);
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od_max = CCU_PLL_OD_MAX / CCU_PLL_CLKOD_FACTOR;
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/*
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* Bypass the out-of-bound values, which can't be properly
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* handled by the rational fraction approximation algorithm.
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*/
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if (num / denom >= nf_max) {
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n1 = nf_max;
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d1 = 1;
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} else if (denom / num >= od_max) {
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n1 = 1;
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d1 = od_max;
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} else {
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rational_best_approximation(num, denom, nf_max, od_max,
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&n1, &d1);
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}
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/* Select the best approximation of the target rate. */
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freq = ccu_pll_calc_freq(parent_rate, nri, n1, d1);
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err = abs((int64_t)freq - num);
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if (err < min_err) {
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min_err = err;
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*nr = nri;
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*nf = n1;
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*od = CCU_PLL_CLKOD_FACTOR * d1;
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}
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}
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}
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static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long nr = 1, nf = 1, od = 1;
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ccu_pll_calc_factors(rate, *parent_rate, &nr, &nf, &od);
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return ccu_pll_calc_freq(*parent_rate, nr, nf, od);
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}
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/*
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* This method is used for PLLs, which support the on-the-fly dividers
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* adjustment. So there is no need in gating such clocks.
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*/
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static int ccu_pll_set_rate_reset(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_pll *pll = to_ccu_pll(hw);
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unsigned long nr, nf, od;
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unsigned long flags;
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u32 mask, val;
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int ret;
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ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
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mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
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CCU_PLL_CTL_CLKOD_MASK;
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val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
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FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
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FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
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spin_lock_irqsave(&pll->lock, flags);
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regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
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ret = ccu_pll_reset(pll, parent_rate, nr);
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spin_unlock_irqrestore(&pll->lock, flags);
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if (ret)
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pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
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return ret;
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}
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/*
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* This method is used for PLLs, which don't support the on-the-fly dividers
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* adjustment. So the corresponding clocks are supposed to be gated first.
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*/
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static int ccu_pll_set_rate_norst(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_pll *pll = to_ccu_pll(hw);
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unsigned long nr, nf, od;
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unsigned long flags;
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u32 mask, val;
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ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
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/*
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* Disable PLL if it was enabled by default or left enabled by the
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* system bootloader.
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*/
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mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
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CCU_PLL_CTL_CLKOD_MASK | CCU_PLL_CTL_EN;
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val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
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FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
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FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
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spin_lock_irqsave(&pll->lock, flags);
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regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
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spin_unlock_irqrestore(&pll->lock, flags);
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return 0;
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}
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#ifdef CONFIG_DEBUG_FS
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struct ccu_pll_dbgfs_bit {
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struct ccu_pll *pll;
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const char *name;
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unsigned int reg;
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u32 mask;
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};
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struct ccu_pll_dbgfs_fld {
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struct ccu_pll *pll;
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const char *name;
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unsigned int reg;
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unsigned int lsb;
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u32 mask;
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u32 min;
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u32 max;
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};
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#define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \
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{ \
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.name = _name, \
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.reg = _reg, \
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.mask = _mask \
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}
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#define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \
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{ \
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.name = _name, \
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.reg = _reg, \
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.lsb = _lsb, \
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.mask = _mask, \
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.min = _min, \
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.max = _max \
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}
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static const struct ccu_pll_dbgfs_bit ccu_pll_bits[] = {
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CCU_PLL_DBGFS_BIT_ATTR("pll_en", CCU_PLL_CTL, CCU_PLL_CTL_EN),
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CCU_PLL_DBGFS_BIT_ATTR("pll_rst", CCU_PLL_CTL, CCU_PLL_CTL_RST),
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CCU_PLL_DBGFS_BIT_ATTR("pll_bypass", CCU_PLL_CTL, CCU_PLL_CTL_BYPASS),
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CCU_PLL_DBGFS_BIT_ATTR("pll_lock", CCU_PLL_CTL, CCU_PLL_CTL_LOCK)
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};
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#define CCU_PLL_DBGFS_BIT_NUM ARRAY_SIZE(ccu_pll_bits)
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static const struct ccu_pll_dbgfs_fld ccu_pll_flds[] = {
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CCU_PLL_DBGFS_FLD_ATTR("pll_nr", CCU_PLL_CTL, CCU_PLL_CTL_CLKR_FLD,
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CCU_PLL_CTL_CLKR_MASK, 1, CCU_PLL_NR_MAX),
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CCU_PLL_DBGFS_FLD_ATTR("pll_nf", CCU_PLL_CTL, CCU_PLL_CTL_CLKF_FLD,
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CCU_PLL_CTL_CLKF_MASK, 1, CCU_PLL_NF_MAX),
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CCU_PLL_DBGFS_FLD_ATTR("pll_od", CCU_PLL_CTL, CCU_PLL_CTL_CLKOD_FLD,
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CCU_PLL_CTL_CLKOD_MASK, 1, CCU_PLL_OD_MAX),
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CCU_PLL_DBGFS_FLD_ATTR("pll_nb", CCU_PLL_CTL1, CCU_PLL_CTL1_BWADJ_FLD,
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CCU_PLL_CTL1_BWADJ_MASK, 1, CCU_PLL_NB_MAX)
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};
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#define CCU_PLL_DBGFS_FLD_NUM ARRAY_SIZE(ccu_pll_flds)
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/*
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* It can be dangerous to change the PLL settings behind clock framework back,
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* therefore we don't provide any kernel config based compile time option for
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* this feature to enable.
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*/
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#undef CCU_PLL_ALLOW_WRITE_DEBUGFS
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#ifdef CCU_PLL_ALLOW_WRITE_DEBUGFS
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static int ccu_pll_dbgfs_bit_set(void *priv, u64 val)
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{
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const struct ccu_pll_dbgfs_bit *bit = priv;
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struct ccu_pll *pll = bit->pll;
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unsigned long flags;
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spin_lock_irqsave(&pll->lock, flags);
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regmap_update_bits(pll->sys_regs, pll->reg_ctl + bit->reg,
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bit->mask, val ? bit->mask : 0);
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spin_unlock_irqrestore(&pll->lock, flags);
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return 0;
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}
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static int ccu_pll_dbgfs_fld_set(void *priv, u64 val)
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{
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struct ccu_pll_dbgfs_fld *fld = priv;
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struct ccu_pll *pll = fld->pll;
|
||
|
unsigned long flags;
|
||
|
u32 data;
|
||
|
|
||
|
val = clamp_t(u64, val, fld->min, fld->max);
|
||
|
data = ((val - 1) << fld->lsb) & fld->mask;
|
||
|
|
||
|
spin_lock_irqsave(&pll->lock, flags);
|
||
|
regmap_update_bits(pll->sys_regs, pll->reg_ctl + fld->reg, fld->mask,
|
||
|
data);
|
||
|
spin_unlock_irqrestore(&pll->lock, flags);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
#define ccu_pll_dbgfs_mode 0644
|
||
|
|
||
|
#else /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
|
||
|
|
||
|
#define ccu_pll_dbgfs_bit_set NULL
|
||
|
#define ccu_pll_dbgfs_fld_set NULL
|
||
|
#define ccu_pll_dbgfs_mode 0444
|
||
|
|
||
|
#endif /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
|
||
|
|
||
|
static int ccu_pll_dbgfs_bit_get(void *priv, u64 *val)
|
||
|
{
|
||
|
struct ccu_pll_dbgfs_bit *bit = priv;
|
||
|
struct ccu_pll *pll = bit->pll;
|
||
|
u32 data = 0;
|
||
|
|
||
|
regmap_read(pll->sys_regs, pll->reg_ctl + bit->reg, &data);
|
||
|
*val = !!(data & bit->mask);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_bit_fops,
|
||
|
ccu_pll_dbgfs_bit_get, ccu_pll_dbgfs_bit_set, "%llu\n");
|
||
|
|
||
|
static int ccu_pll_dbgfs_fld_get(void *priv, u64 *val)
|
||
|
{
|
||
|
struct ccu_pll_dbgfs_fld *fld = priv;
|
||
|
struct ccu_pll *pll = fld->pll;
|
||
|
u32 data = 0;
|
||
|
|
||
|
regmap_read(pll->sys_regs, pll->reg_ctl + fld->reg, &data);
|
||
|
*val = ((data & fld->mask) >> fld->lsb) + 1;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_fld_fops,
|
||
|
ccu_pll_dbgfs_fld_get, ccu_pll_dbgfs_fld_set, "%llu\n");
|
||
|
|
||
|
static void ccu_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||
|
{
|
||
|
struct ccu_pll *pll = to_ccu_pll(hw);
|
||
|
struct ccu_pll_dbgfs_bit *bits;
|
||
|
struct ccu_pll_dbgfs_fld *flds;
|
||
|
int idx;
|
||
|
|
||
|
bits = kcalloc(CCU_PLL_DBGFS_BIT_NUM, sizeof(*bits), GFP_KERNEL);
|
||
|
if (!bits)
|
||
|
return;
|
||
|
|
||
|
for (idx = 0; idx < CCU_PLL_DBGFS_BIT_NUM; ++idx) {
|
||
|
bits[idx] = ccu_pll_bits[idx];
|
||
|
bits[idx].pll = pll;
|
||
|
|
||
|
debugfs_create_file_unsafe(bits[idx].name, ccu_pll_dbgfs_mode,
|
||
|
dentry, &bits[idx],
|
||
|
&ccu_pll_dbgfs_bit_fops);
|
||
|
}
|
||
|
|
||
|
flds = kcalloc(CCU_PLL_DBGFS_FLD_NUM, sizeof(*flds), GFP_KERNEL);
|
||
|
if (!flds)
|
||
|
return;
|
||
|
|
||
|
for (idx = 0; idx < CCU_PLL_DBGFS_FLD_NUM; ++idx) {
|
||
|
flds[idx] = ccu_pll_flds[idx];
|
||
|
flds[idx].pll = pll;
|
||
|
|
||
|
debugfs_create_file_unsafe(flds[idx].name, ccu_pll_dbgfs_mode,
|
||
|
dentry, &flds[idx],
|
||
|
&ccu_pll_dbgfs_fld_fops);
|
||
|
}
|
||
|
}
|
||
|
|
||
|
#else /* !CONFIG_DEBUG_FS */
|
||
|
|
||
|
#define ccu_pll_debug_init NULL
|
||
|
|
||
|
#endif /* !CONFIG_DEBUG_FS */
|
||
|
|
||
|
static const struct clk_ops ccu_pll_gate_to_set_ops = {
|
||
|
.enable = ccu_pll_enable,
|
||
|
.disable = ccu_pll_disable,
|
||
|
.is_enabled = ccu_pll_is_enabled,
|
||
|
.recalc_rate = ccu_pll_recalc_rate,
|
||
|
.round_rate = ccu_pll_round_rate,
|
||
|
.set_rate = ccu_pll_set_rate_norst,
|
||
|
.debug_init = ccu_pll_debug_init
|
||
|
};
|
||
|
|
||
|
static const struct clk_ops ccu_pll_straight_set_ops = {
|
||
|
.enable = ccu_pll_enable,
|
||
|
.disable = ccu_pll_disable,
|
||
|
.is_enabled = ccu_pll_is_enabled,
|
||
|
.recalc_rate = ccu_pll_recalc_rate,
|
||
|
.round_rate = ccu_pll_round_rate,
|
||
|
.set_rate = ccu_pll_set_rate_reset,
|
||
|
.debug_init = ccu_pll_debug_init
|
||
|
};
|
||
|
|
||
|
struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *pll_init)
|
||
|
{
|
||
|
struct clk_parent_data parent_data = { };
|
||
|
struct clk_init_data hw_init = { };
|
||
|
struct ccu_pll *pll;
|
||
|
int ret;
|
||
|
|
||
|
if (!pll_init)
|
||
|
return ERR_PTR(-EINVAL);
|
||
|
|
||
|
pll = kzalloc(sizeof(*pll), GFP_KERNEL);
|
||
|
if (!pll)
|
||
|
return ERR_PTR(-ENOMEM);
|
||
|
|
||
|
/*
|
||
|
* Note since Baikal-T1 System Controller registers are MMIO-backed
|
||
|
* we won't check the regmap IO operations return status, because it
|
||
|
* must be zero anyway.
|
||
|
*/
|
||
|
pll->hw.init = &hw_init;
|
||
|
pll->reg_ctl = pll_init->base + CCU_PLL_CTL;
|
||
|
pll->reg_ctl1 = pll_init->base + CCU_PLL_CTL1;
|
||
|
pll->sys_regs = pll_init->sys_regs;
|
||
|
pll->id = pll_init->id;
|
||
|
spin_lock_init(&pll->lock);
|
||
|
|
||
|
hw_init.name = pll_init->name;
|
||
|
hw_init.flags = pll_init->flags;
|
||
|
|
||
|
if (hw_init.flags & CLK_SET_RATE_GATE)
|
||
|
hw_init.ops = &ccu_pll_gate_to_set_ops;
|
||
|
else
|
||
|
hw_init.ops = &ccu_pll_straight_set_ops;
|
||
|
|
||
|
if (!pll_init->parent_name) {
|
||
|
ret = -EINVAL;
|
||
|
goto err_free_pll;
|
||
|
}
|
||
|
parent_data.fw_name = pll_init->parent_name;
|
||
|
hw_init.parent_data = &parent_data;
|
||
|
hw_init.num_parents = 1;
|
||
|
|
||
|
ret = of_clk_hw_register(pll_init->np, &pll->hw);
|
||
|
if (ret)
|
||
|
goto err_free_pll;
|
||
|
|
||
|
return pll;
|
||
|
|
||
|
err_free_pll:
|
||
|
kfree(pll);
|
||
|
|
||
|
return ERR_PTR(ret);
|
||
|
}
|
||
|
|
||
|
void ccu_pll_hw_unregister(struct ccu_pll *pll)
|
||
|
{
|
||
|
clk_hw_unregister(&pll->hw);
|
||
|
|
||
|
kfree(pll);
|
||
|
}
|