crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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/* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
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//
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// This file is dual-licensed, meaning that you can use it under your
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// choice of either of the following two licenses:
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//
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// Copyright 2023 The OpenSSL Project Authors. All Rights Reserved.
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//
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// Licensed under the Apache License 2.0 (the "License"). You can obtain
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// a copy in the file LICENSE in the source distribution or at
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// https://www.openssl.org/source/license.html
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//
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// or
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//
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// Copyright (c) 2023, Christoph Müllner <christoph.muellner@vrull.eu>
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// Copyright (c) 2023, Phoebe Chen <phoebe.chen@sifive.com>
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// Copyright (c) 2023, Jerry Shih <jerry.shih@sifive.com>
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// Copyright 2024 Google LLC
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// The generated code of this file depends on the following RISC-V extensions:
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// - RV64I
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// - RISC-V Vector ('V') with VLEN >= 128
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// - RISC-V Vector AES block cipher extension ('Zvkned')
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#include <linux/linkage.h>
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.text
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.option arch, +zvkned
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#include "aes-macros.S"
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#define KEYP a0
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#define INP a1
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#define OUTP a2
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#define LEN a3
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#define IVP a4
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.macro __aes_crypt_zvkned enc, keylen
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vle32.v v16, (INP)
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aes_crypt v16, \enc, \keylen
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vse32.v v16, (OUTP)
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ret
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.endm
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.macro aes_crypt_zvkned enc
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aes_begin KEYP, 128f, 192f
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__aes_crypt_zvkned \enc, 256
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128:
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__aes_crypt_zvkned \enc, 128
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192:
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__aes_crypt_zvkned \enc, 192
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.endm
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// void aes_encrypt_zvkned(const struct crypto_aes_ctx *key,
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// const u8 in[16], u8 out[16]);
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SYM_FUNC_START(aes_encrypt_zvkned)
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aes_crypt_zvkned 1
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SYM_FUNC_END(aes_encrypt_zvkned)
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// Same prototype and calling convention as the encryption function
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SYM_FUNC_START(aes_decrypt_zvkned)
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aes_crypt_zvkned 0
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SYM_FUNC_END(aes_decrypt_zvkned)
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.macro __aes_ecb_crypt enc, keylen
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srli t0, LEN, 2
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// t0 is the remaining length in 32-bit words. It's a multiple of 4.
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1:
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vsetvli t1, t0, e32, m8, ta, ma
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sub t0, t0, t1 // Subtract number of words processed
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slli t1, t1, 2 // Words to bytes
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vle32.v v16, (INP)
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aes_crypt v16, \enc, \keylen
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vse32.v v16, (OUTP)
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add INP, INP, t1
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add OUTP, OUTP, t1
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bnez t0, 1b
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ret
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.endm
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.macro aes_ecb_crypt enc
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aes_begin KEYP, 128f, 192f
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__aes_ecb_crypt \enc, 256
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128:
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__aes_ecb_crypt \enc, 128
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192:
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__aes_ecb_crypt \enc, 192
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.endm
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// void aes_ecb_encrypt_zvkned(const struct crypto_aes_ctx *key,
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// const u8 *in, u8 *out, size_t len);
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//
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// |len| must be nonzero and a multiple of 16 (AES_BLOCK_SIZE).
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SYM_FUNC_START(aes_ecb_encrypt_zvkned)
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aes_ecb_crypt 1
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SYM_FUNC_END(aes_ecb_encrypt_zvkned)
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// Same prototype and calling convention as the encryption function
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SYM_FUNC_START(aes_ecb_decrypt_zvkned)
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aes_ecb_crypt 0
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SYM_FUNC_END(aes_ecb_decrypt_zvkned)
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.macro aes_cbc_encrypt keylen
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vle32.v v16, (IVP) // Load IV
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1:
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vle32.v v17, (INP) // Load plaintext block
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vxor.vv v16, v16, v17 // XOR with IV or prev ciphertext block
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aes_encrypt v16, \keylen // Encrypt
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vse32.v v16, (OUTP) // Store ciphertext block
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addi INP, INP, 16
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addi OUTP, OUTP, 16
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addi LEN, LEN, -16
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bnez LEN, 1b
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vse32.v v16, (IVP) // Store next IV
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ret
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.endm
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.macro aes_cbc_decrypt keylen
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2024-02-08 06:08:51 +00:00
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srli LEN, LEN, 2 // Convert LEN from bytes to words
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crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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vle32.v v16, (IVP) // Load IV
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1:
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2024-02-08 06:08:51 +00:00
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vsetvli t0, LEN, e32, m4, ta, ma
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vle32.v v20, (INP) // Load ciphertext blocks
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vslideup.vi v16, v20, 4 // Setup prev ciphertext blocks
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addi t1, t0, -4
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vslidedown.vx v24, v20, t1 // Save last ciphertext block
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aes_decrypt v20, \keylen // Decrypt the blocks
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vxor.vv v20, v20, v16 // XOR with prev ciphertext blocks
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vse32.v v20, (OUTP) // Store plaintext blocks
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vmv.v.v v16, v24 // Next "IV" is last ciphertext block
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slli t1, t0, 2 // Words to bytes
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add INP, INP, t1
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add OUTP, OUTP, t1
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sub LEN, LEN, t0
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crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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bnez LEN, 1b
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2024-02-08 06:08:51 +00:00
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vsetivli zero, 4, e32, m1, ta, ma
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crypto: riscv - add vector crypto accelerated AES-{ECB,CBC,CTR,XTS}
Add implementations of AES-ECB, AES-CBC, AES-CTR, and AES-XTS, as well
as bare (single-block) AES, using the RISC-V vector crypto extensions.
The assembly code is derived from OpenSSL code (openssl/openssl#21923)
that was dual-licensed so that it could be reused in the kernel.
Nevertheless, the assembly has been significantly reworked for
integration with the kernel, for example by using regular .S files
instead of the so-called perlasm, using the assembler instead of bare
'.inst', greatly reducing code duplication, supporting AES-192, and
making the code use the same AES key structure as the C code.
Co-developed-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Phoebe Chen <phoebe.chen@sifive.com>
Signed-off-by: Jerry Shih <jerry.shih@sifive.com>
Co-developed-by: Eric Biggers <ebiggers@google.com>
Signed-off-by: Eric Biggers <ebiggers@google.com>
Link: https://lore.kernel.org/r/20240122002024.27477-5-ebiggers@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2024-01-22 00:19:15 +00:00
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vse32.v v16, (IVP) // Store next IV
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ret
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.endm
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// void aes_cbc_encrypt_zvkned(const struct crypto_aes_ctx *key,
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// const u8 *in, u8 *out, size_t len, u8 iv[16]);
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//
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// |len| must be nonzero and a multiple of 16 (AES_BLOCK_SIZE).
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SYM_FUNC_START(aes_cbc_encrypt_zvkned)
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aes_begin KEYP, 128f, 192f
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aes_cbc_encrypt 256
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128:
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aes_cbc_encrypt 128
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192:
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aes_cbc_encrypt 192
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SYM_FUNC_END(aes_cbc_encrypt_zvkned)
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// Same prototype and calling convention as the encryption function
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SYM_FUNC_START(aes_cbc_decrypt_zvkned)
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aes_begin KEYP, 128f, 192f
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aes_cbc_decrypt 256
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128:
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aes_cbc_decrypt 128
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192:
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aes_cbc_decrypt 192
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SYM_FUNC_END(aes_cbc_decrypt_zvkned)
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