linux-stable/drivers/gpu/drm/xe/xe_gpu_scheduler_types.h

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drm/xe: Introduce a new DRM driver for Intel GPUs Xe, is a new driver for Intel GPUs that supports both integrated and discrete platforms starting with Tiger Lake (first Intel Xe Architecture). The code is at a stage where it is already functional and has experimental support for multiple platforms starting from Tiger Lake, with initial support implemented in Mesa (for Iris and Anv, our OpenGL and Vulkan drivers), as well as in NEO (for OpenCL and Level0). The new Xe driver leverages a lot from i915. As for display, the intent is to share the display code with the i915 driver so that there is maximum reuse there. But it is not added in this patch. This initial work is a collaboration of many people and unfortunately the big squashed patch won't fully honor the proper credits. But let's get some git quick stats so we can at least try to preserve some of the credits: Co-developed-by: Matthew Brost <matthew.brost@intel.com> Co-developed-by: Matthew Auld <matthew.auld@intel.com> Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Co-developed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Co-developed-by: Francois Dugast <francois.dugast@intel.com> Co-developed-by: Lucas De Marchi <lucas.demarchi@intel.com> Co-developed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Co-developed-by: Philippe Lecluse <philippe.lecluse@intel.com> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com> Co-developed-by: Jani Nikula <jani.nikula@intel.com> Co-developed-by: José Roberto de Souza <jose.souza@intel.com> Co-developed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Co-developed-by: Dave Airlie <airlied@redhat.com> Co-developed-by: Faith Ekstrand <faith.ekstrand@collabora.com> Co-developed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Co-developed-by: Mauro Carvalho Chehab <mchehab@kernel.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
2023-03-30 21:31:57 +00:00
/* SPDX-License-Identifier: MIT */
/*
* Copyright © 2023 Intel Corporation
*/
#ifndef _XE_GPU_SCHEDULER_TYPES_H_
#define _XE_GPU_SCHEDULER_TYPES_H_
#include <drm/gpu_scheduler.h>
/**
* struct xe_sched_msg - an in-band (relative to GPU scheduler run queue)
* message
*
* Generic enough for backend defined messages, backend can expand if needed.
*/
struct xe_sched_msg {
/** @link: list link into the gpu scheduler list of messages */
struct list_head link;
/**
* @private_data: opaque pointer to message private data (backend defined)
*/
void *private_data;
/** @opcode: opcode of message (backend defined) */
unsigned int opcode;
};
/**
* struct xe_sched_backend_ops - Define the backend operations called by the
* scheduler
*/
struct xe_sched_backend_ops {
/**
* @process_msg: Process a message. Allowed to block, it is this
* function's responsibility to free message if dynamically allocated.
*/
void (*process_msg)(struct xe_sched_msg *msg);
};
/**
* struct xe_gpu_scheduler - Xe GPU scheduler
*/
struct xe_gpu_scheduler {
/** @base: DRM GPU scheduler */
struct drm_gpu_scheduler base;
/** @ops: Xe scheduler ops */
const struct xe_sched_backend_ops *ops;
/** @msgs: list of messages to be processed in @work_process_msg */
struct list_head msgs;
/** @work_process_msg: processes messages */
struct work_struct work_process_msg;
};
#define xe_sched_entity drm_sched_entity
#define xe_sched_policy drm_sched_policy
#endif