2020-03-13 19:42:50 +00:00
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2005, Intec Automation Inc.
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* Copyright (C) 2014, Freescale Semiconductor, Inc.
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*/
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#include <linux/mtd/spi-nor.h>
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#include "core.h"
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2022-02-23 13:43:48 +00:00
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#define XILINX_OP_SE 0x50 /* Sector erase */
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#define XILINX_OP_PP 0x82 /* Page program */
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#define XILINX_OP_RDSR 0xd7 /* Read status register */
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2022-02-23 13:43:47 +00:00
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#define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
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#define XSR_RDY BIT(7) /* Ready */
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2022-04-20 10:34:25 +00:00
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#define XILINX_RDSR_OP(buf) \
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SPI_MEM_OP(SPI_MEM_OP_CMD(XILINX_OP_RDSR, 0), \
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SPI_MEM_OP_NO_ADDR, \
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SPI_MEM_OP_NO_DUMMY, \
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SPI_MEM_OP_DATA_IN(1, buf, 0))
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2022-02-23 13:43:47 +00:00
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#define S3AN_INFO(_jedec_id, _n_sectors, _page_size) \
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.id = { \
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((_jedec_id) >> 16) & 0xff, \
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((_jedec_id) >> 8) & 0xff, \
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(_jedec_id) & 0xff \
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}, \
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.id_len = 3, \
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.sector_size = (8 * (_page_size)), \
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.n_sectors = (_n_sectors), \
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.page_size = (_page_size), \
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR
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/* Xilinx S3AN share MFR with Atmel SPI NOR */
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static const struct flash_info xilinx_nor_parts[] = {
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/* Xilinx S3AN Internal Flash */
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{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
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{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
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{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
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{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
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{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
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};
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/*
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* This code converts an address to the Default Address Mode, that has non
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* power of two page sizes. We must support this mode because it is the default
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* mode supported by Xilinx tools, it can access the whole flash area and
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* changing over to the Power-of-two mode is irreversible and corrupts the
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* original data.
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* Addr can safely be unsigned int, the biggest S3AN device is smaller than
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* 4 MiB.
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*/
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static u32 s3an_nor_convert_addr(struct spi_nor *nor, u32 addr)
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{
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u32 page_size = nor->params->page_size;
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2020-03-13 19:42:50 +00:00
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u32 offset, page;
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2021-10-29 17:26:12 +00:00
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offset = addr % page_size;
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page = addr / page_size;
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page <<= (page_size > 512) ? 10 : 9;
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2020-03-13 19:42:50 +00:00
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return page | offset;
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}
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2022-02-23 13:43:47 +00:00
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/**
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* xilinx_nor_read_sr() - Read the Status Register on S3AN flashes.
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* @nor: pointer to 'struct spi_nor'.
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* @sr: pointer to a DMA-able buffer where the value of the
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* Status Register will be written.
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*
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* Return: 0 on success, -errno otherwise.
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*/
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static int xilinx_nor_read_sr(struct spi_nor *nor, u8 *sr)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op = XILINX_RDSR_OP(sr);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_read_reg(nor, XILINX_OP_RDSR, sr,
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1);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d reading SR\n", ret);
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return ret;
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}
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/**
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* xilinx_nor_sr_ready() - Query the Status Register of the S3AN flash to see
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* if the flash is ready for new commands.
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2022-02-23 13:43:47 +00:00
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 1 if ready, 0 if not ready, -errno on errors.
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*/
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static int xilinx_nor_sr_ready(struct spi_nor *nor)
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{
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int ret;
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ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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return !!(nor->bouncebuf[0] & XSR_RDY);
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}
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2020-03-13 19:42:50 +00:00
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static int xilinx_nor_setup(struct spi_nor *nor,
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const struct spi_nor_hwcaps *hwcaps)
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{
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u32 page_size;
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int ret;
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ret = xilinx_nor_read_sr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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nor->erase_opcode = XILINX_OP_SE;
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nor->program_opcode = XILINX_OP_PP;
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nor->read_opcode = SPINOR_OP_READ;
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nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
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/*
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* This flashes have a page size of 264 or 528 bytes (known as
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* Default addressing mode). It can be changed to a more standard
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* Power of two mode where the page size is 256/512. This comes
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* with a price: there is 3% less of space, the data is corrupted
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* and the page size cannot be changed back to default addressing
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* mode.
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*
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* The current addressing mode can be read from the XRDSR register
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* and should not be changed, because is a destructive operation.
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*/
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if (nor->bouncebuf[0] & XSR_PAGESIZE) {
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/* Flash in Power of 2 mode */
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page_size = (nor->params->page_size == 264) ? 256 : 512;
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nor->params->page_size = page_size;
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nor->mtd.writebufsize = page_size;
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nor->params->size = 8 * page_size * nor->info->n_sectors;
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nor->mtd.erasesize = 8 * page_size;
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} else {
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/* Flash in Default addressing mode */
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nor->params->convert_addr = s3an_nor_convert_addr;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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return 0;
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}
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static void xilinx_nor_late_init(struct spi_nor *nor)
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{
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nor->params->setup = xilinx_nor_setup;
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nor->params->ready = xilinx_nor_sr_ready;
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}
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static const struct spi_nor_fixups xilinx_nor_fixups = {
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.late_init = xilinx_nor_late_init,
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};
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const struct spi_nor_manufacturer spi_nor_xilinx = {
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.name = "xilinx",
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.parts = xilinx_nor_parts,
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.nparts = ARRAY_SIZE(xilinx_nor_parts),
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.fixups = &xilinx_nor_fixups,
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};
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