2011-05-09 16:56:46 +00:00
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/*
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* Broadcom specific AMBA
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* ChipCommon Power Management Unit driver
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*
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2011-07-04 18:50:05 +00:00
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* Copyright 2009, Michael Buesch <m@bues.ch>
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2011-05-09 16:56:46 +00:00
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* Copyright 2007, Broadcom Corporation
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*
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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#include "bcma_private.h"
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#include <linux/bcma/bcma.h>
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static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set)
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{
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u32 value;
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bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
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bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
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value = bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
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value &= mask;
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value |= set;
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL_DATA, value);
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bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
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}
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static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4313:
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case 0x4331:
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case 43224:
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case 43225:
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break;
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default:
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pr_err("PLL init unknown for device 0x%04X\n",
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bus->chipinfo.id);
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}
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}
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static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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u32 min_msk = 0, max_msk = 0;
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switch (bus->chipinfo.id) {
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case 0x4313:
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min_msk = 0x200D;
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max_msk = 0xFFFF;
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break;
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case 43224:
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2011-06-17 11:15:23 +00:00
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case 43225:
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2011-05-09 16:56:46 +00:00
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break;
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default:
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pr_err("PMU resource config unknown for device 0x%04X\n",
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bus->chipinfo.id);
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}
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/* Set the resource masks. */
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if (min_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
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if (max_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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}
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void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4313:
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case 0x4331:
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case 43224:
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2011-06-17 11:15:23 +00:00
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case 43225:
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2011-05-09 16:56:46 +00:00
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break;
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default:
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pr_err("PMU switch/regulators init unknown for device "
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"0x%04X\n", bus->chipinfo.id);
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}
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}
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void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4313:
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
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break;
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case 0x4331:
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pr_err("Enabling Ext PA lines not implemented\n");
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break;
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case 43224:
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if (bus->chipinfo.rev == 0) {
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pr_err("Workarounds for 43224 rev 0 not fully "
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"implemented\n");
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2011-06-17 11:15:24 +00:00
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
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2011-05-09 16:56:46 +00:00
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} else {
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bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
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}
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break;
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2011-06-17 11:15:23 +00:00
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case 43225:
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break;
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2011-05-09 16:56:46 +00:00
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default:
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pr_err("Workarounds unknown for device 0x%04X\n",
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bus->chipinfo.id);
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}
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}
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void bcma_pmu_init(struct bcma_drv_cc *cc)
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{
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u32 pmucap;
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pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
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cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
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pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
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pmucap);
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if (cc->pmu.rev == 1)
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bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
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~BCMA_CC_PMU_CTL_NOILPONW);
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else
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bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
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BCMA_CC_PMU_CTL_NOILPONW);
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if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
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pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
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bcma_pmu_pll_init(cc);
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bcma_pmu_resources_init(cc);
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bcma_pmu_swreg_init(cc);
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bcma_pmu_workarounds(cc);
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}
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2011-07-22 23:20:10 +00:00
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u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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switch (bus->chipinfo.id) {
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case 0x4716:
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case 0x4748:
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case 47162:
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case 0x4313:
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case 0x5357:
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case 0x4749:
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case 53572:
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/* always 20Mhz */
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return 20000 * 1000;
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case 0x5356:
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case 0x5300:
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/* always 25Mhz */
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return 25000 * 1000;
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default:
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pr_warn("No ALP clock specified for %04X device, "
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"pmu rev. %d, using default %d Hz\n",
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bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
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}
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return BCMA_CC_PMU_ALP_CLOCK;
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}
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