2019-05-19 13:51:37 +00:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2006-05-24 00:18:44 +00:00
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/*
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* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
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*/
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2012-03-06 22:34:26 +00:00
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#ifndef LINUX_DMAENGINE_H
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#define LINUX_DMAENGINE_H
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2006-06-27 09:53:56 +00:00
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2006-05-24 00:18:44 +00:00
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#include <linux/device.h>
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dma: add channel request API that supports deferred probe
dma_request_slave_channel() simply returns NULL whenever DMA channel
lookup fails. Lookup could fail for two distinct reasons:
a) No DMA specification exists for the channel name.
This includes situations where no DMA specifications exist at all, or
other general lookup problems.
b) A DMA specification does exist, yet the driver for that channel is not
yet registered.
Case (b) should trigger deferred probe in client drivers. However, since
they have no way to differentiate the two situations, it cannot.
Implement new function dma_request_slave_channel_reason(), which performs
identically to dma_request_slave_channel(), except that it returns an
error-pointer rather than NULL, which allows callers to detect when
deferred probe should occur.
Eventually, all drivers should be converted to this new API, the old API
removed, and the new API renamed to the more desirable name. This patch
doesn't convert the existing API and all drivers in one go, since some
drivers call dma_request_slave_channel() then dma_request_channel() if
that fails. That would require either modifying dma_request_channel() in
the same way, or adding extra error-handling code to all affected
drivers, and there are close to 100 drivers using the other API, rather
than just the 15-20 or so that use dma_request_slave_channel(), which
might be tenable in a single patch.
acpi_dma_request_slave_chan_by_name() doesn't currently implement
deferred probe. It should, but this will be addressed later.
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-11-26 17:04:22 +00:00
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#include <linux/err.h>
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2006-05-24 00:18:44 +00:00
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#include <linux/uio.h>
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2011-11-24 01:12:59 +00:00
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#include <linux/bug.h>
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2011-07-25 14:27:52 +00:00
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#include <linux/scatterlist.h>
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2011-07-29 06:55:11 +00:00
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#include <linux/bitmap.h>
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2012-02-01 10:42:18 +00:00
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#include <linux/types.h>
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2011-07-29 06:55:11 +00:00
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#include <asm/page.h>
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2011-06-16 11:01:34 +00:00
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2006-05-24 00:18:44 +00:00
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/**
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2006-07-04 02:44:51 +00:00
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* typedef dma_cookie_t - an opaque DMA cookie
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2006-05-24 00:18:44 +00:00
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*
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* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
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*/
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typedef s32 dma_cookie_t;
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2010-03-01 05:18:16 +00:00
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#define DMA_MIN_COOKIE 1
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2006-05-24 00:18:44 +00:00
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2013-08-10 07:46:50 +00:00
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static inline int dma_submit_error(dma_cookie_t cookie)
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{
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return cookie < 0 ? cookie : 0;
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}
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2006-05-24 00:18:44 +00:00
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/**
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* enum dma_status - DMA transaction status
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2013-10-16 07:59:02 +00:00
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* @DMA_COMPLETE: transaction completed
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2006-05-24 00:18:44 +00:00
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* @DMA_IN_PROGRESS: transaction not yet processed
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2010-03-26 23:50:49 +00:00
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* @DMA_PAUSED: transaction is paused
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2006-05-24 00:18:44 +00:00
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* @DMA_ERROR: transaction failed
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*/
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enum dma_status {
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2013-10-17 01:59:57 +00:00
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DMA_COMPLETE,
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2006-05-24 00:18:44 +00:00
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DMA_IN_PROGRESS,
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2010-03-26 23:50:49 +00:00
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DMA_PAUSED,
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2006-05-24 00:18:44 +00:00
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DMA_ERROR,
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2020-05-13 18:47:49 +00:00
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DMA_OUT_OF_ORDER,
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2006-05-24 00:18:44 +00:00
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};
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
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/**
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* enum dma_transaction_type - DMA transaction types/indexes
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2009-09-09 00:42:51 +00:00
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*
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* Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
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* automatically set as dma devices are registered.
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
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*/
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enum dma_transaction_type {
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DMA_MEMCPY,
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DMA_XOR,
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async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
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DMA_PQ,
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2009-04-08 21:28:37 +00:00
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DMA_XOR_VAL,
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DMA_PQ_VAL,
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2015-05-18 11:46:15 +00:00
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DMA_MEMSET,
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2015-07-06 10:19:23 +00:00
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DMA_MEMSET_SG,
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
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DMA_INTERRUPT,
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2009-01-06 18:38:15 +00:00
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DMA_PRIVATE,
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2009-09-09 00:42:51 +00:00
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DMA_ASYNC_TX,
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dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 18:59:35 +00:00
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DMA_SLAVE,
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2010-09-30 13:56:32 +00:00
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DMA_CYCLIC,
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2011-10-13 07:03:30 +00:00
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DMA_INTERLEAVE,
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2020-05-13 18:47:49 +00:00
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DMA_COMPLETION_NO_ORDER,
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2020-07-17 01:33:34 +00:00
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DMA_REPEAT,
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DMA_LOAD_EOT,
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dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
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/* last transaction type for creation of the capabilities mask */
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2011-10-13 07:03:30 +00:00
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DMA_TX_TYPE_END,
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};
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dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 18:59:35 +00:00
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2011-10-13 09:45:27 +00:00
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/**
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* enum dma_transfer_direction - dma transfer mode and direction indicator
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* @DMA_MEM_TO_MEM: Async/Memcpy mode
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* @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
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* @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
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* @DMA_DEV_TO_DEV: Slave mode & From Device to Device
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|
*/
|
|
|
|
enum dma_transfer_direction {
|
|
|
|
DMA_MEM_TO_MEM,
|
|
|
|
DMA_MEM_TO_DEV,
|
|
|
|
DMA_DEV_TO_MEM,
|
|
|
|
DMA_DEV_TO_DEV,
|
2011-12-13 15:48:03 +00:00
|
|
|
DMA_TRANS_NONE,
|
2011-10-13 09:45:27 +00:00
|
|
|
};
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
|
2011-10-13 07:03:30 +00:00
|
|
|
/**
|
|
|
|
* Interleaved Transfer Request
|
|
|
|
* ----------------------------
|
2020-04-14 04:17:03 +00:00
|
|
|
* A chunk is collection of contiguous bytes to be transferred.
|
2011-10-13 07:03:30 +00:00
|
|
|
* The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
|
2020-04-14 04:17:03 +00:00
|
|
|
* ICGs may or may not change between chunks.
|
2011-10-13 07:03:30 +00:00
|
|
|
* A FRAME is the smallest series of contiguous {chunk,icg} pairs,
|
|
|
|
* that when repeated an integral number of times, specifies the transfer.
|
|
|
|
* A transfer template is specification of a Frame, the number of times
|
|
|
|
* it is to be repeated and other per-transfer attributes.
|
|
|
|
*
|
|
|
|
* Practically, a client driver would have ready a template for each
|
|
|
|
* type of transfer it is going to need during its lifetime and
|
|
|
|
* set only 'src_start' and 'dst_start' before submitting the requests.
|
|
|
|
*
|
|
|
|
*
|
|
|
|
* | Frame-1 | Frame-2 | ~ | Frame-'numf' |
|
|
|
|
* |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
|
|
|
|
*
|
|
|
|
* == Chunk size
|
|
|
|
* ... ICG
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct data_chunk - Element of scatter-gather list that makes a frame.
|
|
|
|
* @size: Number of bytes to read from source.
|
|
|
|
* size_dst := fn(op, size_src), so doesn't mean much for destination.
|
|
|
|
* @icg: Number of bytes to jump after last src/dst address of this
|
|
|
|
* chunk and before first src/dst address for next chunk.
|
|
|
|
* Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
|
|
|
|
* Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
|
2015-05-07 15:38:07 +00:00
|
|
|
* @dst_icg: Number of bytes to jump after last dst address of this
|
|
|
|
* chunk and before the first dst address for next chunk.
|
|
|
|
* Ignored if dst_inc is true and dst_sgl is false.
|
|
|
|
* @src_icg: Number of bytes to jump after last src address of this
|
|
|
|
* chunk and before the first src address for next chunk.
|
|
|
|
* Ignored if src_inc is true and src_sgl is false.
|
2011-10-13 07:03:30 +00:00
|
|
|
*/
|
|
|
|
struct data_chunk {
|
|
|
|
size_t size;
|
|
|
|
size_t icg;
|
2015-05-07 15:38:07 +00:00
|
|
|
size_t dst_icg;
|
|
|
|
size_t src_icg;
|
2011-10-13 07:03:30 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dma_interleaved_template - Template to convey DMAC the transfer pattern
|
|
|
|
* and attributes.
|
|
|
|
* @src_start: Bus address of source for the first chunk.
|
|
|
|
* @dst_start: Bus address of destination for the first chunk.
|
|
|
|
* @dir: Specifies the type of Source and Destination.
|
|
|
|
* @src_inc: If the source address increments after reading from it.
|
|
|
|
* @dst_inc: If the destination address increments after writing to it.
|
|
|
|
* @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
|
|
|
|
* Otherwise, source is read contiguously (icg ignored).
|
|
|
|
* Ignored if src_inc is false.
|
|
|
|
* @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
|
|
|
|
* Otherwise, destination is filled contiguously (icg ignored).
|
|
|
|
* Ignored if dst_inc is false.
|
|
|
|
* @numf: Number of frames in this template.
|
|
|
|
* @frame_size: Number of chunks in a frame i.e, size of sgl[].
|
|
|
|
* @sgl: Array of {chunk,icg} pairs that make up a frame.
|
|
|
|
*/
|
|
|
|
struct dma_interleaved_template {
|
|
|
|
dma_addr_t src_start;
|
|
|
|
dma_addr_t dst_start;
|
|
|
|
enum dma_transfer_direction dir;
|
|
|
|
bool src_inc;
|
|
|
|
bool dst_inc;
|
|
|
|
bool src_sgl;
|
|
|
|
bool dst_sgl;
|
|
|
|
size_t numf;
|
|
|
|
size_t frame_size;
|
2020-05-28 14:35:11 +00:00
|
|
|
struct data_chunk sgl[];
|
2011-10-13 07:03:30 +00:00
|
|
|
};
|
|
|
|
|
2008-02-03 02:49:58 +00:00
|
|
|
/**
|
2008-04-18 03:17:26 +00:00
|
|
|
* enum dma_ctrl_flags - DMA flags to augment operation preparation,
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
* control completion, and communicate status.
|
2008-02-03 02:49:58 +00:00
|
|
|
* @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
* this transaction
|
2009-12-10 17:35:15 +00:00
|
|
|
* @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
|
2020-07-18 02:51:18 +00:00
|
|
|
* acknowledges receipt, i.e. has a chance to establish any dependency
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
* chains
|
|
|
|
* @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
|
|
|
|
* @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
|
|
|
|
* @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
|
|
|
|
* sources that were the result of a previous operation, in the case of a PQ
|
|
|
|
* operation it continues the calculation with new sources
|
2009-09-09 00:42:50 +00:00
|
|
|
* @DMA_PREP_FENCE - tell the driver that subsequent operations depend
|
|
|
|
* on the result of this operation
|
2015-08-05 03:12:05 +00:00
|
|
|
* @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
|
|
|
|
* cleared or freed
|
2017-08-01 14:11:42 +00:00
|
|
|
* @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
|
|
|
|
* data and the descriptor should be in different format from normal
|
|
|
|
* data descriptors.
|
2020-07-17 01:33:34 +00:00
|
|
|
* @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
|
|
|
|
* repeated when it ends until a transaction is issued on the same channel
|
|
|
|
* with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
|
|
|
|
* interleaved transactions and is ignored for all other transaction types.
|
|
|
|
* @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
|
|
|
|
* active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
|
|
|
|
* repeated transaction ends. Not setting this flag when the previously queued
|
|
|
|
* transaction is marked with DMA_PREP_REPEAT will cause the new transaction
|
|
|
|
* to never be processed and stay in the issued queue forever. The flag is
|
|
|
|
* ignored if the previous transaction is not a repeated transaction.
|
2008-02-03 02:49:58 +00:00
|
|
|
*/
|
2008-04-18 03:17:26 +00:00
|
|
|
enum dma_ctrl_flags {
|
2008-02-03 02:49:58 +00:00
|
|
|
DMA_PREP_INTERRUPT = (1 << 0),
|
2008-04-18 03:17:26 +00:00
|
|
|
DMA_CTRL_ACK = (1 << 1),
|
2013-10-18 17:35:33 +00:00
|
|
|
DMA_PREP_PQ_DISABLE_P = (1 << 2),
|
|
|
|
DMA_PREP_PQ_DISABLE_Q = (1 << 3),
|
|
|
|
DMA_PREP_CONTINUE = (1 << 4),
|
|
|
|
DMA_PREP_FENCE = (1 << 5),
|
2015-08-05 03:12:05 +00:00
|
|
|
DMA_CTRL_REUSE = (1 << 6),
|
2017-08-01 14:11:42 +00:00
|
|
|
DMA_PREP_CMD = (1 << 7),
|
2020-07-17 01:33:34 +00:00
|
|
|
DMA_PREP_REPEAT = (1 << 8),
|
|
|
|
DMA_PREP_LOAD_EOT = (1 << 9),
|
2008-02-03 02:49:58 +00:00
|
|
|
};
|
|
|
|
|
2009-08-30 02:09:26 +00:00
|
|
|
/**
|
|
|
|
* enum sum_check_bits - bit position of pq_check_flags
|
|
|
|
*/
|
|
|
|
enum sum_check_bits {
|
|
|
|
SUM_CHECK_P = 0,
|
|
|
|
SUM_CHECK_Q = 1,
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
|
|
|
|
* @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
|
|
|
|
* @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
|
|
|
|
*/
|
|
|
|
enum sum_check_flags {
|
|
|
|
SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
|
|
|
|
SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
|
|
|
|
};
|
|
|
|
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
/**
|
|
|
|
* dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
|
|
|
|
* See linux/cpumask.h
|
|
|
|
*/
|
|
|
|
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
/**
|
|
|
|
* struct dma_chan_percpu - the per-CPU part of struct dma_chan
|
|
|
|
* @memcpy_count: transaction counter
|
|
|
|
* @bytes_transferred: byte counter
|
|
|
|
*/
|
|
|
|
|
2019-12-23 11:04:44 +00:00
|
|
|
/**
|
|
|
|
* enum dma_desc_metadata_mode - per descriptor metadata mode types supported
|
|
|
|
* @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
|
|
|
|
* client driver and it is attached (via the dmaengine_desc_attach_metadata()
|
|
|
|
* helper) to the descriptor.
|
|
|
|
*
|
|
|
|
* Client drivers interested to use this mode can follow:
|
|
|
|
* - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
|
|
|
|
* 1. prepare the descriptor (dmaengine_prep_*)
|
|
|
|
* construct the metadata in the client's buffer
|
|
|
|
* 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
|
|
|
|
* descriptor
|
|
|
|
* 3. submit the transfer
|
|
|
|
* - DMA_DEV_TO_MEM:
|
|
|
|
* 1. prepare the descriptor (dmaengine_prep_*)
|
|
|
|
* 2. use dmaengine_desc_attach_metadata() to attach the buffer to the
|
|
|
|
* descriptor
|
|
|
|
* 3. submit the transfer
|
|
|
|
* 4. when the transfer is completed, the metadata should be available in the
|
|
|
|
* attached buffer
|
|
|
|
*
|
|
|
|
* @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
|
|
|
|
* driver. The client driver can ask for the pointer, maximum size and the
|
|
|
|
* currently used size of the metadata and can directly update or read it.
|
|
|
|
* dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
|
|
|
|
* provided as helper functions.
|
|
|
|
*
|
|
|
|
* Note: the metadata area for the descriptor is no longer valid after the
|
|
|
|
* transfer has been completed (valid up to the point when the completion
|
|
|
|
* callback returns if used).
|
|
|
|
*
|
|
|
|
* Client drivers interested to use this mode can follow:
|
|
|
|
* - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
|
|
|
|
* 1. prepare the descriptor (dmaengine_prep_*)
|
|
|
|
* 2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
|
|
|
|
* metadata area
|
|
|
|
* 3. update the metadata at the pointer
|
|
|
|
* 4. use dmaengine_desc_set_metadata_len() to tell the DMA engine the amount
|
|
|
|
* of data the client has placed into the metadata buffer
|
|
|
|
* 5. submit the transfer
|
|
|
|
* - DMA_DEV_TO_MEM:
|
|
|
|
* 1. prepare the descriptor (dmaengine_prep_*)
|
|
|
|
* 2. submit the transfer
|
|
|
|
* 3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
|
|
|
|
* pointer to the engine's metadata area
|
|
|
|
* 4. Read out the metadata from the pointer
|
|
|
|
*
|
|
|
|
* Note: the two mode is not compatible and clients must use one mode for a
|
|
|
|
* descriptor.
|
|
|
|
*/
|
|
|
|
enum dma_desc_metadata_mode {
|
|
|
|
DESC_METADATA_NONE = 0,
|
|
|
|
DESC_METADATA_CLIENT = BIT(0),
|
|
|
|
DESC_METADATA_ENGINE = BIT(1),
|
|
|
|
};
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
struct dma_chan_percpu {
|
|
|
|
/* stats */
|
|
|
|
unsigned long memcpy_count;
|
|
|
|
unsigned long bytes_transferred;
|
|
|
|
};
|
|
|
|
|
2015-04-09 09:35:47 +00:00
|
|
|
/**
|
|
|
|
* struct dma_router - DMA router structure
|
|
|
|
* @dev: pointer to the DMA router device
|
|
|
|
* @route_free: function to be called when the route can be disconnected
|
|
|
|
*/
|
|
|
|
struct dma_router {
|
|
|
|
struct device *dev;
|
|
|
|
void (*route_free)(struct device *dev, void *route_data);
|
|
|
|
};
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
/**
|
|
|
|
* struct dma_chan - devices supply DMA channels, clients use them
|
2006-07-04 02:44:51 +00:00
|
|
|
* @device: ptr to the dma device who supplies this channel, always !%NULL
|
2020-01-17 15:30:56 +00:00
|
|
|
* @slave: ptr to the device using this channel
|
2006-05-24 00:18:44 +00:00
|
|
|
* @cookie: last cookie value returned to client
|
2012-03-06 22:34:06 +00:00
|
|
|
* @completed_cookie: last completed cookie for this channel
|
2006-07-04 02:44:51 +00:00
|
|
|
* @chan_id: channel ID for sysfs
|
2009-01-06 18:38:21 +00:00
|
|
|
* @dev: class device for sysfs
|
2020-01-17 15:30:56 +00:00
|
|
|
* @name: backlink name for sysfs
|
2020-03-06 14:28:37 +00:00
|
|
|
* @dbg_client_name: slave name for debugfs in format:
|
|
|
|
* dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
|
2006-05-24 00:18:44 +00:00
|
|
|
* @device_node: used to add this to the device chan list
|
|
|
|
* @local: per-cpu pointer to a struct dma_chan_percpu
|
2013-12-18 16:09:39 +00:00
|
|
|
* @client_count: how many clients are using this channel
|
2009-01-06 18:38:14 +00:00
|
|
|
* @table_count: number of appearances in the mem-to-mem allocation table
|
2015-04-09 09:35:47 +00:00
|
|
|
* @router: pointer to the DMA router structure
|
|
|
|
* @route_data: channel specific data for the router
|
2009-02-18 22:48:26 +00:00
|
|
|
* @private: private data for certain client-channel associations
|
2006-05-24 00:18:44 +00:00
|
|
|
*/
|
|
|
|
struct dma_chan {
|
|
|
|
struct dma_device *device;
|
2020-01-17 15:30:56 +00:00
|
|
|
struct device *slave;
|
2006-05-24 00:18:44 +00:00
|
|
|
dma_cookie_t cookie;
|
2012-03-06 22:34:06 +00:00
|
|
|
dma_cookie_t completed_cookie;
|
2006-05-24 00:18:44 +00:00
|
|
|
|
|
|
|
/* sysfs */
|
|
|
|
int chan_id;
|
2009-01-06 18:38:21 +00:00
|
|
|
struct dma_chan_dev *dev;
|
2020-01-17 15:30:56 +00:00
|
|
|
const char *name;
|
2020-03-06 14:28:37 +00:00
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
char *dbg_client_name;
|
|
|
|
#endif
|
2006-05-24 00:18:44 +00:00
|
|
|
|
|
|
|
struct list_head device_node;
|
2010-02-02 05:39:15 +00:00
|
|
|
struct dma_chan_percpu __percpu *local;
|
2008-07-08 18:58:21 +00:00
|
|
|
int client_count;
|
2009-01-06 18:38:14 +00:00
|
|
|
int table_count;
|
2015-04-09 09:35:47 +00:00
|
|
|
|
|
|
|
/* DMA router */
|
|
|
|
struct dma_router *router;
|
|
|
|
void *route_data;
|
|
|
|
|
2009-02-18 22:48:26 +00:00
|
|
|
void *private;
|
2006-05-24 00:18:44 +00:00
|
|
|
};
|
|
|
|
|
2009-01-06 18:38:21 +00:00
|
|
|
/**
|
|
|
|
* struct dma_chan_dev - relate sysfs device node to backing channel device
|
2013-12-18 16:09:39 +00:00
|
|
|
* @chan: driver channel device
|
|
|
|
* @device: sysfs device
|
|
|
|
* @dev_id: parent dma_device dev_id
|
2009-01-06 18:38:21 +00:00
|
|
|
*/
|
|
|
|
struct dma_chan_dev {
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct device device;
|
2009-01-06 18:38:21 +00:00
|
|
|
int dev_id;
|
2009-01-06 18:38:21 +00:00
|
|
|
};
|
|
|
|
|
2010-08-04 11:37:33 +00:00
|
|
|
/**
|
2014-05-15 14:15:31 +00:00
|
|
|
* enum dma_slave_buswidth - defines bus width of the DMA slave
|
2010-08-04 11:37:33 +00:00
|
|
|
* device, source or target buses
|
|
|
|
*/
|
|
|
|
enum dma_slave_buswidth {
|
|
|
|
DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
|
|
|
|
DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
|
|
|
|
DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
|
2014-07-03 04:51:52 +00:00
|
|
|
DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
|
2010-08-04 11:37:33 +00:00
|
|
|
DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
|
|
|
|
DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
|
2014-08-06 08:52:41 +00:00
|
|
|
DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
|
|
|
|
DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
|
|
|
|
DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
|
2010-08-04 11:37:33 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dma_slave_config - dma slave channel runtime config
|
|
|
|
* @direction: whether the data shall go in or out on this slave
|
2013-12-16 08:12:17 +00:00
|
|
|
* channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
|
2014-08-20 17:20:53 +00:00
|
|
|
* legal values. DEPRECATED, drivers should use the direction argument
|
|
|
|
* to the device_prep_slave_sg and device_prep_dma_cyclic functions or
|
|
|
|
* the dir field in the dma_interleaved_template structure.
|
2010-08-04 11:37:33 +00:00
|
|
|
* @src_addr: this is the physical address where DMA slave data
|
|
|
|
* should be read (RX), if the source is memory this argument is
|
|
|
|
* ignored.
|
|
|
|
* @dst_addr: this is the physical address where DMA slave data
|
|
|
|
* should be written (TX), if the source is memory this argument
|
|
|
|
* is ignored.
|
|
|
|
* @src_addr_width: this is the width in bytes of the source (RX)
|
|
|
|
* register where DMA data shall be read. If the source
|
|
|
|
* is memory this may be ignored depending on architecture.
|
2017-09-11 23:44:44 +00:00
|
|
|
* Legal values: 1, 2, 3, 4, 8, 16, 32, 64.
|
2010-08-04 11:37:33 +00:00
|
|
|
* @dst_addr_width: same as src_addr_width but for destination
|
|
|
|
* target (TX) mutatis mutandis.
|
|
|
|
* @src_maxburst: the maximum number of words (note: words, as in
|
|
|
|
* units of the src_addr_width member, not bytes) that can be sent
|
|
|
|
* in one burst to the device. Typically something like half the
|
|
|
|
* FIFO depth on I/O peripherals so you don't overflow it. This
|
|
|
|
* may or may not be applicable on memory sources.
|
|
|
|
* @dst_maxburst: same as src_maxburst but for destination target
|
|
|
|
* mutatis mutandis.
|
2016-11-29 14:23:41 +00:00
|
|
|
* @src_port_window_size: The length of the register area in words the data need
|
|
|
|
* to be accessed on the device side. It is only used for devices which is using
|
|
|
|
* an area instead of a single register to receive the data. Typically the DMA
|
|
|
|
* loops in this area in order to transfer the data.
|
|
|
|
* @dst_port_window_size: same as src_port_window_size but for the destination
|
|
|
|
* port.
|
2012-02-01 10:42:18 +00:00
|
|
|
* @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
|
|
|
|
* with 'true' if peripheral should be flow controller. Direction will be
|
|
|
|
* selected at Runtime.
|
2012-06-06 05:25:26 +00:00
|
|
|
* @slave_id: Slave requester id. Only valid for slave channels. The dma
|
|
|
|
* slave peripheral will have unique id as dma requester which need to be
|
|
|
|
* pass as slave config.
|
2010-08-04 11:37:33 +00:00
|
|
|
*
|
|
|
|
* This struct is passed in as configuration data to a DMA engine
|
|
|
|
* in order to set up a certain channel for DMA transport at runtime.
|
|
|
|
* The DMA device/engine has to provide support for an additional
|
2014-11-17 13:42:54 +00:00
|
|
|
* callback in the dma_device structure, device_config and this struct
|
|
|
|
* will then be passed in as an argument to the function.
|
2010-08-04 11:37:33 +00:00
|
|
|
*
|
dma: Remove comment about embedding dma_slave_config into custom structs
The documentation for the dma_slave_config struct recommends that if a DMA
controller has special configuration options, which can not be configured
through the dma_slave_config struct, the driver should create its own custom
config struct and embed the dma_slave_config struct in it and pass the custom
config struct to dmaengine_slave_config(). This overloads the generic
dmaengine_slave_config() API with custom semantics and any caller of the
dmaengine_slave_config() that is not aware of these special semantics will cause
undefined behavior. This means that it is impossible for generic code to make
use of dmaengine_slave_config(). Such a restriction contradicts the very idea of
having a generic API.
E.g. consider the following case of a DMA controller that has an option to
reverse the field polarity of the DMA transfer with the following implementation
for setting the configuration:
struct my_slave_config {
struct dma_slave_config config;
unsigned int field_polarity;
};
static int my_dma_controller_slave_config(struct dma_chan *chan,
struct dma_slave_config *config)
{
struct my_slave_config *my_cfg = container_of(config,
struct my_slave_config, config);
...
my_dma_set_field_polarity(chan, my_cfg->field_polarity);
...
}
Now a generic user of the dmaengine API might want to configure a DMA channel
for this DMA controller that it obtained using the following code:
struct dma_slave_config config;
config.src_addr = ...;
...
dmaengine_slave_config(chan, &config);
The call to dmaengine_slave_config() will eventually call into
my_dma_controller_slave_config() which will cast from dma_slave_config to
my_slave_config and then tries to access the field_polarity member. Since the
dma_slave_config struct that was passed in was never embedded into a
my_slave_config struct this attempt will just read random stack garbage and use
that to configure the DMA controller. This is bad. Instead, if a DMA controller
really needs to have custom configuration options, the driver should create a
custom API for it. This makes it very clear that there is a direct dependency
of a user of such an API and the implementer. E.g.:
int my_dma_set_field_polarity(struct dma_chan *chan,
unsigned int field_polarity) {
if (chan->device->dev->driver != &my_dma_controller_driver.driver)
return -EINVAL;
...
}
EXPORT_SYMBOL_GPL(my_dma_set_field_polarity);
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2014-02-16 13:21:22 +00:00
|
|
|
* The rationale for adding configuration information to this struct is as
|
|
|
|
* follows: if it is likely that more than one DMA slave controllers in
|
|
|
|
* the world will support the configuration option, then make it generic.
|
|
|
|
* If not: if it is fixed so that it be sent in static from the platform
|
|
|
|
* data, then prefer to do that.
|
2010-08-04 11:37:33 +00:00
|
|
|
*/
|
|
|
|
struct dma_slave_config {
|
2011-10-13 09:45:27 +00:00
|
|
|
enum dma_transfer_direction direction;
|
2016-02-15 16:57:02 +00:00
|
|
|
phys_addr_t src_addr;
|
|
|
|
phys_addr_t dst_addr;
|
2010-08-04 11:37:33 +00:00
|
|
|
enum dma_slave_buswidth src_addr_width;
|
|
|
|
enum dma_slave_buswidth dst_addr_width;
|
|
|
|
u32 src_maxburst;
|
|
|
|
u32 dst_maxburst;
|
2016-11-29 14:23:41 +00:00
|
|
|
u32 src_port_window_size;
|
|
|
|
u32 dst_port_window_size;
|
2012-02-01 10:42:18 +00:00
|
|
|
bool device_fc;
|
2012-06-06 05:25:26 +00:00
|
|
|
unsigned int slave_id;
|
2010-08-04 11:37:33 +00:00
|
|
|
};
|
|
|
|
|
2014-01-11 13:02:16 +00:00
|
|
|
/**
|
|
|
|
* enum dma_residue_granularity - Granularity of the reported transfer residue
|
|
|
|
* @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
|
|
|
|
* DMA channel is only able to tell whether a descriptor has been completed or
|
|
|
|
* not, which means residue reporting is not supported by this channel. The
|
|
|
|
* residue field of the dma_tx_state field will always be 0.
|
|
|
|
* @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
|
|
|
|
* completed segment of the transfer (For cyclic transfers this is after each
|
|
|
|
* period). This is typically implemented by having the hardware generate an
|
|
|
|
* interrupt after each transferred segment and then the drivers updates the
|
|
|
|
* outstanding residue by the size of the segment. Another possibility is if
|
|
|
|
* the hardware supports scatter-gather and the segment descriptor has a field
|
|
|
|
* which gets set after the segment has been completed. The driver then counts
|
|
|
|
* the number of segments without the flag set to compute the residue.
|
|
|
|
* @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
|
|
|
|
* burst. This is typically only supported if the hardware has a progress
|
|
|
|
* register of some sort (E.g. a register with the current read/write address
|
|
|
|
* or a register with the amount of bursts/beats/bytes that have been
|
|
|
|
* transferred or still need to be transferred).
|
|
|
|
*/
|
|
|
|
enum dma_residue_granularity {
|
|
|
|
DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
|
|
|
|
DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
|
|
|
|
DMA_RESIDUE_GRANULARITY_BURST = 2,
|
|
|
|
};
|
|
|
|
|
2017-09-11 23:44:45 +00:00
|
|
|
/**
|
|
|
|
* struct dma_slave_caps - expose capabilities of a slave channel only
|
|
|
|
* @src_addr_widths: bit mask of src addr widths the channel supports.
|
|
|
|
* Width is specified in bytes, e.g. for a channel supporting
|
|
|
|
* a width of 4 the mask should have BIT(4) set.
|
|
|
|
* @dst_addr_widths: bit mask of dst addr widths the channel supports
|
|
|
|
* @directions: bit mask of slave directions the channel supports.
|
|
|
|
* Since the enum dma_transfer_direction is not defined as bit flag for
|
|
|
|
* each type, the dma controller should set BIT(<TYPE>) and same
|
|
|
|
* should be checked by controller as well
|
2020-07-23 00:58:41 +00:00
|
|
|
* @min_burst: min burst capability per-transfer
|
2016-01-22 11:06:50 +00:00
|
|
|
* @max_burst: max burst capability per-transfer
|
2020-07-23 00:58:42 +00:00
|
|
|
* @max_sg_burst: max number of SG list entries executed in a single burst
|
|
|
|
* DMA tansaction with no software intervention for reinitialization.
|
|
|
|
* Zero value means unlimited number of entries.
|
2018-07-02 13:08:10 +00:00
|
|
|
* @cmd_pause: true, if pause is supported (i.e. for reading residue or
|
|
|
|
* for resume later)
|
|
|
|
* @cmd_resume: true, if resume is supported
|
2013-07-08 08:45:25 +00:00
|
|
|
* @cmd_terminate: true, if terminate cmd is supported
|
2014-01-11 13:02:16 +00:00
|
|
|
* @residue_granularity: granularity of the reported transfer residue
|
2015-08-05 03:12:05 +00:00
|
|
|
* @descriptor_reuse: if a descriptor can be reused by client and
|
|
|
|
* resubmitted multiple times
|
2013-07-08 08:45:25 +00:00
|
|
|
*/
|
|
|
|
struct dma_slave_caps {
|
|
|
|
u32 src_addr_widths;
|
2014-11-17 13:41:57 +00:00
|
|
|
u32 dst_addr_widths;
|
2013-07-08 08:45:25 +00:00
|
|
|
u32 directions;
|
2020-07-23 00:58:41 +00:00
|
|
|
u32 min_burst;
|
2016-01-22 11:06:50 +00:00
|
|
|
u32 max_burst;
|
2020-07-23 00:58:42 +00:00
|
|
|
u32 max_sg_burst;
|
2013-07-08 08:45:25 +00:00
|
|
|
bool cmd_pause;
|
2018-07-02 13:08:10 +00:00
|
|
|
bool cmd_resume;
|
2013-07-08 08:45:25 +00:00
|
|
|
bool cmd_terminate;
|
2014-01-11 13:02:16 +00:00
|
|
|
enum dma_residue_granularity residue_granularity;
|
2015-08-05 03:12:05 +00:00
|
|
|
bool descriptor_reuse;
|
2013-07-08 08:45:25 +00:00
|
|
|
};
|
|
|
|
|
2009-01-06 18:38:21 +00:00
|
|
|
static inline const char *dma_chan_name(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
return dev_name(&chan->dev->device);
|
|
|
|
}
|
2007-07-09 18:56:42 +00:00
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
void dma_chan_cleanup(struct kref *kref);
|
|
|
|
|
2009-01-06 18:38:15 +00:00
|
|
|
/**
|
|
|
|
* typedef dma_filter_fn - callback filter for dma_request_channel
|
|
|
|
* @chan: channel to be reviewed
|
|
|
|
* @filter_param: opaque parameter passed through dma_request_channel
|
|
|
|
*
|
|
|
|
* When this optional parameter is specified in a call to dma_request_channel a
|
|
|
|
* suitable channel is passed to this routine for further dispositioning before
|
|
|
|
* being returned. Where 'suitable' indicates a non-busy channel that
|
2009-01-06 18:38:19 +00:00
|
|
|
* satisfies the given capability mask. It returns 'true' to indicate that the
|
|
|
|
* channel is suitable.
|
2009-01-06 18:38:15 +00:00
|
|
|
*/
|
2009-01-06 18:38:19 +00:00
|
|
|
typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
|
2009-01-06 18:38:15 +00:00
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
typedef void (*dma_async_tx_callback)(void *dma_async_param);
|
2013-10-18 17:35:23 +00:00
|
|
|
|
2016-07-20 20:13:50 +00:00
|
|
|
enum dmaengine_tx_result {
|
|
|
|
DMA_TRANS_NOERROR = 0, /* SUCCESS */
|
|
|
|
DMA_TRANS_READ_FAILED, /* Source DMA read failed */
|
|
|
|
DMA_TRANS_WRITE_FAILED, /* Destination DMA write failed */
|
|
|
|
DMA_TRANS_ABORTED, /* Op never submitted / aborted */
|
|
|
|
};
|
|
|
|
|
|
|
|
struct dmaengine_result {
|
|
|
|
enum dmaengine_tx_result result;
|
|
|
|
u32 residue;
|
|
|
|
};
|
|
|
|
|
|
|
|
typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
|
|
|
|
const struct dmaengine_result *result);
|
|
|
|
|
2013-10-18 17:35:23 +00:00
|
|
|
struct dmaengine_unmap_data {
|
2018-01-08 15:50:50 +00:00
|
|
|
#if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
|
|
|
|
u16 map_cnt;
|
|
|
|
#else
|
2014-05-21 21:02:37 +00:00
|
|
|
u8 map_cnt;
|
2018-01-08 15:50:50 +00:00
|
|
|
#endif
|
2013-10-18 17:35:23 +00:00
|
|
|
u8 to_cnt;
|
|
|
|
u8 from_cnt;
|
|
|
|
u8 bidi_cnt;
|
|
|
|
struct device *dev;
|
|
|
|
struct kref kref;
|
|
|
|
size_t len;
|
2020-05-28 14:35:11 +00:00
|
|
|
dma_addr_t addr[];
|
2013-10-18 17:35:23 +00:00
|
|
|
};
|
|
|
|
|
2019-12-23 11:04:44 +00:00
|
|
|
struct dma_async_tx_descriptor;
|
|
|
|
|
|
|
|
struct dma_descriptor_metadata_ops {
|
|
|
|
int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
|
|
|
|
size_t len);
|
|
|
|
|
|
|
|
void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
|
|
|
|
size_t *payload_len, size_t *max_len);
|
|
|
|
int (*set_len)(struct dma_async_tx_descriptor *desc,
|
|
|
|
size_t payload_len);
|
|
|
|
};
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
/**
|
|
|
|
* struct dma_async_tx_descriptor - async transaction descriptor
|
|
|
|
* ---dma generic offload fields---
|
|
|
|
* @cookie: tracking cookie for this transaction, set to -EBUSY if
|
|
|
|
* this tx is sitting on a dependency list
|
2008-04-18 03:17:26 +00:00
|
|
|
* @flags: flags to augment operation preparation, control completion, and
|
2019-12-06 13:24:35 +00:00
|
|
|
* communicate status
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @phys: physical address of the descriptor
|
|
|
|
* @chan: target channel for this operation
|
2014-12-05 15:19:07 +00:00
|
|
|
* @tx_submit: accept the descriptor, assign ordered cookie and mark the
|
|
|
|
* descriptor pending. To be pushed on .issue_pending() call
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @callback: routine to call after this operation is complete
|
|
|
|
* @callback_param: general parameter to pass to the callback routine
|
2019-12-23 11:04:44 +00:00
|
|
|
* @desc_metadata_mode: core managed metadata mode to protect mixed use of
|
|
|
|
* DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
|
|
|
|
* DESC_METADATA_NONE
|
|
|
|
* @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
|
|
|
|
* DMA driver if metadata mode is supported with the descriptor
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* ---async_tx api specific fields---
|
2008-04-18 03:17:25 +00:00
|
|
|
* @next: at completion submit this descriptor
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @parent: pointer to the next level up in the dependency chain
|
2008-04-18 03:17:25 +00:00
|
|
|
* @lock: protect the parent and next pointers
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
*/
|
|
|
|
struct dma_async_tx_descriptor {
|
|
|
|
dma_cookie_t cookie;
|
2008-04-18 03:17:26 +00:00
|
|
|
enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
dma_addr_t phys;
|
|
|
|
struct dma_chan *chan;
|
|
|
|
dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
|
2015-08-05 03:12:05 +00:00
|
|
|
int (*desc_free)(struct dma_async_tx_descriptor *tx);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
dma_async_tx_callback callback;
|
2016-07-20 20:13:50 +00:00
|
|
|
dma_async_tx_callback_result callback_result;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
void *callback_param;
|
2013-10-18 17:35:23 +00:00
|
|
|
struct dmaengine_unmap_data *unmap;
|
2019-12-23 11:04:44 +00:00
|
|
|
enum dma_desc_metadata_mode desc_metadata_mode;
|
|
|
|
struct dma_descriptor_metadata_ops *metadata_ops;
|
2010-10-07 23:44:50 +00:00
|
|
|
#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2008-04-18 03:17:25 +00:00
|
|
|
struct dma_async_tx_descriptor *next;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
struct dma_async_tx_descriptor *parent;
|
|
|
|
spinlock_t lock;
|
2010-05-17 23:24:16 +00:00
|
|
|
#endif
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
};
|
|
|
|
|
2013-10-18 17:35:25 +00:00
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
2013-10-18 17:35:23 +00:00
|
|
|
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
|
|
|
|
struct dmaengine_unmap_data *unmap)
|
|
|
|
{
|
|
|
|
kref_get(&unmap->kref);
|
|
|
|
tx->unmap = unmap;
|
|
|
|
}
|
|
|
|
|
2013-10-18 17:35:25 +00:00
|
|
|
struct dmaengine_unmap_data *
|
|
|
|
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
|
2013-10-18 17:35:24 +00:00
|
|
|
void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
|
2013-10-18 17:35:25 +00:00
|
|
|
#else
|
|
|
|
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
|
|
|
|
struct dmaengine_unmap_data *unmap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline struct dmaengine_unmap_data *
|
|
|
|
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2013-10-18 17:35:24 +00:00
|
|
|
|
2013-10-18 17:35:23 +00:00
|
|
|
static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
2020-02-26 10:18:39 +00:00
|
|
|
if (!tx->unmap)
|
|
|
|
return;
|
|
|
|
|
|
|
|
dmaengine_unmap_put(tx->unmap);
|
|
|
|
tx->unmap = NULL;
|
2013-10-18 17:35:23 +00:00
|
|
|
}
|
|
|
|
|
2010-10-07 23:44:50 +00:00
|
|
|
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2010-05-17 23:24:16 +00:00
|
|
|
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
|
|
|
|
{
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
spin_lock_bh(&txd->lock);
|
|
|
|
}
|
|
|
|
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
spin_unlock_bh(&txd->lock);
|
|
|
|
}
|
|
|
|
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
|
|
|
|
{
|
|
|
|
txd->next = next;
|
|
|
|
next->parent = txd;
|
|
|
|
}
|
|
|
|
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
txd->parent = NULL;
|
|
|
|
}
|
|
|
|
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
txd->next = NULL;
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return txd->parent;
|
|
|
|
}
|
|
|
|
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
|
|
|
|
{
|
|
|
|
return txd->next;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-03-26 23:50:49 +00:00
|
|
|
/**
|
|
|
|
* struct dma_tx_state - filled in to report the status of
|
|
|
|
* a transfer.
|
|
|
|
* @last: last completed DMA cookie
|
|
|
|
* @used: last issued DMA cookie (i.e. the one in progress)
|
|
|
|
* @residue: the remaining number of bytes left to transmit
|
|
|
|
* on the selected transfer for states DMA_IN_PROGRESS and
|
|
|
|
* DMA_PAUSED if this is implemented in the driver, else 0
|
2019-12-23 11:04:45 +00:00
|
|
|
* @in_flight_bytes: amount of data in bytes cached by the DMA.
|
2010-03-26 23:50:49 +00:00
|
|
|
*/
|
|
|
|
struct dma_tx_state {
|
|
|
|
dma_cookie_t last;
|
|
|
|
dma_cookie_t used;
|
|
|
|
u32 residue;
|
2019-12-23 11:04:45 +00:00
|
|
|
u32 in_flight_bytes;
|
2010-03-26 23:50:49 +00:00
|
|
|
};
|
|
|
|
|
2015-07-20 08:41:32 +00:00
|
|
|
/**
|
|
|
|
* enum dmaengine_alignment - defines alignment of the DMA async tx
|
|
|
|
* buffers
|
|
|
|
*/
|
|
|
|
enum dmaengine_alignment {
|
|
|
|
DMAENGINE_ALIGN_1_BYTE = 0,
|
|
|
|
DMAENGINE_ALIGN_2_BYTES = 1,
|
|
|
|
DMAENGINE_ALIGN_4_BYTES = 2,
|
|
|
|
DMAENGINE_ALIGN_8_BYTES = 3,
|
|
|
|
DMAENGINE_ALIGN_16_BYTES = 4,
|
|
|
|
DMAENGINE_ALIGN_32_BYTES = 5,
|
|
|
|
DMAENGINE_ALIGN_64_BYTES = 6,
|
|
|
|
};
|
|
|
|
|
dmaengine: core: Introduce new, universal API to request a channel
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any channel matching with the requested capabilities, can be
used to request channel for memcpy, memset, xor, etc where no hardware
synchronization is needed.
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
To request a slave channel. The dma_request_chan() will try to find the
channel via DT, ACPI or in case if the kernel booted in non DT/ACPI mode
it will use a filter lookup table and retrieves the needed information from
the dma_slave_map provided by the DMA drivers.
This legacy mode needs changes in platform code, in dmaengine drivers and
finally the dmaengine user drivers can be converted:
For each dmaengine driver an array of DMA device, slave and the parameter
for the filter function needs to be added:
static const struct dma_slave_map da830_edma_map[] = {
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
};
This information is going to be needed by the dmaengine driver, so
modification to the platform_data is needed, and the driver map should be
added to the pdata of the DMA driver:
da8xx_edma0_pdata.slave_map = da830_edma_map;
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
The DMA driver then needs to configure the needed device -> filter_fn
mapping before it registers with dma_async_device_register() :
ecc->dma_slave.filter_map.map = info->slave_map;
ecc->dma_slave.filter_map.mapcnt = info->slavecnt;
ecc->dma_slave.filter_map.fn = edma_filter_fn;
When neither DT or ACPI lookup is available the dma_request_chan() will
try to match the requester's device name with the filter_map's list of
device names, when a match found it will use the information from the
dma_slave_map to get the channel with the dma_get_channel() internal
function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-14 20:47:40 +00:00
|
|
|
/**
|
|
|
|
* struct dma_slave_map - associates slave device and it's slave channel with
|
|
|
|
* parameter to be used by a filter function
|
|
|
|
* @devname: name of the device
|
|
|
|
* @slave: slave channel name
|
|
|
|
* @param: opaque parameter to pass to struct dma_filter.fn
|
|
|
|
*/
|
|
|
|
struct dma_slave_map {
|
|
|
|
const char *devname;
|
|
|
|
const char *slave;
|
|
|
|
void *param;
|
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct dma_filter - information for slave device/channel to filter_fn/param
|
|
|
|
* mapping
|
|
|
|
* @fn: filter function callback
|
|
|
|
* @mapcnt: number of slave device/channel in the map
|
|
|
|
* @map: array of channel to filter mapping data
|
|
|
|
*/
|
|
|
|
struct dma_filter {
|
|
|
|
dma_filter_fn fn;
|
|
|
|
int mapcnt;
|
|
|
|
const struct dma_slave_map *map;
|
|
|
|
};
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
/**
|
|
|
|
* struct dma_device - info on the entity supplying DMA services
|
|
|
|
* @chancnt: how many DMA channels are supported
|
2009-03-06 11:07:14 +00:00
|
|
|
* @privatecnt: how many DMA channels are requested by dma_request_channel
|
2006-05-24 00:18:44 +00:00
|
|
|
* @channels: the list of struct dma_chan
|
|
|
|
* @global_node: list_head for global dma_device_list
|
dmaengine: core: Introduce new, universal API to request a channel
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any channel matching with the requested capabilities, can be
used to request channel for memcpy, memset, xor, etc where no hardware
synchronization is needed.
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
To request a slave channel. The dma_request_chan() will try to find the
channel via DT, ACPI or in case if the kernel booted in non DT/ACPI mode
it will use a filter lookup table and retrieves the needed information from
the dma_slave_map provided by the DMA drivers.
This legacy mode needs changes in platform code, in dmaengine drivers and
finally the dmaengine user drivers can be converted:
For each dmaengine driver an array of DMA device, slave and the parameter
for the filter function needs to be added:
static const struct dma_slave_map da830_edma_map[] = {
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
};
This information is going to be needed by the dmaengine driver, so
modification to the platform_data is needed, and the driver map should be
added to the pdata of the DMA driver:
da8xx_edma0_pdata.slave_map = da830_edma_map;
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
The DMA driver then needs to configure the needed device -> filter_fn
mapping before it registers with dma_async_device_register() :
ecc->dma_slave.filter_map.map = info->slave_map;
ecc->dma_slave.filter_map.mapcnt = info->slavecnt;
ecc->dma_slave.filter_map.fn = edma_filter_fn;
When neither DT or ACPI lookup is available the dma_request_chan() will
try to match the requester's device name with the filter_map's list of
device names, when a match found it will use the information from the
dma_slave_map to get the channel with the dma_get_channel() internal
function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-14 20:47:40 +00:00
|
|
|
* @filter: information for device/slave to filter function/param mapping
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @cap_mask: one or more dma_capability flags
|
2019-12-23 11:04:44 +00:00
|
|
|
* @desc_metadata_modes: supported metadata modes by the DMA device
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @max_xor: maximum number of xor sources, 0 if no capability
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
* @max_pq: maximum number of PQ sources and PQ-continue capability
|
2009-09-09 00:42:53 +00:00
|
|
|
* @copy_align: alignment shift for memcpy operations
|
|
|
|
* @xor_align: alignment shift for xor operations
|
|
|
|
* @pq_align: alignment shift for pq operations
|
2015-05-18 11:46:15 +00:00
|
|
|
* @fill_align: alignment shift for memset operations
|
2006-07-04 02:44:51 +00:00
|
|
|
* @dev_id: unique device ID
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @dev: struct device reference for dma mapping api
|
2019-12-16 19:01:16 +00:00
|
|
|
* @owner: owner module (automatically set based on the provided dev)
|
2014-11-17 13:42:04 +00:00
|
|
|
* @src_addr_widths: bit mask of src addr widths the device supports
|
2017-09-11 23:44:45 +00:00
|
|
|
* Width is specified in bytes, e.g. for a device supporting
|
|
|
|
* a width of 4 the mask should have BIT(4) set.
|
2014-11-17 13:42:04 +00:00
|
|
|
* @dst_addr_widths: bit mask of dst addr widths the device supports
|
2017-09-11 23:44:45 +00:00
|
|
|
* @directions: bit mask of slave directions the device supports.
|
|
|
|
* Since the enum dma_transfer_direction is not defined as bit flag for
|
|
|
|
* each type, the dma controller should set BIT(<TYPE>) and same
|
|
|
|
* should be checked by controller as well
|
2020-07-23 00:58:41 +00:00
|
|
|
* @min_burst: min burst capability per-transfer
|
2016-01-22 11:06:50 +00:00
|
|
|
* @max_burst: max burst capability per-transfer
|
2020-07-23 00:58:42 +00:00
|
|
|
* @max_sg_burst: max number of SG list entries executed in a single burst
|
|
|
|
* DMA tansaction with no software intervention for reinitialization.
|
|
|
|
* Zero value means unlimited number of entries.
|
2014-11-17 13:42:04 +00:00
|
|
|
* @residue_granularity: granularity of the transfer residue reported
|
|
|
|
* by tx_status
|
2006-07-04 02:44:51 +00:00
|
|
|
* @device_alloc_chan_resources: allocate resources and return the
|
|
|
|
* number of allocated descriptors
|
|
|
|
* @device_free_chan_resources: release DMA channel's resources
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @device_prep_dma_memcpy: prepares a memcpy operation
|
|
|
|
* @device_prep_dma_xor: prepares a xor operation
|
2009-04-08 21:28:37 +00:00
|
|
|
* @device_prep_dma_xor_val: prepares a xor validation operation
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
* @device_prep_dma_pq: prepares a pq operation
|
|
|
|
* @device_prep_dma_pq_val: prepares a pqzero_sum operation
|
2015-05-18 11:46:15 +00:00
|
|
|
* @device_prep_dma_memset: prepares a memset operation
|
2015-07-06 10:19:23 +00:00
|
|
|
* @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @device_prep_dma_interrupt: prepares an end of chain interrupt operation
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 18:59:35 +00:00
|
|
|
* @device_prep_slave_sg: prepares a slave dma operation
|
2010-09-30 13:56:32 +00:00
|
|
|
* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
|
|
|
|
* The function takes a buffer of size buf_len. The callback function will
|
|
|
|
* be called after period_len bytes have been transferred.
|
2011-10-13 07:03:30 +00:00
|
|
|
* @device_prep_interleaved_dma: Transfer expression in a generic way.
|
2015-09-30 01:09:37 +00:00
|
|
|
* @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
|
2020-07-23 00:58:43 +00:00
|
|
|
* @device_caps: May be used to override the generic DMA slave capabilities
|
|
|
|
* with per-channel specific ones
|
2014-11-17 13:42:00 +00:00
|
|
|
* @device_config: Pushes a new configuration to a channel, return 0 or an error
|
|
|
|
* code
|
2014-11-17 13:42:01 +00:00
|
|
|
* @device_pause: Pauses any transfer happening on a channel. Returns
|
|
|
|
* 0 or an error code
|
|
|
|
* @device_resume: Resumes any transfer on a channel previously
|
|
|
|
* paused. Returns 0 or an error code
|
2014-11-17 13:42:02 +00:00
|
|
|
* @device_terminate_all: Aborts all transfers on a channel. Returns 0
|
|
|
|
* or an error code
|
2015-10-20 09:46:28 +00:00
|
|
|
* @device_synchronize: Synchronizes the termination of a transfers to the
|
|
|
|
* current context.
|
2010-03-26 23:50:49 +00:00
|
|
|
* @device_tx_status: poll for transaction completion, the optional
|
|
|
|
* txstate parameter can be supplied with a pointer to get a
|
2011-03-31 01:57:33 +00:00
|
|
|
* struct with auxiliary transfer status information, otherwise the call
|
2010-03-26 23:50:49 +00:00
|
|
|
* will just return a simple status code
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* @device_issue_pending: push pending transactions to hardware
|
2015-10-13 19:54:29 +00:00
|
|
|
* @descriptor_reuse: a submitted transfer can be resubmitted after completion
|
2019-12-16 19:01:19 +00:00
|
|
|
* @device_release: called sometime atfer dma_async_device_unregister() is
|
|
|
|
* called and there are no further references to this structure. This
|
|
|
|
* must be implemented to free resources however many existing drivers
|
|
|
|
* do not and are therefore not safe to unbind while in use.
|
2020-03-06 14:28:37 +00:00
|
|
|
* @dbg_summary_show: optional routine to show contents in debugfs; default code
|
|
|
|
* will be used when this is omitted, but custom code can show extra,
|
|
|
|
* controller specific information.
|
2006-05-24 00:18:44 +00:00
|
|
|
*/
|
|
|
|
struct dma_device {
|
2019-12-16 19:01:19 +00:00
|
|
|
struct kref ref;
|
2006-05-24 00:18:44 +00:00
|
|
|
unsigned int chancnt;
|
2009-03-06 11:07:14 +00:00
|
|
|
unsigned int privatecnt;
|
2006-05-24 00:18:44 +00:00
|
|
|
struct list_head channels;
|
|
|
|
struct list_head global_node;
|
dmaengine: core: Introduce new, universal API to request a channel
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any channel matching with the requested capabilities, can be
used to request channel for memcpy, memset, xor, etc where no hardware
synchronization is needed.
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
To request a slave channel. The dma_request_chan() will try to find the
channel via DT, ACPI or in case if the kernel booted in non DT/ACPI mode
it will use a filter lookup table and retrieves the needed information from
the dma_slave_map provided by the DMA drivers.
This legacy mode needs changes in platform code, in dmaengine drivers and
finally the dmaengine user drivers can be converted:
For each dmaengine driver an array of DMA device, slave and the parameter
for the filter function needs to be added:
static const struct dma_slave_map da830_edma_map[] = {
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
};
This information is going to be needed by the dmaengine driver, so
modification to the platform_data is needed, and the driver map should be
added to the pdata of the DMA driver:
da8xx_edma0_pdata.slave_map = da830_edma_map;
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
The DMA driver then needs to configure the needed device -> filter_fn
mapping before it registers with dma_async_device_register() :
ecc->dma_slave.filter_map.map = info->slave_map;
ecc->dma_slave.filter_map.mapcnt = info->slavecnt;
ecc->dma_slave.filter_map.fn = edma_filter_fn;
When neither DT or ACPI lookup is available the dma_request_chan() will
try to match the requester's device name with the filter_map's list of
device names, when a match found it will use the information from the
dma_slave_map to get the channel with the dma_get_channel() internal
function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-14 20:47:40 +00:00
|
|
|
struct dma_filter filter;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
dma_cap_mask_t cap_mask;
|
2019-12-23 11:04:44 +00:00
|
|
|
enum dma_desc_metadata_mode desc_metadata_modes;
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
unsigned short max_xor;
|
|
|
|
unsigned short max_pq;
|
2015-07-20 08:41:32 +00:00
|
|
|
enum dmaengine_alignment copy_align;
|
|
|
|
enum dmaengine_alignment xor_align;
|
|
|
|
enum dmaengine_alignment pq_align;
|
|
|
|
enum dmaengine_alignment fill_align;
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
#define DMA_HAS_PQ_CONTINUE (1 << 15)
|
2006-05-24 00:18:44 +00:00
|
|
|
|
|
|
|
int dev_id;
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
struct device *dev;
|
2019-12-16 19:01:16 +00:00
|
|
|
struct module *owner;
|
2020-04-13 17:40:12 +00:00
|
|
|
struct ida chan_ida;
|
|
|
|
struct mutex chan_mutex; /* to protect chan_ida */
|
2006-05-24 00:18:44 +00:00
|
|
|
|
2014-11-17 13:42:04 +00:00
|
|
|
u32 src_addr_widths;
|
|
|
|
u32 dst_addr_widths;
|
|
|
|
u32 directions;
|
2020-07-23 00:58:41 +00:00
|
|
|
u32 min_burst;
|
2016-01-22 11:06:50 +00:00
|
|
|
u32 max_burst;
|
2020-07-23 00:58:42 +00:00
|
|
|
u32 max_sg_burst;
|
2015-10-13 19:54:29 +00:00
|
|
|
bool descriptor_reuse;
|
2014-11-17 13:42:04 +00:00
|
|
|
enum dma_residue_granularity residue_granularity;
|
|
|
|
|
2009-01-06 18:38:17 +00:00
|
|
|
int (*device_alloc_chan_resources)(struct dma_chan *chan);
|
2006-05-24 00:18:44 +00:00
|
|
|
void (*device_free_chan_resources)(struct dma_chan *chan);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
|
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
|
2014-11-17 13:41:57 +00:00
|
|
|
struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
|
2008-02-03 02:49:58 +00:00
|
|
|
size_t len, unsigned long flags);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
|
2014-11-17 13:41:57 +00:00
|
|
|
struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
|
2008-02-03 02:49:58 +00:00
|
|
|
unsigned int src_cnt, size_t len, unsigned long flags);
|
2009-04-08 21:28:37 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
|
2008-02-03 02:49:57 +00:00
|
|
|
struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
|
2009-08-30 02:09:26 +00:00
|
|
|
size_t len, enum sum_check_flags *result, unsigned long flags);
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
|
|
|
|
struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
|
|
|
|
unsigned int src_cnt, const unsigned char *scf,
|
|
|
|
size_t len, unsigned long flags);
|
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
|
|
|
|
struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
|
|
|
|
unsigned int src_cnt, const unsigned char *scf, size_t len,
|
|
|
|
enum sum_check_flags *pqres, unsigned long flags);
|
2015-05-18 11:46:15 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
|
|
|
|
struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
|
|
|
|
unsigned long flags);
|
2015-07-06 10:19:23 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sg,
|
|
|
|
unsigned int nents, int value, unsigned long flags);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
|
2008-04-18 03:17:26 +00:00
|
|
|
struct dma_chan *chan, unsigned long flags);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 18:59:35 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl,
|
2011-10-13 09:45:27 +00:00
|
|
|
unsigned int sg_len, enum dma_transfer_direction direction,
|
2012-03-08 20:35:13 +00:00
|
|
|
unsigned long flags, void *context);
|
2010-09-30 13:56:32 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
|
|
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
2012-03-08 20:35:13 +00:00
|
|
|
size_t period_len, enum dma_transfer_direction direction,
|
2014-08-01 10:20:10 +00:00
|
|
|
unsigned long flags);
|
2011-10-13 07:03:30 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
|
|
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
|
|
unsigned long flags);
|
2015-09-30 01:09:37 +00:00
|
|
|
struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
|
|
|
|
struct dma_chan *chan, dma_addr_t dst, u64 data,
|
|
|
|
unsigned long flags);
|
2014-11-17 13:42:00 +00:00
|
|
|
|
2020-07-23 00:58:43 +00:00
|
|
|
void (*device_caps)(struct dma_chan *chan,
|
|
|
|
struct dma_slave_caps *caps);
|
2014-11-17 13:42:00 +00:00
|
|
|
int (*device_config)(struct dma_chan *chan,
|
|
|
|
struct dma_slave_config *config);
|
2014-11-17 13:42:01 +00:00
|
|
|
int (*device_pause)(struct dma_chan *chan);
|
|
|
|
int (*device_resume)(struct dma_chan *chan);
|
2014-11-17 13:42:02 +00:00
|
|
|
int (*device_terminate_all)(struct dma_chan *chan);
|
2015-10-20 09:46:28 +00:00
|
|
|
void (*device_synchronize)(struct dma_chan *chan);
|
dmaengine: Add slave DMA interface
This patch adds the necessary interfaces to the DMA Engine framework
to use functionality found on most embedded DMA controllers: DMA from
and to I/O registers with hardware handshaking.
In this context, hardware hanshaking means that the peripheral that
owns the I/O registers in question is able to tell the DMA controller
when more data is available for reading, or when there is room for
more data to be written. This usually happens internally on the chip,
but these signals may also be exported outside the chip for things
like IDE DMA, etc.
A new struct dma_slave is introduced. This contains information that
the DMA engine driver needs to set up slave transfers to and from a
slave device. Most engines supporting DMA slave transfers will want to
extend this structure with controller-specific parameters. This
additional information is usually passed from the platform/board code
through the client driver.
A "slave" pointer is added to the dma_client struct. This must point
to a valid dma_slave structure iff the DMA_SLAVE capability is
requested. The DMA engine driver may use this information in its
device_alloc_chan_resources hook to configure the DMA controller for
slave transfers from and to the given slave device.
A new operation for preparing slave DMA transfers is added to struct
dma_device. This takes a scatterlist and returns a single descriptor
representing the whole transfer.
Another new operation for terminating all pending transfers is added as
well. The latter is needed because there may be errors outside the scope
of the DMA Engine framework that may require DMA operations to be
terminated prematurely.
DMA Engine drivers may extend the dma_device, dma_chan and/or
dma_slave_descriptor structures to allow controller-specific
operations. The client driver can detect such extensions by looking at
the DMA Engine's struct device, or it can request a specific DMA
Engine device by setting the dma_dev field in struct dma_slave.
dmaslave interface changes since v4:
* Fix checkpatch errors
* Fix changelog (there are no slave descriptors anymore)
dmaslave interface changes since v3:
* Use dma_data_direction instead of a new enum
* Submit slave transfers as scatterlists
* Remove the DMA slave descriptor struct
dmaslave interface changes since v2:
* Add a dma_dev field to struct dma_slave. If set, the client can
only be bound to the DMA controller that corresponds to this
device. This allows controller-specific extensions of the
dma_slave structure; if the device matches, the controller may
safely assume its extensions are present.
* Move reg_width into struct dma_slave as there are currently no
users that need to be able to set the width on a per-transfer
basis.
dmaslave interface changes since v1:
* Drop the set_direction and set_width descriptor hooks. Pass the
direction and width to the prep function instead.
* Declare a dma_slave struct with fixed information about a slave,
i.e. register addresses, handshake interfaces and such.
* Add pointer to a dma_slave struct to dma_client. Can be NULL if
the DMA_SLAVE capability isn't requested.
* Drop the set_slave device hook since the alloc_chan_resources hook
now has enough information to set up the channel for slave
transfers.
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2008-07-08 18:59:35 +00:00
|
|
|
|
2010-03-26 23:50:49 +00:00
|
|
|
enum dma_status (*device_tx_status)(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie,
|
|
|
|
struct dma_tx_state *txstate);
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
void (*device_issue_pending)(struct dma_chan *chan);
|
2019-12-16 19:01:19 +00:00
|
|
|
void (*device_release)(struct dma_device *dev);
|
2020-03-06 14:28:37 +00:00
|
|
|
/* debugfs support */
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
|
|
void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
|
2020-03-06 14:28:39 +00:00
|
|
|
struct dentry *dbg_dev_root;
|
2020-03-06 14:28:37 +00:00
|
|
|
#endif
|
2006-05-24 00:18:44 +00:00
|
|
|
};
|
|
|
|
|
2010-09-30 13:56:33 +00:00
|
|
|
static inline int dmaengine_slave_config(struct dma_chan *chan,
|
|
|
|
struct dma_slave_config *config)
|
|
|
|
{
|
2014-11-17 13:42:00 +00:00
|
|
|
if (chan->device->device_config)
|
|
|
|
return chan->device->device_config(chan, config);
|
|
|
|
|
2014-11-17 13:42:54 +00:00
|
|
|
return -ENOSYS;
|
2010-09-30 13:56:33 +00:00
|
|
|
}
|
|
|
|
|
2013-01-10 08:52:56 +00:00
|
|
|
static inline bool is_slave_direction(enum dma_transfer_direction direction)
|
|
|
|
{
|
|
|
|
return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
|
|
|
|
}
|
|
|
|
|
2011-07-25 14:27:52 +00:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
|
2012-04-25 18:50:53 +00:00
|
|
|
struct dma_chan *chan, dma_addr_t buf, size_t len,
|
2011-10-13 09:45:27 +00:00
|
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
2011-07-25 14:27:52 +00:00
|
|
|
{
|
|
|
|
struct scatterlist sg;
|
2012-04-25 18:50:53 +00:00
|
|
|
sg_init_table(&sg, 1);
|
|
|
|
sg_dma_address(&sg) = buf;
|
|
|
|
sg_dma_len(&sg) = len;
|
2011-07-25 14:27:52 +00:00
|
|
|
|
2016-04-12 15:37:06 +00:00
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
|
|
|
|
return NULL;
|
|
|
|
|
2012-03-08 20:35:13 +00:00
|
|
|
return chan->device->device_prep_slave_sg(chan, &sg, 1,
|
|
|
|
dir, flags, NULL);
|
2011-07-25 14:27:52 +00:00
|
|
|
}
|
|
|
|
|
2012-03-08 21:11:18 +00:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
|
|
|
|
enum dma_transfer_direction dir, unsigned long flags)
|
|
|
|
{
|
2016-04-12 15:37:06 +00:00
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
|
|
|
|
return NULL;
|
|
|
|
|
2012-03-08 21:11:18 +00:00
|
|
|
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
|
2012-03-08 20:35:13 +00:00
|
|
|
dir, flags, NULL);
|
2012-03-08 21:11:18 +00:00
|
|
|
}
|
|
|
|
|
2012-05-31 23:26:38 +00:00
|
|
|
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
|
|
|
|
struct rio_dma_ext;
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
|
|
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
|
|
|
|
enum dma_transfer_direction dir, unsigned long flags,
|
|
|
|
struct rio_dma_ext *rio_ext)
|
|
|
|
{
|
2016-04-12 15:37:06 +00:00
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
|
|
|
|
return NULL;
|
|
|
|
|
2012-05-31 23:26:38 +00:00
|
|
|
return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
|
|
|
|
dir, flags, rio_ext);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-03-08 21:11:18 +00:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
|
|
|
|
struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
|
2012-09-24 07:58:04 +00:00
|
|
|
size_t period_len, enum dma_transfer_direction dir,
|
|
|
|
unsigned long flags)
|
2012-03-08 21:11:18 +00:00
|
|
|
{
|
2016-04-12 15:37:06 +00:00
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
|
|
|
|
return NULL;
|
|
|
|
|
2012-03-08 21:11:18 +00:00
|
|
|
return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
|
2014-08-01 10:20:10 +00:00
|
|
|
period_len, dir, flags);
|
2012-11-06 13:32:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
|
|
|
|
struct dma_chan *chan, struct dma_interleaved_template *xt,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
2016-04-12 15:37:06 +00:00
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
|
|
|
|
return NULL;
|
2020-07-17 01:33:34 +00:00
|
|
|
if (flags & DMA_PREP_REPEAT &&
|
|
|
|
!test_bit(DMA_REPEAT, chan->device->cap_mask.bits))
|
|
|
|
return NULL;
|
2016-04-12 15:37:06 +00:00
|
|
|
|
2012-11-06 13:32:39 +00:00
|
|
|
return chan->device->device_prep_interleaved_dma(chan, xt, flags);
|
2011-07-25 14:27:52 +00:00
|
|
|
}
|
|
|
|
|
2015-05-18 11:46:15 +00:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
|
|
|
|
struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
2016-04-12 15:37:06 +00:00
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
|
2015-05-18 11:46:15 +00:00
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return chan->device->device_prep_dma_memset(chan, dest, value,
|
|
|
|
len, flags);
|
|
|
|
}
|
|
|
|
|
2017-01-27 16:42:01 +00:00
|
|
|
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
|
|
|
|
struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
|
|
|
|
size_t len, unsigned long flags)
|
|
|
|
{
|
|
|
|
if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return chan->device->device_prep_dma_memcpy(chan, dest, src,
|
|
|
|
len, flags);
|
|
|
|
}
|
|
|
|
|
2019-12-23 11:04:44 +00:00
|
|
|
static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
|
|
|
|
enum dma_desc_metadata_mode mode)
|
|
|
|
{
|
|
|
|
if (!chan)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return !!(chan->device->desc_metadata_modes & mode);
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
|
|
int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
|
|
|
|
void *data, size_t len);
|
|
|
|
void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
|
|
|
|
size_t *payload_len, size_t *max_len);
|
|
|
|
int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
|
|
|
|
size_t payload_len);
|
|
|
|
#else /* CONFIG_DMA_ENGINE */
|
|
|
|
static inline int dmaengine_desc_attach_metadata(
|
|
|
|
struct dma_async_tx_descriptor *desc, void *data, size_t len)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
static inline void *dmaengine_desc_get_metadata_ptr(
|
|
|
|
struct dma_async_tx_descriptor *desc, size_t *payload_len,
|
|
|
|
size_t *max_len)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline int dmaengine_desc_set_metadata_len(
|
|
|
|
struct dma_async_tx_descriptor *desc, size_t payload_len)
|
|
|
|
{
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_DMA_ENGINE */
|
|
|
|
|
2015-10-20 09:46:28 +00:00
|
|
|
/**
|
|
|
|
* dmaengine_terminate_all() - Terminate all active DMA transfers
|
|
|
|
* @chan: The channel for which to terminate the transfers
|
|
|
|
*
|
|
|
|
* This function is DEPRECATED use either dmaengine_terminate_sync() or
|
|
|
|
* dmaengine_terminate_async() instead.
|
|
|
|
*/
|
2010-09-30 13:56:33 +00:00
|
|
|
static inline int dmaengine_terminate_all(struct dma_chan *chan)
|
|
|
|
{
|
2014-11-17 13:42:02 +00:00
|
|
|
if (chan->device->device_terminate_all)
|
|
|
|
return chan->device->device_terminate_all(chan);
|
|
|
|
|
2014-11-17 13:42:54 +00:00
|
|
|
return -ENOSYS;
|
2010-09-30 13:56:33 +00:00
|
|
|
}
|
|
|
|
|
2015-10-20 09:46:28 +00:00
|
|
|
/**
|
|
|
|
* dmaengine_terminate_async() - Terminate all active DMA transfers
|
|
|
|
* @chan: The channel for which to terminate the transfers
|
|
|
|
*
|
|
|
|
* Calling this function will terminate all active and pending descriptors
|
|
|
|
* that have previously been submitted to the channel. It is not guaranteed
|
|
|
|
* though that the transfer for the active descriptor has stopped when the
|
|
|
|
* function returns. Furthermore it is possible the complete callback of a
|
|
|
|
* submitted transfer is still running when this function returns.
|
|
|
|
*
|
|
|
|
* dmaengine_synchronize() needs to be called before it is safe to free
|
|
|
|
* any memory that is accessed by previously submitted descriptors or before
|
|
|
|
* freeing any resources accessed from within the completion callback of any
|
2020-04-14 04:17:03 +00:00
|
|
|
* previously submitted descriptors.
|
2015-10-20 09:46:28 +00:00
|
|
|
*
|
|
|
|
* This function can be called from atomic context as well as from within a
|
|
|
|
* complete callback of a descriptor submitted on the same channel.
|
|
|
|
*
|
|
|
|
* If none of the two conditions above apply consider using
|
|
|
|
* dmaengine_terminate_sync() instead.
|
|
|
|
*/
|
|
|
|
static inline int dmaengine_terminate_async(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
if (chan->device->device_terminate_all)
|
|
|
|
return chan->device->device_terminate_all(chan);
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dmaengine_synchronize() - Synchronize DMA channel termination
|
|
|
|
* @chan: The channel to synchronize
|
|
|
|
*
|
|
|
|
* Synchronizes to the DMA channel termination to the current context. When this
|
|
|
|
* function returns it is guaranteed that all transfers for previously issued
|
2020-04-14 04:17:03 +00:00
|
|
|
* descriptors have stopped and it is safe to free the memory associated
|
2015-10-20 09:46:28 +00:00
|
|
|
* with them. Furthermore it is guaranteed that all complete callback functions
|
|
|
|
* for a previously submitted descriptor have finished running and it is safe to
|
|
|
|
* free resources accessed from within the complete callbacks.
|
|
|
|
*
|
|
|
|
* The behavior of this function is undefined if dma_async_issue_pending() has
|
|
|
|
* been called between dmaengine_terminate_async() and this function.
|
|
|
|
*
|
|
|
|
* This function must only be called from non-atomic context and must not be
|
|
|
|
* called from within a complete callback of a descriptor submitted on the same
|
|
|
|
* channel.
|
|
|
|
*/
|
|
|
|
static inline void dmaengine_synchronize(struct dma_chan *chan)
|
|
|
|
{
|
2015-11-23 10:06:43 +00:00
|
|
|
might_sleep();
|
|
|
|
|
2015-10-20 09:46:28 +00:00
|
|
|
if (chan->device->device_synchronize)
|
|
|
|
chan->device->device_synchronize(chan);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dmaengine_terminate_sync() - Terminate all active DMA transfers
|
|
|
|
* @chan: The channel for which to terminate the transfers
|
|
|
|
*
|
|
|
|
* Calling this function will terminate all active and pending transfers
|
|
|
|
* that have previously been submitted to the channel. It is similar to
|
|
|
|
* dmaengine_terminate_async() but guarantees that the DMA transfer has actually
|
|
|
|
* stopped and that all complete callbacks have finished running when the
|
|
|
|
* function returns.
|
|
|
|
*
|
|
|
|
* This function must only be called from non-atomic context and must not be
|
|
|
|
* called from within a complete callback of a descriptor submitted on the same
|
|
|
|
* channel.
|
|
|
|
*/
|
|
|
|
static inline int dmaengine_terminate_sync(struct dma_chan *chan)
|
|
|
|
{
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dmaengine_terminate_async(chan);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
dmaengine_synchronize(chan);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-09-30 13:56:33 +00:00
|
|
|
static inline int dmaengine_pause(struct dma_chan *chan)
|
|
|
|
{
|
2014-11-17 13:42:01 +00:00
|
|
|
if (chan->device->device_pause)
|
|
|
|
return chan->device->device_pause(chan);
|
|
|
|
|
2014-11-17 13:42:54 +00:00
|
|
|
return -ENOSYS;
|
2010-09-30 13:56:33 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline int dmaengine_resume(struct dma_chan *chan)
|
|
|
|
{
|
2014-11-17 13:42:01 +00:00
|
|
|
if (chan->device->device_resume)
|
|
|
|
return chan->device->device_resume(chan);
|
|
|
|
|
2014-11-17 13:42:54 +00:00
|
|
|
return -ENOSYS;
|
2010-09-30 13:56:33 +00:00
|
|
|
}
|
|
|
|
|
2012-06-11 18:11:40 +00:00
|
|
|
static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
|
|
|
|
dma_cookie_t cookie, struct dma_tx_state *state)
|
|
|
|
{
|
|
|
|
return chan->device->device_tx_status(chan, cookie, state);
|
|
|
|
}
|
|
|
|
|
2011-01-01 23:00:23 +00:00
|
|
|
static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
|
2010-09-30 13:56:33 +00:00
|
|
|
{
|
|
|
|
return desc->tx_submit(desc);
|
|
|
|
}
|
|
|
|
|
2015-07-20 08:41:32 +00:00
|
|
|
static inline bool dmaengine_check_align(enum dmaengine_alignment align,
|
|
|
|
size_t off1, size_t off2, size_t len)
|
2009-09-09 00:42:53 +00:00
|
|
|
{
|
2020-02-26 10:18:38 +00:00
|
|
|
return !(((1 << align) - 1) & (off1 | off2 | len));
|
2009-09-09 00:42:53 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->copy_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->xor_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->pq_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
2015-05-18 11:46:15 +00:00
|
|
|
static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
|
|
|
|
size_t off2, size_t len)
|
|
|
|
{
|
|
|
|
return dmaengine_check_align(dev->fill_align, off1, off2, len);
|
|
|
|
}
|
|
|
|
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
static inline void
|
|
|
|
dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
|
|
|
|
{
|
|
|
|
dma->max_pq = maxpq;
|
|
|
|
if (has_pq_continue)
|
|
|
|
dma->max_pq |= DMA_HAS_PQ_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dmaf_continue(enum dma_ctrl_flags flags)
|
|
|
|
{
|
|
|
|
return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
|
|
|
|
{
|
|
|
|
enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
|
|
|
|
|
|
|
|
return (flags & mask) == mask;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
|
|
|
|
{
|
|
|
|
return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
|
|
|
|
}
|
|
|
|
|
2010-08-14 13:02:44 +00:00
|
|
|
static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
{
|
|
|
|
return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* dma_maxpq - reduce maxpq in the face of continued operations
|
|
|
|
* @dma - dma device with PQ capability
|
|
|
|
* @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
|
|
|
|
*
|
|
|
|
* When an engine does not support native continuation we need 3 extra
|
|
|
|
* source slots to reuse P and Q with the following coefficients:
|
|
|
|
* 1/ {00} * P : remove P from Q', but use it as a source for P'
|
|
|
|
* 2/ {01} * Q : use Q to continue Q' calculation
|
|
|
|
* 3/ {00} * Q : subtract Q from P' to cancel (2)
|
|
|
|
*
|
|
|
|
* In the case where P is disabled we only need 1 extra source:
|
|
|
|
* 1/ {01} * Q : use Q to continue Q' calculation
|
|
|
|
*/
|
|
|
|
static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
|
|
|
|
{
|
|
|
|
if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
|
|
|
|
return dma_dev_to_maxpq(dma);
|
2020-02-26 10:18:40 +00:00
|
|
|
if (dmaf_p_disabled_continue(flags))
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
return dma_dev_to_maxpq(dma) - 1;
|
2020-02-26 10:18:40 +00:00
|
|
|
if (dmaf_continue(flags))
|
async_tx: add support for asynchronous GF multiplication
[ Based on an original patch by Yuri Tikhonov ]
This adds support for doing asynchronous GF multiplication by adding
two additional functions to the async_tx API:
async_gen_syndrome() does simultaneous XOR and Galois field
multiplication of sources.
async_syndrome_val() validates the given source buffers against known P
and Q values.
When a request is made to run async_pq against more than the hardware
maximum number of supported sources we need to reuse the previous
generated P and Q values as sources into the next operation. Care must
be taken to remove Q from P' and P from Q'. For example to perform a 5
source pq op with hardware that only supports 4 sources at a time the
following approach is taken:
p, q = PQ(src0, src1, src2, src3, COEF({01}, {02}, {04}, {08}))
p', q' = PQ(p, q, q, src4, COEF({00}, {01}, {00}, {10}))
p' = p + q + q + src4 = p + src4
q' = {00}*p + {01}*q + {00}*q + {10}*src4 = q + {10}*src4
Note: 4 is the minimum acceptable maxpq otherwise we punt to
synchronous-software path.
The DMA_PREP_CONTINUE flag indicates to the driver to reuse p and q as
sources (in the above manner) and fill the remaining slots up to maxpq
with the new sources/coefficients.
Note1: Some devices have native support for P+Q continuation and can skip
this extra work. Devices with this capability can advertise it with
dma_set_maxpq. It is up to each driver how to handle the
DMA_PREP_CONTINUE flag.
Note2: The api supports disabling the generation of P when generating Q,
this is ignored by the synchronous path but is implemented by some dma
devices to save unnecessary writes. In this case the continuation
algorithm is simplified to only reuse Q as a source.
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Reviewed-by: Andre Noll <maan@systemlinux.org>
Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2009-07-14 19:20:36 +00:00
|
|
|
return dma_dev_to_maxpq(dma) - 3;
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
2015-05-27 14:01:52 +00:00
|
|
|
static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
|
|
|
|
size_t dir_icg)
|
|
|
|
{
|
|
|
|
if (inc) {
|
|
|
|
if (dir_icg)
|
|
|
|
return dir_icg;
|
2020-02-26 10:18:40 +00:00
|
|
|
if (sgl)
|
2015-05-27 14:01:52 +00:00
|
|
|
return icg;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
|
|
|
|
struct data_chunk *chunk)
|
|
|
|
{
|
|
|
|
return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
|
|
|
|
chunk->icg, chunk->dst_icg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
|
|
|
|
struct data_chunk *chunk)
|
|
|
|
{
|
|
|
|
return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
|
|
|
|
chunk->icg, chunk->src_icg);
|
|
|
|
}
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
/* --- public DMA engine API --- */
|
|
|
|
|
2009-01-11 08:20:39 +00:00
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
2009-01-06 18:38:17 +00:00
|
|
|
void dmaengine_get(void);
|
|
|
|
void dmaengine_put(void);
|
2009-01-11 08:20:39 +00:00
|
|
|
#else
|
|
|
|
static inline void dmaengine_get(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void dmaengine_put(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-03-25 16:13:25 +00:00
|
|
|
#ifdef CONFIG_ASYNC_TX_DMA
|
|
|
|
#define async_dmaengine_get() dmaengine_get()
|
|
|
|
#define async_dmaengine_put() dmaengine_put()
|
2010-10-07 23:44:50 +00:00
|
|
|
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
|
2009-09-09 00:42:51 +00:00
|
|
|
#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
|
|
|
|
#else
|
2009-03-25 16:13:25 +00:00
|
|
|
#define async_dma_find_channel(type) dma_find_channel(type)
|
2010-10-07 23:44:50 +00:00
|
|
|
#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
|
2009-03-25 16:13:25 +00:00
|
|
|
#else
|
|
|
|
static inline void async_dmaengine_get(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline void async_dmaengine_put(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
static inline struct dma_chan *
|
|
|
|
async_dma_find_channel(enum dma_transaction_type type)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2009-09-09 00:42:51 +00:00
|
|
|
#endif /* CONFIG_ASYNC_TX_DMA */
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
|
2013-12-30 20:37:29 +00:00
|
|
|
struct dma_chan *chan);
|
2006-05-24 00:18:44 +00:00
|
|
|
|
2008-07-18 00:59:56 +00:00
|
|
|
static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
{
|
2008-04-18 03:17:26 +00:00
|
|
|
tx->flags |= DMA_CTRL_ACK;
|
|
|
|
}
|
|
|
|
|
2009-01-19 22:36:21 +00:00
|
|
|
static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
tx->flags &= ~DMA_CTRL_ACK;
|
|
|
|
}
|
|
|
|
|
2008-07-18 00:59:56 +00:00
|
|
|
static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
|
2008-04-18 03:17:26 +00:00
|
|
|
{
|
2008-07-18 00:59:56 +00:00
|
|
|
return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
|
2006-05-24 00:18:44 +00:00
|
|
|
}
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
|
|
|
|
static inline void
|
|
|
|
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
2006-05-24 00:18:44 +00:00
|
|
|
{
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
set_bit(tx_type, dstp->bits);
|
|
|
|
}
|
2006-05-24 00:18:44 +00:00
|
|
|
|
2009-03-06 11:07:14 +00:00
|
|
|
#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
|
|
|
|
static inline void
|
|
|
|
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
|
|
|
|
{
|
|
|
|
clear_bit(tx_type, dstp->bits);
|
|
|
|
}
|
|
|
|
|
2009-01-06 18:38:15 +00:00
|
|
|
#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
|
|
|
|
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
|
|
|
|
{
|
|
|
|
bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
|
|
|
|
}
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
|
|
|
|
static inline int
|
|
|
|
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
|
|
|
|
{
|
|
|
|
return test_bit(tx_type, srcp->bits);
|
2006-05-24 00:18:44 +00:00
|
|
|
}
|
|
|
|
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
#define for_each_dma_cap_mask(cap, mask) \
|
2012-10-26 14:35:15 +00:00
|
|
|
for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
/**
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* dma_async_issue_pending - flush pending transactions to HW
|
2006-07-04 02:44:51 +00:00
|
|
|
* @chan: target DMA channel
|
2006-05-24 00:18:44 +00:00
|
|
|
*
|
|
|
|
* This allows drivers to push copies to HW in batches,
|
|
|
|
* reducing MMIO writes where possible.
|
|
|
|
*/
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
static inline void dma_async_issue_pending(struct dma_chan *chan)
|
2006-05-24 00:18:44 +00:00
|
|
|
{
|
2008-03-01 14:51:29 +00:00
|
|
|
chan->device->device_issue_pending(chan);
|
2006-05-24 00:18:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
* dma_async_is_tx_complete - poll for transaction completion
|
2006-05-24 00:18:44 +00:00
|
|
|
* @chan: DMA channel
|
|
|
|
* @cookie: transaction identifier to check status of
|
|
|
|
* @last: returns last completed cookie, can be NULL
|
|
|
|
* @used: returns last issued cookie, can be NULL
|
|
|
|
*
|
|
|
|
* If @last and @used are passed in, upon return they reflect the driver
|
|
|
|
* internal state and can be used with dma_async_is_complete() to check
|
|
|
|
* the status of multiple cookies without re-checking hardware state.
|
|
|
|
*/
|
dmaengine: refactor dmaengine around dma_async_tx_descriptor
The current dmaengine interface defines mutliple routines per operation,
i.e. dma_async_memcpy_buf_to_buf, dma_async_memcpy_buf_to_page etc. Adding
more operation types (xor, crc, etc) to this model would result in an
unmanageable number of method permutations.
Are we really going to add a set of hooks for each DMA engine
whizbang feature?
- Jeff Garzik
The descriptor creation process is refactored using the new common
dma_async_tx_descriptor structure. Instead of per driver
do_<operation>_<dest>_to_<src> methods, drivers integrate
dma_async_tx_descriptor into their private software descriptor and then
define a 'prep' routine per operation. The prep routine allocates a
descriptor and ensures that the tx_set_src, tx_set_dest, tx_submit routines
are valid. Descriptor creation and submission becomes:
struct dma_device *dev;
struct dma_chan *chan;
struct dma_async_tx_descriptor *tx;
tx = dev->device_prep_dma_<operation>(chan, len, int_flag)
tx->tx_set_src(dma_addr_t, tx, index /* for multi-source ops */)
tx->tx_set_dest(dma_addr_t, tx, index)
tx->tx_submit(tx)
In addition to the refactoring, dma_async_tx_descriptor also lays the
groundwork for definining cross-channel-operation dependencies, and a
callback facility for asynchronous notification of operation completion.
Changelog:
* drop dma mapping methods, suggested by Chris Leech
* fix ioat_dma_dependency_added, also caught by Andrew Morton
* fix dma_sync_wait, change from Andrew Morton
* uninline large functions, change from Andrew Morton
* add tx->callback = NULL to dmaengine calls to interoperate with async_tx
calls
* hookup ioat_tx_submit
* convert channel capabilities to a 'cpumask_t like' bitmap
* removed DMA_TX_ARRAY_INIT, no longer needed
* checkpatch.pl fixes
* make set_src, set_dest, and tx_submit descriptor specific methods
* fixup git-ioat merge
* move group_list and phys to dma_async_tx_descriptor
Cc: Jeff Garzik <jeff@garzik.org>
Cc: Chris Leech <christopher.leech@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: David S. Miller <davem@davemloft.net>
2007-01-02 18:10:43 +00:00
|
|
|
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
|
2006-05-24 00:18:44 +00:00
|
|
|
dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
|
|
|
|
{
|
2010-03-26 23:50:49 +00:00
|
|
|
struct dma_tx_state state;
|
|
|
|
enum dma_status status;
|
|
|
|
|
|
|
|
status = chan->device->device_tx_status(chan, cookie, &state);
|
|
|
|
if (last)
|
|
|
|
*last = state.last;
|
|
|
|
if (used)
|
|
|
|
*used = state.used;
|
|
|
|
return status;
|
2006-05-24 00:18:44 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_async_is_complete - test a cookie against chan state
|
|
|
|
* @cookie: transaction identifier to test status of
|
|
|
|
* @last_complete: last know completed transaction
|
|
|
|
* @last_used: last cookie value handed out
|
|
|
|
*
|
2012-11-08 10:01:01 +00:00
|
|
|
* dma_async_is_complete() is used in dma_async_is_tx_complete()
|
2008-04-21 22:38:45 +00:00
|
|
|
* the test logic is separated for lightweight testing of multiple cookies
|
2006-05-24 00:18:44 +00:00
|
|
|
*/
|
|
|
|
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
|
|
|
|
dma_cookie_t last_complete, dma_cookie_t last_used)
|
|
|
|
{
|
|
|
|
if (last_complete <= last_used) {
|
|
|
|
if ((cookie <= last_complete) || (cookie > last_used))
|
2013-10-16 07:59:02 +00:00
|
|
|
return DMA_COMPLETE;
|
2006-05-24 00:18:44 +00:00
|
|
|
} else {
|
|
|
|
if ((cookie <= last_complete) && (cookie > last_used))
|
2013-10-16 07:59:02 +00:00
|
|
|
return DMA_COMPLETE;
|
2006-05-24 00:18:44 +00:00
|
|
|
}
|
|
|
|
return DMA_IN_PROGRESS;
|
|
|
|
}
|
|
|
|
|
2010-03-26 23:52:10 +00:00
|
|
|
static inline void
|
|
|
|
dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
|
|
|
|
{
|
2020-02-26 10:18:39 +00:00
|
|
|
if (!st)
|
|
|
|
return;
|
|
|
|
|
|
|
|
st->last = last;
|
|
|
|
st->used = used;
|
|
|
|
st->residue = residue;
|
2010-03-26 23:52:10 +00:00
|
|
|
}
|
|
|
|
|
2009-01-06 00:14:31 +00:00
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
2013-09-09 23:51:59 +00:00
|
|
|
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
|
|
|
|
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
|
2009-01-06 00:14:31 +00:00
|
|
|
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
|
2009-01-19 22:33:14 +00:00
|
|
|
void dma_issue_pending_all(void);
|
2013-03-25 12:23:52 +00:00
|
|
|
struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
|
2019-05-20 11:32:14 +00:00
|
|
|
dma_filter_fn fn, void *fn_param,
|
|
|
|
struct device_node *np);
|
2013-02-24 15:36:09 +00:00
|
|
|
struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
|
dmaengine: core: Introduce new, universal API to request a channel
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any channel matching with the requested capabilities, can be
used to request channel for memcpy, memset, xor, etc where no hardware
synchronization is needed.
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
To request a slave channel. The dma_request_chan() will try to find the
channel via DT, ACPI or in case if the kernel booted in non DT/ACPI mode
it will use a filter lookup table and retrieves the needed information from
the dma_slave_map provided by the DMA drivers.
This legacy mode needs changes in platform code, in dmaengine drivers and
finally the dmaengine user drivers can be converted:
For each dmaengine driver an array of DMA device, slave and the parameter
for the filter function needs to be added:
static const struct dma_slave_map da830_edma_map[] = {
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
};
This information is going to be needed by the dmaengine driver, so
modification to the platform_data is needed, and the driver map should be
added to the pdata of the DMA driver:
da8xx_edma0_pdata.slave_map = da830_edma_map;
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
The DMA driver then needs to configure the needed device -> filter_fn
mapping before it registers with dma_async_device_register() :
ecc->dma_slave.filter_map.map = info->slave_map;
ecc->dma_slave.filter_map.mapcnt = info->slavecnt;
ecc->dma_slave.filter_map.fn = edma_filter_fn;
When neither DT or ACPI lookup is available the dma_request_chan() will
try to match the requester's device name with the filter_map's list of
device names, when a match found it will use the information from the
dma_slave_map to get the channel with the dma_get_channel() internal
function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-14 20:47:40 +00:00
|
|
|
|
|
|
|
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
|
|
|
|
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
|
|
|
|
|
2010-12-22 13:46:46 +00:00
|
|
|
void dma_release_channel(struct dma_chan *chan);
|
2015-01-19 11:54:27 +00:00
|
|
|
int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
|
2009-01-06 00:14:31 +00:00
|
|
|
#else
|
2013-09-09 23:51:59 +00:00
|
|
|
static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
|
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
|
|
|
|
{
|
2013-10-16 07:59:02 +00:00
|
|
|
return DMA_COMPLETE;
|
2013-09-09 23:51:59 +00:00
|
|
|
}
|
2009-01-06 00:14:31 +00:00
|
|
|
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
2013-10-16 07:59:02 +00:00
|
|
|
return DMA_COMPLETE;
|
2009-01-06 00:14:31 +00:00
|
|
|
}
|
2009-01-19 22:33:14 +00:00
|
|
|
static inline void dma_issue_pending_all(void)
|
|
|
|
{
|
2010-12-22 13:46:46 +00:00
|
|
|
}
|
2013-03-25 12:23:52 +00:00
|
|
|
static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
|
2019-05-20 11:32:14 +00:00
|
|
|
dma_filter_fn fn,
|
|
|
|
void *fn_param,
|
|
|
|
struct device_node *np)
|
2010-12-22 13:46:46 +00:00
|
|
|
{
|
|
|
|
return NULL;
|
|
|
|
}
|
2012-09-14 22:41:57 +00:00
|
|
|
static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
|
2013-02-24 15:36:09 +00:00
|
|
|
const char *name)
|
2012-09-14 22:41:57 +00:00
|
|
|
{
|
2012-09-25 10:48:55 +00:00
|
|
|
return NULL;
|
2012-09-14 22:41:57 +00:00
|
|
|
}
|
dmaengine: core: Introduce new, universal API to request a channel
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any channel matching with the requested capabilities, can be
used to request channel for memcpy, memset, xor, etc where no hardware
synchronization is needed.
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
To request a slave channel. The dma_request_chan() will try to find the
channel via DT, ACPI or in case if the kernel booted in non DT/ACPI mode
it will use a filter lookup table and retrieves the needed information from
the dma_slave_map provided by the DMA drivers.
This legacy mode needs changes in platform code, in dmaengine drivers and
finally the dmaengine user drivers can be converted:
For each dmaengine driver an array of DMA device, slave and the parameter
for the filter function needs to be added:
static const struct dma_slave_map da830_edma_map[] = {
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
};
This information is going to be needed by the dmaengine driver, so
modification to the platform_data is needed, and the driver map should be
added to the pdata of the DMA driver:
da8xx_edma0_pdata.slave_map = da830_edma_map;
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
The DMA driver then needs to configure the needed device -> filter_fn
mapping before it registers with dma_async_device_register() :
ecc->dma_slave.filter_map.map = info->slave_map;
ecc->dma_slave.filter_map.mapcnt = info->slavecnt;
ecc->dma_slave.filter_map.fn = edma_filter_fn;
When neither DT or ACPI lookup is available the dma_request_chan() will
try to match the requester's device name with the filter_map's list of
device names, when a match found it will use the information from the
dma_slave_map to get the channel with the dma_get_channel() internal
function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-14 20:47:40 +00:00
|
|
|
static inline struct dma_chan *dma_request_chan(struct device *dev,
|
|
|
|
const char *name)
|
|
|
|
{
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
}
|
|
|
|
static inline struct dma_chan *dma_request_chan_by_mask(
|
|
|
|
const dma_cap_mask_t *mask)
|
|
|
|
{
|
|
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
}
|
2010-12-22 13:46:46 +00:00
|
|
|
static inline void dma_release_channel(struct dma_chan *chan)
|
|
|
|
{
|
2009-01-19 22:33:14 +00:00
|
|
|
}
|
2015-01-19 11:54:27 +00:00
|
|
|
static inline int dma_get_slave_caps(struct dma_chan *chan,
|
|
|
|
struct dma_slave_caps *caps)
|
|
|
|
{
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
2009-01-06 00:14:31 +00:00
|
|
|
#endif
|
2006-05-24 00:18:44 +00:00
|
|
|
|
dmaengine: core: Introduce new, universal API to request a channel
The two API function can cover most, if not all current APIs used to
request a channel. With minimal effort dmaengine drivers, platforms and
dmaengine user drivers can be converted to use the two function.
struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
To request any channel matching with the requested capabilities, can be
used to request channel for memcpy, memset, xor, etc where no hardware
synchronization is needed.
struct dma_chan *dma_request_chan(struct device *dev, const char *name);
To request a slave channel. The dma_request_chan() will try to find the
channel via DT, ACPI or in case if the kernel booted in non DT/ACPI mode
it will use a filter lookup table and retrieves the needed information from
the dma_slave_map provided by the DMA drivers.
This legacy mode needs changes in platform code, in dmaengine drivers and
finally the dmaengine user drivers can be converted:
For each dmaengine driver an array of DMA device, slave and the parameter
for the filter function needs to be added:
static const struct dma_slave_map da830_edma_map[] = {
{ "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
{ "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
{ "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
{ "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
{ "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
{ "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
{ "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
{ "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
{ "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
{ "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
{ "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
{ "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
};
This information is going to be needed by the dmaengine driver, so
modification to the platform_data is needed, and the driver map should be
added to the pdata of the DMA driver:
da8xx_edma0_pdata.slave_map = da830_edma_map;
da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
The DMA driver then needs to configure the needed device -> filter_fn
mapping before it registers with dma_async_device_register() :
ecc->dma_slave.filter_map.map = info->slave_map;
ecc->dma_slave.filter_map.mapcnt = info->slavecnt;
ecc->dma_slave.filter_map.fn = edma_filter_fn;
When neither DT or ACPI lookup is available the dma_request_chan() will
try to match the requester's device name with the filter_map's list of
device names, when a match found it will use the information from the
dma_slave_map to get the channel with the dma_get_channel() internal
function.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-14 20:47:40 +00:00
|
|
|
#define dma_request_slave_channel_reason(dev, name) dma_request_chan(dev, name)
|
|
|
|
|
2015-08-05 03:12:05 +00:00
|
|
|
static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
struct dma_slave_caps caps;
|
2019-12-05 11:54:49 +00:00
|
|
|
int ret;
|
2015-08-05 03:12:05 +00:00
|
|
|
|
2019-12-05 11:54:49 +00:00
|
|
|
ret = dma_get_slave_caps(tx->chan, &caps);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2015-08-05 03:12:05 +00:00
|
|
|
|
2020-02-26 10:18:39 +00:00
|
|
|
if (!caps.descriptor_reuse)
|
2015-08-05 03:12:05 +00:00
|
|
|
return -EPERM;
|
2020-02-26 10:18:39 +00:00
|
|
|
|
|
|
|
tx->flags |= DMA_CTRL_REUSE;
|
|
|
|
return 0;
|
2015-08-05 03:12:05 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
tx->flags &= ~DMA_CTRL_REUSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
|
|
|
|
{
|
|
|
|
return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
|
|
|
|
{
|
|
|
|
/* this is supported for reusable desc, so check that */
|
2020-02-26 10:18:39 +00:00
|
|
|
if (!dmaengine_desc_test_reuse(desc))
|
2015-08-05 03:12:05 +00:00
|
|
|
return -EPERM;
|
2020-02-26 10:18:39 +00:00
|
|
|
|
|
|
|
return desc->desc_free(desc);
|
2015-08-05 03:12:05 +00:00
|
|
|
}
|
|
|
|
|
2006-05-24 00:18:44 +00:00
|
|
|
/* --- DMA device --- */
|
|
|
|
|
|
|
|
int dma_async_device_register(struct dma_device *device);
|
2018-07-26 06:45:53 +00:00
|
|
|
int dmaenginem_async_device_register(struct dma_device *device);
|
2006-05-24 00:18:44 +00:00
|
|
|
void dma_async_device_unregister(struct dma_device *device);
|
2020-01-21 23:43:53 +00:00
|
|
|
int dma_async_device_channel_register(struct dma_device *device,
|
|
|
|
struct dma_chan *chan);
|
|
|
|
void dma_async_device_channel_unregister(struct dma_device *device,
|
|
|
|
struct dma_chan *chan);
|
2009-01-06 00:14:31 +00:00
|
|
|
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
|
2019-05-20 11:32:14 +00:00
|
|
|
#define dma_request_channel(mask, x, y) \
|
|
|
|
__dma_request_channel(&(mask), x, y, NULL)
|
2013-02-01 18:22:52 +00:00
|
|
|
|
|
|
|
static inline struct dma_chan
|
2020-01-21 09:33:10 +00:00
|
|
|
*dma_request_slave_channel_compat(const dma_cap_mask_t mask,
|
2013-03-25 12:23:52 +00:00
|
|
|
dma_filter_fn fn, void *fn_param,
|
2015-08-12 08:30:59 +00:00
|
|
|
struct device *dev, const char *name)
|
2013-02-01 18:22:52 +00:00
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
|
|
|
|
chan = dma_request_slave_channel(dev, name);
|
|
|
|
if (chan)
|
|
|
|
return chan;
|
|
|
|
|
dmaengine: Stricter legacy checking in dma_request_slave_channel_compat()
dma_request_slave_channel_compat() is meant for drivers that support
both DT and legacy platform device based probing: if DT channel DMA
setup fails, it will fall back to platform data based DMA channel setup,
using hardcoded DMA channel IDs and a filter function.
However, if the DTS doesn't provide a "dmas" property for the device,
the fallback is also used. If the legacy filter function is not
hardcoded in the DMA slave driver, but comes from platform data, it will
be NULL. Then dma_request_slave_channel_compat() will succeed
incorrectly, and return a DMA channel, as a NULL legacy filter function
actually means "all channels are OK", not "do not match".
Later, when trying to use that DMA channel, it will fail with:
rcar-dmac e6700000.dma-controller: rcar_dmac_prep_slave_sg: bad parameter: len=1, id=-22
To fix this, ensure that both the filter function and the DMA channel ID
are not NULL before using the legacy fallback.
Note that some DMA slave drivers can handle this failure, and will fall
back to PIO.
See also commit 056f6c87028544de ("dmaengine: shdma: Make dummy
shdma_chan_filter() always return false"), which fixed the same issue
for the case where shdma_chan_filter() is hardcoded in a DMA slave
driver.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-08-17 13:08:55 +00:00
|
|
|
if (!fn || !fn_param)
|
|
|
|
return NULL;
|
|
|
|
|
2020-01-21 09:33:10 +00:00
|
|
|
return __dma_request_channel(&mask, fn, fn_param, NULL);
|
2013-02-01 18:22:52 +00:00
|
|
|
}
|
2019-12-23 11:04:46 +00:00
|
|
|
|
|
|
|
static inline char *
|
|
|
|
dmaengine_get_direction_text(enum dma_transfer_direction dir)
|
|
|
|
{
|
|
|
|
switch (dir) {
|
|
|
|
case DMA_DEV_TO_MEM:
|
|
|
|
return "DEV_TO_MEM";
|
|
|
|
case DMA_MEM_TO_DEV:
|
|
|
|
return "MEM_TO_DEV";
|
|
|
|
case DMA_MEM_TO_MEM:
|
|
|
|
return "MEM_TO_MEM";
|
|
|
|
case DMA_DEV_TO_DEV:
|
|
|
|
return "DEV_TO_DEV";
|
|
|
|
default:
|
2020-02-26 10:18:41 +00:00
|
|
|
return "invalid";
|
2019-12-23 11:04:46 +00:00
|
|
|
}
|
2013-02-01 18:22:52 +00:00
|
|
|
}
|
2006-05-24 00:18:44 +00:00
|
|
|
#endif /* DMAENGINE_H */
|