2009-11-29 15:15:25 +00:00
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/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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2011-02-25 00:01:34 +00:00
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* Copyright 2006-2010 Solarflare Communications Inc.
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2009-11-29 15:15:25 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/module.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2010-04-28 09:29:02 +00:00
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#include <linux/random.h>
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2009-11-29 15:15:25 +00:00
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#include "net_driver.h"
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#include "bitfield.h"
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#include "efx.h"
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#include "nic.h"
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#include "spi.h"
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2012-09-18 00:57:07 +00:00
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#include "farch_regs.h"
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2009-11-29 15:15:25 +00:00
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#include "io.h"
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#include "phy.h"
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#include "workarounds.h"
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#include "mcdi.h"
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#include "mcdi_pcol.h"
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2012-07-04 02:58:33 +00:00
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#include "selftest.h"
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2009-11-29 15:15:25 +00:00
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/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
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static void siena_init_wol(struct efx_nic *efx);
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static void siena_push_irq_moderation(struct efx_channel *channel)
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{
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efx_dword_t timer_cmd;
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if (channel->irq_moderation)
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EFX_POPULATE_DWORD_2(timer_cmd,
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FRF_CZ_TC_TIMER_MODE,
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FFE_CZ_TIMER_MODE_INT_HLDOFF,
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FRF_CZ_TC_TIMER_VAL,
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channel->irq_moderation - 1);
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else
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EFX_POPULATE_DWORD_2(timer_cmd,
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FRF_CZ_TC_TIMER_MODE,
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FFE_CZ_TIMER_MODE_DIS,
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FRF_CZ_TC_TIMER_VAL, 0);
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efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
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channel->channel);
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}
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2012-09-06 15:52:31 +00:00
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void siena_prepare_flush(struct efx_nic *efx)
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{
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if (efx->fc_disable++ == 0)
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efx_mcdi_set_mac(efx);
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}
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void siena_finish_flush(struct efx_nic *efx)
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{
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if (--efx->fc_disable == 0)
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efx_mcdi_set_mac(efx);
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}
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2009-11-29 15:15:25 +00:00
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static const struct efx_nic_register_test siena_register_tests[] = {
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{ FR_AZ_ADR_REGION,
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2010-02-03 09:31:40 +00:00
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EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
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2009-11-29 15:15:25 +00:00
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{ FR_CZ_USR_EV_CFG,
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EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_AZ_RX_CFG,
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EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
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{ FR_AZ_TX_CFG,
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EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
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{ FR_AZ_TX_RESERVED,
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EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
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{ FR_AZ_SRM_TX_DC_CFG,
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EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_AZ_RX_DC_CFG,
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EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_AZ_RX_DC_PF_WM,
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EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_BZ_DP_CTRL,
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EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
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{ FR_BZ_RX_RSS_TKEY,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG1,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG2,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
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{ FR_CZ_RX_RSS_IPV6_REG3,
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EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
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};
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2012-07-04 02:58:33 +00:00
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static int siena_test_chip(struct efx_nic *efx, struct efx_self_tests *tests)
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2009-11-29 15:15:25 +00:00
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{
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2012-12-01 01:55:27 +00:00
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enum reset_type reset_method = RESET_TYPE_ALL;
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2012-07-04 02:58:33 +00:00
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int rc, rc2;
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efx_reset_down(efx, reset_method);
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/* Reset the chip immediately so that it is completely
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* quiescent regardless of what any VF driver does.
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*/
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2012-09-18 01:33:52 +00:00
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rc = efx_mcdi_reset(efx, reset_method);
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2012-07-04 02:58:33 +00:00
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if (rc)
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goto out;
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tests->registers =
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efx_nic_test_registers(efx, siena_register_tests,
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ARRAY_SIZE(siena_register_tests))
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? -1 : 1;
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2012-09-18 01:33:52 +00:00
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rc = efx_mcdi_reset(efx, reset_method);
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2012-07-04 02:58:33 +00:00
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out:
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rc2 = efx_reset_up(efx, reset_method, rc == 0);
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return rc ? rc : rc2;
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2009-11-29 15:15:25 +00:00
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}
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/**************************************************************************
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*
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* Device reset
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*
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**************************************************************************
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*/
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2011-06-24 19:50:07 +00:00
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static int siena_map_reset_flags(u32 *flags)
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{
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enum {
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SIENA_RESET_PORT = (ETH_RESET_DMA | ETH_RESET_FILTER |
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ETH_RESET_OFFLOAD | ETH_RESET_MAC |
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ETH_RESET_PHY),
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SIENA_RESET_MC = (SIENA_RESET_PORT |
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ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT),
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};
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if ((*flags & SIENA_RESET_MC) == SIENA_RESET_MC) {
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*flags &= ~SIENA_RESET_MC;
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return RESET_TYPE_WORLD;
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}
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if ((*flags & SIENA_RESET_PORT) == SIENA_RESET_PORT) {
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*flags &= ~SIENA_RESET_PORT;
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return RESET_TYPE_ALL;
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}
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/* no invisible reset implemented */
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return -EINVAL;
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}
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2013-01-14 17:20:22 +00:00
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#ifdef CONFIG_EEH
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/* When a PCI device is isolated from the bus, a subsequent MMIO read is
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* required for the kernel EEH mechanisms to notice. As the Solarflare driver
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* was written to minimise MMIO read (for latency) then a periodic call to check
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* the EEH status of the device is required so that device recovery can happen
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* in a timely fashion.
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*/
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static void siena_monitor(struct efx_nic *efx)
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{
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struct eeh_dev *eehdev =
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of_node_to_eeh_dev(pci_device_to_OF_node(efx->pci_dev));
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eeh_dev_check_failure(eehdev);
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}
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#endif
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|
2009-11-29 15:15:25 +00:00
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static int siena_probe_nvconfig(struct efx_nic *efx)
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{
|
2011-12-08 19:51:47 +00:00
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u32 caps = 0;
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int rc;
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rc = efx_mcdi_get_board_cfg(efx, efx->net_dev->perm_addr, NULL, &caps);
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efx->timer_quantum_ns =
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(caps & (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN)) ?
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3072 : 6144; /* 768 cycles */
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return rc;
|
2009-11-29 15:15:25 +00:00
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}
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|
2012-02-15 01:58:49 +00:00
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static void siena_dimension_resources(struct efx_nic *efx)
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|
|
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{
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|
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/* Each port has a small block of internal SRAM dedicated to
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* the buffer table and descriptor caches. In theory we can
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* map both blocks to one port, but we don't.
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*/
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efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
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}
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|
2009-11-29 15:15:25 +00:00
|
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static int siena_probe_nic(struct efx_nic *efx)
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|
|
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{
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|
|
|
struct siena_nic_data *nic_data;
|
2011-12-19 13:56:45 +00:00
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bool already_attached = false;
|
2010-06-01 11:32:43 +00:00
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efx_oword_t reg;
|
2009-11-29 15:15:25 +00:00
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int rc;
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|
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/* Allocate storage for hardware specific data */
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nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
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if (!nic_data)
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|
|
return -ENOMEM;
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|
|
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efx->nic_data = nic_data;
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|
|
|
|
|
if (efx_nic_fpga_ver(efx) != 0) {
|
2010-06-23 11:30:07 +00:00
|
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|
netif_err(efx, probe, efx->net_dev,
|
|
|
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"Siena FPGA not supported\n");
|
2009-11-29 15:15:25 +00:00
|
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|
rc = -ENODEV;
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goto fail1;
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|
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}
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|
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|
2010-06-01 11:32:43 +00:00
|
|
|
efx_reado(efx, ®, FR_AZ_CS_DEBUG);
|
2013-06-10 17:03:17 +00:00
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|
|
efx->port_num = EFX_OWORD_FIELD(reg, FRF_CZ_CS_PORT_NUM) - 1;
|
2010-06-01 11:32:43 +00:00
|
|
|
|
2012-09-18 01:33:55 +00:00
|
|
|
rc = efx_mcdi_init(efx);
|
2009-11-29 15:15:25 +00:00
|
|
|
if (rc)
|
2011-09-01 12:09:29 +00:00
|
|
|
goto fail1;
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
/* Let the BMC know that the driver is now in charge of link and
|
|
|
|
* filter settings. We must do this before we reset the NIC */
|
|
|
|
rc = efx_mcdi_drv_attach(efx, true, &already_attached);
|
|
|
|
if (rc) {
|
2010-06-23 11:30:07 +00:00
|
|
|
netif_err(efx, probe, efx->net_dev,
|
|
|
|
"Unable to register driver with MCPU\n");
|
2009-11-29 15:15:25 +00:00
|
|
|
goto fail2;
|
|
|
|
}
|
|
|
|
if (already_attached)
|
|
|
|
/* Not a fatal error */
|
2010-06-23 11:30:07 +00:00
|
|
|
netif_err(efx, probe, efx->net_dev,
|
|
|
|
"Host already registered with MCPU\n");
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
/* Now we can reset the NIC */
|
2012-09-18 01:33:52 +00:00
|
|
|
rc = efx_mcdi_reset(efx, RESET_TYPE_ALL);
|
2009-11-29 15:15:25 +00:00
|
|
|
if (rc) {
|
2010-06-23 11:30:07 +00:00
|
|
|
netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
|
2009-11-29 15:15:25 +00:00
|
|
|
goto fail3;
|
|
|
|
}
|
|
|
|
|
|
|
|
siena_init_wol(efx);
|
|
|
|
|
|
|
|
/* Allocate memory for INT_KER */
|
2012-09-18 20:59:52 +00:00
|
|
|
rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t),
|
|
|
|
GFP_KERNEL);
|
2009-11-29 15:15:25 +00:00
|
|
|
if (rc)
|
|
|
|
goto fail4;
|
|
|
|
BUG_ON(efx->irq_status.dma_addr & 0x0f);
|
|
|
|
|
2010-06-23 11:30:07 +00:00
|
|
|
netif_dbg(efx, probe, efx->net_dev,
|
|
|
|
"INT_KER at %llx (virt %p phys %llx)\n",
|
|
|
|
(unsigned long long)efx->irq_status.dma_addr,
|
|
|
|
efx->irq_status.addr,
|
|
|
|
(unsigned long long)virt_to_phys(efx->irq_status.addr));
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
/* Read in the non-volatile configuration */
|
|
|
|
rc = siena_probe_nvconfig(efx);
|
|
|
|
if (rc == -EINVAL) {
|
2010-06-23 11:30:07 +00:00
|
|
|
netif_err(efx, probe, efx->net_dev,
|
|
|
|
"NVRAM is invalid therefore using defaults\n");
|
2009-11-29 15:15:25 +00:00
|
|
|
efx->phy_type = PHY_TYPE_NONE;
|
|
|
|
efx->mdio.prtad = MDIO_PRTAD_NONE;
|
|
|
|
} else if (rc) {
|
|
|
|
goto fail5;
|
|
|
|
}
|
|
|
|
|
2012-01-06 20:25:39 +00:00
|
|
|
rc = efx_mcdi_mon_probe(efx);
|
|
|
|
if (rc)
|
|
|
|
goto fail5;
|
|
|
|
|
sfc: Add SR-IOV back-end support for SFC9000 family
On the SFC9000 family, each port has 1024 Virtual Interfaces (VIs),
each with an RX queue, a TX queue, an event queue and a mailbox
register. These may be assigned to up to 127 SR-IOV virtual functions
per port, with up to 64 VIs per VF.
We allocate an extra channel (IRQ and event queue only) to receive
requests from VF drivers.
There is a per-port limit of 4 concurrent RX queue flushes, and queue
flushes may be initiated by the MC in response to a Function Level
Reset (FLR) of a VF. Therefore, when SR-IOV is in use, we submit all
flush requests via the MC.
The RSS indirection table is shared with VFs, so the number of RX
queues used in the PF is limited to the number of VIs per VF.
This is almost entirely the work of Steve Hodgson, formerly
shodgson@solarflare.com.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
2012-02-14 00:48:07 +00:00
|
|
|
efx_sriov_probe(efx);
|
2012-09-03 10:09:36 +00:00
|
|
|
efx_ptp_probe(efx);
|
sfc: Add SR-IOV back-end support for SFC9000 family
On the SFC9000 family, each port has 1024 Virtual Interfaces (VIs),
each with an RX queue, a TX queue, an event queue and a mailbox
register. These may be assigned to up to 127 SR-IOV virtual functions
per port, with up to 64 VIs per VF.
We allocate an extra channel (IRQ and event queue only) to receive
requests from VF drivers.
There is a per-port limit of 4 concurrent RX queue flushes, and queue
flushes may be initiated by the MC in response to a Function Level
Reset (FLR) of a VF. Therefore, when SR-IOV is in use, we submit all
flush requests via the MC.
The RSS indirection table is shared with VFs, so the number of RX
queues used in the PF is limited to the number of VIs per VF.
This is almost entirely the work of Steve Hodgson, formerly
shodgson@solarflare.com.
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
2012-02-14 00:48:07 +00:00
|
|
|
|
2009-11-29 15:15:25 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
fail5:
|
|
|
|
efx_nic_free_buffer(efx, &efx->irq_status);
|
|
|
|
fail4:
|
|
|
|
fail3:
|
|
|
|
efx_mcdi_drv_attach(efx, false, NULL);
|
|
|
|
fail2:
|
2012-09-18 01:33:56 +00:00
|
|
|
efx_mcdi_fini(efx);
|
2009-11-29 15:15:25 +00:00
|
|
|
fail1:
|
|
|
|
kfree(efx->nic_data);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This call performs hardware-specific global initialisation, such as
|
|
|
|
* defining the descriptor cache sizes and number of RSS channels.
|
|
|
|
* It does not set up any buffers, descriptor rings or event queues.
|
|
|
|
*/
|
|
|
|
static int siena_init_nic(struct efx_nic *efx)
|
|
|
|
{
|
|
|
|
efx_oword_t temp;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* Recover from a failed assertion post-reset */
|
|
|
|
rc = efx_mcdi_handle_assertion(efx);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
/* Squash TX of packets of 16 bytes or less */
|
|
|
|
efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
|
|
|
|
efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
|
|
|
|
|
|
|
|
/* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
|
|
|
|
* descriptors (which is bad).
|
|
|
|
*/
|
|
|
|
efx_reado(efx, &temp, FR_AZ_TX_CFG);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
|
|
|
|
efx_writeo(efx, &temp, FR_AZ_TX_CFG);
|
|
|
|
|
|
|
|
efx_reado(efx, &temp, FR_AZ_RX_CFG);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
|
2010-06-25 07:05:56 +00:00
|
|
|
/* Enable hash insertion. This is broken for the 'Falcon' hash
|
|
|
|
* if IPv6 hashing is also enabled, so also select Toeplitz
|
|
|
|
* TCP/IPv4 and IPv4 hashes. */
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_INSRT_HDR, 1);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_HASH_ALG, 1);
|
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_IP_HASH, 1);
|
2013-01-29 23:33:15 +00:00
|
|
|
EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_USR_BUF_SIZE,
|
|
|
|
EFX_RX_USR_BUF_SIZE >> 5);
|
2009-11-29 15:15:25 +00:00
|
|
|
efx_writeo(efx, &temp, FR_AZ_RX_CFG);
|
|
|
|
|
2010-06-25 07:05:56 +00:00
|
|
|
/* Set hash key for IPv4 */
|
|
|
|
memcpy(&temp, efx->rx_hash_key, sizeof(temp));
|
|
|
|
efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
|
|
|
|
|
2010-04-28 09:29:02 +00:00
|
|
|
/* Enable IPv6 RSS */
|
2010-06-25 07:05:43 +00:00
|
|
|
BUILD_BUG_ON(sizeof(efx->rx_hash_key) <
|
2010-04-28 09:29:02 +00:00
|
|
|
2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
|
|
|
|
FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
|
2010-06-25 07:05:43 +00:00
|
|
|
memcpy(&temp, efx->rx_hash_key, sizeof(temp));
|
2010-04-28 09:29:02 +00:00
|
|
|
efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
|
2010-06-25 07:05:43 +00:00
|
|
|
memcpy(&temp, efx->rx_hash_key + sizeof(temp), sizeof(temp));
|
2010-04-28 09:29:02 +00:00
|
|
|
efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
|
|
|
|
EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
|
|
|
|
FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
|
2010-06-25 07:05:43 +00:00
|
|
|
memcpy(&temp, efx->rx_hash_key + 2 * sizeof(temp),
|
2010-04-28 09:29:02 +00:00
|
|
|
FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
|
|
|
|
efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
|
|
|
|
|
2009-11-29 15:15:25 +00:00
|
|
|
/* Enable event logging */
|
|
|
|
rc = efx_mcdi_log_ctrl(efx, true, false, 0);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
/* Set destination of both TX and RX Flush events */
|
|
|
|
EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
|
|
|
|
efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
|
|
|
|
|
|
|
|
EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
|
|
|
|
efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
|
|
|
|
|
|
|
|
efx_nic_init_common(efx);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void siena_remove_nic(struct efx_nic *efx)
|
|
|
|
{
|
2012-01-06 20:25:39 +00:00
|
|
|
efx_mcdi_mon_remove(efx);
|
|
|
|
|
2009-11-29 15:15:25 +00:00
|
|
|
efx_nic_free_buffer(efx, &efx->irq_status);
|
|
|
|
|
2012-09-18 01:33:52 +00:00
|
|
|
efx_mcdi_reset(efx, RESET_TYPE_ALL);
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
/* Relinquish the device back to the BMC */
|
2012-02-24 21:29:40 +00:00
|
|
|
efx_mcdi_drv_attach(efx, false, NULL);
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
/* Tear down the private nic state */
|
2011-09-01 12:09:29 +00:00
|
|
|
kfree(efx->nic_data);
|
2009-11-29 15:15:25 +00:00
|
|
|
efx->nic_data = NULL;
|
2012-09-18 01:33:56 +00:00
|
|
|
|
|
|
|
efx_mcdi_fini(efx);
|
2009-11-29 15:15:25 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int siena_try_update_nic_stats(struct efx_nic *efx)
|
|
|
|
{
|
2011-06-22 11:11:33 +00:00
|
|
|
__le64 *dma_stats;
|
2009-11-29 15:15:25 +00:00
|
|
|
struct efx_mac_stats *mac_stats;
|
2011-06-22 11:11:33 +00:00
|
|
|
__le64 generation_start, generation_end;
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
mac_stats = &efx->mac_stats;
|
2011-06-16 19:08:06 +00:00
|
|
|
dma_stats = efx->stats_buffer.addr;
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
|
2012-09-18 01:33:54 +00:00
|
|
|
if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
|
2009-11-29 15:15:25 +00:00
|
|
|
return 0;
|
|
|
|
rmb();
|
|
|
|
|
|
|
|
#define MAC_STAT(M, D) \
|
2011-06-22 11:11:33 +00:00
|
|
|
mac_stats->M = le64_to_cpu(dma_stats[MC_CMD_MAC_ ## D])
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
MAC_STAT(tx_bytes, TX_BYTES);
|
|
|
|
MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
|
2012-07-04 21:25:07 +00:00
|
|
|
efx_update_diff_stat(&mac_stats->tx_good_bytes,
|
|
|
|
mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
|
2009-11-29 15:15:25 +00:00
|
|
|
MAC_STAT(tx_packets, TX_PKTS);
|
|
|
|
MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
|
|
|
|
MAC_STAT(tx_pause, TX_PAUSE_PKTS);
|
|
|
|
MAC_STAT(tx_control, TX_CONTROL_PKTS);
|
|
|
|
MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
|
|
|
|
MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
|
|
|
|
MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
|
|
|
|
MAC_STAT(tx_lt64, TX_LT64_PKTS);
|
|
|
|
MAC_STAT(tx_64, TX_64_PKTS);
|
|
|
|
MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
|
|
|
|
MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
|
|
|
|
MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
|
|
|
|
MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
|
|
|
|
MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
|
|
|
|
MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
|
|
|
|
MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
|
|
|
|
mac_stats->tx_collision = 0;
|
|
|
|
MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
|
|
|
|
MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
|
|
|
|
MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
|
|
|
|
MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
|
|
|
|
MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
|
|
|
|
mac_stats->tx_collision = (mac_stats->tx_single_collision +
|
|
|
|
mac_stats->tx_multiple_collision +
|
|
|
|
mac_stats->tx_excessive_collision +
|
|
|
|
mac_stats->tx_late_collision);
|
|
|
|
MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
|
|
|
|
MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
|
|
|
|
MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
|
|
|
|
MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
|
|
|
|
MAC_STAT(rx_bytes, RX_BYTES);
|
|
|
|
MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
|
2012-07-04 21:25:07 +00:00
|
|
|
efx_update_diff_stat(&mac_stats->rx_good_bytes,
|
|
|
|
mac_stats->rx_bytes - mac_stats->rx_bad_bytes);
|
2009-11-29 15:15:25 +00:00
|
|
|
MAC_STAT(rx_packets, RX_PKTS);
|
|
|
|
MAC_STAT(rx_good, RX_GOOD_PKTS);
|
2010-09-10 06:41:00 +00:00
|
|
|
MAC_STAT(rx_bad, RX_BAD_FCS_PKTS);
|
2009-11-29 15:15:25 +00:00
|
|
|
MAC_STAT(rx_pause, RX_PAUSE_PKTS);
|
|
|
|
MAC_STAT(rx_control, RX_CONTROL_PKTS);
|
|
|
|
MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
|
|
|
|
MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
|
|
|
|
MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
|
|
|
|
MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
|
|
|
|
MAC_STAT(rx_64, RX_64_PKTS);
|
|
|
|
MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
|
|
|
|
MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
|
|
|
|
MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
|
|
|
|
MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
|
|
|
|
MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
|
|
|
|
MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
|
|
|
|
MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
|
|
|
|
mac_stats->rx_bad_lt64 = 0;
|
|
|
|
mac_stats->rx_bad_64_to_15xx = 0;
|
|
|
|
mac_stats->rx_bad_15xx_to_jumbo = 0;
|
|
|
|
MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
|
|
|
|
MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
|
|
|
|
mac_stats->rx_missed = 0;
|
|
|
|
MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
|
|
|
|
MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
|
|
|
|
MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
|
|
|
|
MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
|
|
|
|
MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
|
|
|
|
mac_stats->rx_good_lt64 = 0;
|
|
|
|
|
2011-06-22 11:11:33 +00:00
|
|
|
efx->n_rx_nodesc_drop_cnt =
|
|
|
|
le64_to_cpu(dma_stats[MC_CMD_MAC_RX_NODESC_DROPS]);
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
#undef MAC_STAT
|
|
|
|
|
|
|
|
rmb();
|
|
|
|
generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
|
|
|
|
if (generation_end != generation_start)
|
|
|
|
return -EAGAIN;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void siena_update_nic_stats(struct efx_nic *efx)
|
|
|
|
{
|
2010-04-28 09:00:35 +00:00
|
|
|
int retry;
|
|
|
|
|
|
|
|
/* If we're unlucky enough to read statistics wduring the DMA, wait
|
|
|
|
* up to 10ms for it to finish (typically takes <500us) */
|
|
|
|
for (retry = 0; retry < 100; ++retry) {
|
|
|
|
if (siena_try_update_nic_stats(efx) == 0)
|
|
|
|
return;
|
|
|
|
udelay(100);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Use the old values instead */
|
2009-11-29 15:15:25 +00:00
|
|
|
}
|
|
|
|
|
2012-10-08 15:56:18 +00:00
|
|
|
static int siena_mac_reconfigure(struct efx_nic *efx)
|
|
|
|
{
|
|
|
|
MCDI_DECLARE_BUF(inbuf, MC_CMD_SET_MCAST_HASH_IN_LEN);
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN !=
|
|
|
|
MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST +
|
|
|
|
sizeof(efx->multicast_hash));
|
|
|
|
|
|
|
|
WARN_ON(!mutex_is_locked(&efx->mac_lock));
|
|
|
|
|
|
|
|
rc = efx_mcdi_set_mac(efx);
|
|
|
|
if (rc != 0)
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
memcpy(MCDI_PTR(inbuf, SET_MCAST_HASH_IN_HASH0),
|
|
|
|
efx->multicast_hash.byte, sizeof(efx->multicast_hash));
|
|
|
|
return efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
|
|
|
|
inbuf, sizeof(inbuf), NULL, 0, NULL);
|
|
|
|
}
|
|
|
|
|
2009-11-29 15:15:25 +00:00
|
|
|
/**************************************************************************
|
|
|
|
*
|
|
|
|
* Wake on LAN
|
|
|
|
*
|
|
|
|
**************************************************************************
|
|
|
|
*/
|
|
|
|
|
|
|
|
static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
|
|
|
|
{
|
|
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
|
|
|
|
|
|
wol->supported = WAKE_MAGIC;
|
|
|
|
if (nic_data->wol_filter_id != -1)
|
|
|
|
wol->wolopts = WAKE_MAGIC;
|
|
|
|
else
|
|
|
|
wol->wolopts = 0;
|
|
|
|
memset(&wol->sopass, 0, sizeof(wol->sopass));
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int siena_set_wol(struct efx_nic *efx, u32 type)
|
|
|
|
{
|
|
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
if (type & ~WAKE_MAGIC)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
if (type & WAKE_MAGIC) {
|
|
|
|
if (nic_data->wol_filter_id != -1)
|
|
|
|
efx_mcdi_wol_filter_remove(efx,
|
|
|
|
nic_data->wol_filter_id);
|
2010-12-02 13:48:20 +00:00
|
|
|
rc = efx_mcdi_wol_filter_set_magic(efx, efx->net_dev->dev_addr,
|
2009-11-29 15:15:25 +00:00
|
|
|
&nic_data->wol_filter_id);
|
|
|
|
if (rc)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
pci_wake_from_d3(efx->pci_dev, true);
|
|
|
|
} else {
|
|
|
|
rc = efx_mcdi_wol_filter_reset(efx);
|
|
|
|
nic_data->wol_filter_id = -1;
|
|
|
|
pci_wake_from_d3(efx->pci_dev, false);
|
|
|
|
if (rc)
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
fail:
|
2010-06-23 11:30:07 +00:00
|
|
|
netif_err(efx, hw, efx->net_dev, "%s failed: type=%d rc=%d\n",
|
|
|
|
__func__, type, rc);
|
2009-11-29 15:15:25 +00:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static void siena_init_wol(struct efx_nic *efx)
|
|
|
|
{
|
|
|
|
struct siena_nic_data *nic_data = efx->nic_data;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
|
|
|
|
|
|
|
|
if (rc != 0) {
|
|
|
|
/* If it failed, attempt to get into a synchronised
|
|
|
|
* state with MC by resetting any set WoL filters */
|
|
|
|
efx_mcdi_wol_filter_reset(efx);
|
|
|
|
nic_data->wol_filter_id = -1;
|
|
|
|
} else if (nic_data->wol_filter_id != -1) {
|
|
|
|
pci_wake_from_d3(efx->pci_dev, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-09-18 01:33:56 +00:00
|
|
|
/**************************************************************************
|
|
|
|
*
|
|
|
|
* MCDI
|
|
|
|
*
|
|
|
|
**************************************************************************
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define MCDI_PDU(efx) \
|
|
|
|
(efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
|
|
|
|
#define MCDI_DOORBELL(efx) \
|
|
|
|
(efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
|
|
|
|
#define MCDI_STATUS(efx) \
|
|
|
|
(efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
|
|
|
|
|
|
|
|
static void siena_mcdi_request(struct efx_nic *efx,
|
|
|
|
const efx_dword_t *hdr, size_t hdr_len,
|
|
|
|
const efx_dword_t *sdu, size_t sdu_len)
|
|
|
|
{
|
|
|
|
unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
|
|
|
|
unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
|
|
|
|
unsigned int i;
|
|
|
|
unsigned int inlen_dw = DIV_ROUND_UP(sdu_len, 4);
|
|
|
|
|
|
|
|
EFX_BUG_ON_PARANOID(hdr_len != 4);
|
|
|
|
|
|
|
|
efx_writed(efx, hdr, pdu);
|
|
|
|
|
|
|
|
for (i = 0; i < inlen_dw; i++)
|
|
|
|
efx_writed(efx, &sdu[i], pdu + hdr_len + 4 * i);
|
|
|
|
|
|
|
|
/* Ensure the request is written out before the doorbell */
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
/* ring the doorbell with a distinctive value */
|
|
|
|
_efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool siena_mcdi_poll_response(struct efx_nic *efx)
|
|
|
|
{
|
|
|
|
unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
|
|
|
|
efx_dword_t hdr;
|
|
|
|
|
|
|
|
efx_readd(efx, &hdr, pdu);
|
|
|
|
|
|
|
|
/* All 1's indicates that shared memory is in reset (and is
|
|
|
|
* not a valid hdr). Wait for it to come out reset before
|
|
|
|
* completing the command
|
|
|
|
*/
|
|
|
|
return EFX_DWORD_FIELD(hdr, EFX_DWORD_0) != 0xffffffff &&
|
|
|
|
EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void siena_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf,
|
|
|
|
size_t offset, size_t outlen)
|
|
|
|
{
|
|
|
|
unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
|
|
|
|
unsigned int outlen_dw = DIV_ROUND_UP(outlen, 4);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < outlen_dw; i++)
|
|
|
|
efx_readd(efx, &outbuf[i], pdu + offset + 4 * i);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int siena_mcdi_poll_reboot(struct efx_nic *efx)
|
|
|
|
{
|
|
|
|
unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
|
|
|
|
efx_dword_t reg;
|
|
|
|
u32 value;
|
|
|
|
|
|
|
|
efx_readd(efx, ®, addr);
|
|
|
|
value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
|
|
|
|
|
|
|
|
if (value == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
EFX_ZERO_DWORD(reg);
|
|
|
|
efx_writed(efx, ®, addr);
|
|
|
|
|
|
|
|
if (value == MC_STATUS_DWORD_ASSERT)
|
|
|
|
return -EINTR;
|
|
|
|
else
|
|
|
|
return -EIO;
|
|
|
|
}
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
/**************************************************************************
|
|
|
|
*
|
|
|
|
* Revision-dependent attributes used by efx.c and nic.c
|
|
|
|
*
|
|
|
|
**************************************************************************
|
|
|
|
*/
|
|
|
|
|
2011-04-14 05:50:12 +00:00
|
|
|
const struct efx_nic_type siena_a0_nic_type = {
|
2009-11-29 15:15:25 +00:00
|
|
|
.probe = siena_probe_nic,
|
|
|
|
.remove = siena_remove_nic,
|
|
|
|
.init = siena_init_nic,
|
2012-02-15 01:58:49 +00:00
|
|
|
.dimension_resources = siena_dimension_resources,
|
2009-11-29 15:15:25 +00:00
|
|
|
.fini = efx_port_dummy_op_void,
|
2013-01-14 17:20:22 +00:00
|
|
|
#ifdef CONFIG_EEH
|
|
|
|
.monitor = siena_monitor,
|
|
|
|
#else
|
2009-11-29 15:15:25 +00:00
|
|
|
.monitor = NULL,
|
2013-01-14 17:20:22 +00:00
|
|
|
#endif
|
2012-09-18 01:33:52 +00:00
|
|
|
.map_reset_reason = efx_mcdi_map_reset_reason,
|
2011-06-24 19:50:07 +00:00
|
|
|
.map_reset_flags = siena_map_reset_flags,
|
2012-09-18 01:33:52 +00:00
|
|
|
.reset = efx_mcdi_reset,
|
2012-09-18 01:33:54 +00:00
|
|
|
.probe_port = efx_mcdi_port_probe,
|
|
|
|
.remove_port = efx_mcdi_port_remove,
|
2013-05-27 15:52:54 +00:00
|
|
|
.fini_dmaq = efx_farch_fini_dmaq,
|
2012-09-06 15:52:31 +00:00
|
|
|
.prepare_flush = siena_prepare_flush,
|
|
|
|
.finish_flush = siena_finish_flush,
|
2009-11-29 15:15:25 +00:00
|
|
|
.update_stats = siena_update_nic_stats,
|
2012-09-18 01:33:54 +00:00
|
|
|
.start_stats = efx_mcdi_mac_start_stats,
|
|
|
|
.stop_stats = efx_mcdi_mac_stop_stats,
|
2009-11-29 15:15:25 +00:00
|
|
|
.set_id_led = efx_mcdi_set_id_led,
|
|
|
|
.push_irq_moderation = siena_push_irq_moderation,
|
2012-10-08 15:56:18 +00:00
|
|
|
.reconfigure_mac = siena_mac_reconfigure,
|
2011-09-02 23:15:00 +00:00
|
|
|
.check_mac_fault = efx_mcdi_mac_check_fault,
|
2012-09-18 01:33:54 +00:00
|
|
|
.reconfigure_port = efx_mcdi_port_reconfigure,
|
2009-11-29 15:15:25 +00:00
|
|
|
.get_wol = siena_get_wol,
|
|
|
|
.set_wol = siena_set_wol,
|
|
|
|
.resume_wol = siena_init_wol,
|
2012-07-04 02:58:33 +00:00
|
|
|
.test_chip = siena_test_chip,
|
2010-02-03 09:31:01 +00:00
|
|
|
.test_nvram = efx_mcdi_nvram_test_all,
|
2012-09-18 01:33:56 +00:00
|
|
|
.mcdi_request = siena_mcdi_request,
|
|
|
|
.mcdi_poll_response = siena_mcdi_poll_response,
|
|
|
|
.mcdi_read_response = siena_mcdi_read_response,
|
|
|
|
.mcdi_poll_reboot = siena_mcdi_poll_reboot,
|
2009-11-29 15:15:25 +00:00
|
|
|
|
|
|
|
.revision = EFX_REV_SIENA_A0,
|
2011-09-01 12:09:29 +00:00
|
|
|
.mem_map_size = (FR_CZ_MC_TREG_SMEM +
|
|
|
|
FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
|
2009-11-29 15:15:25 +00:00
|
|
|
.txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
|
|
|
|
.rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
|
|
|
|
.buf_tbl_base = FR_BZ_BUF_FULL_TBL,
|
|
|
|
.evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
|
|
|
|
.evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
|
|
|
|
.max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
|
2010-06-23 11:31:28 +00:00
|
|
|
.rx_buffer_hash_size = 0x10,
|
2009-11-29 15:15:25 +00:00
|
|
|
.rx_buffer_padding = 0,
|
2013-01-29 23:33:15 +00:00
|
|
|
.can_rx_scatter = true,
|
2009-11-29 15:15:25 +00:00
|
|
|
.max_interrupt_mode = EFX_INT_MODE_MSIX,
|
|
|
|
.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
|
|
|
|
* interrupt handler only supports 32
|
|
|
|
* channels */
|
2011-12-08 19:51:47 +00:00
|
|
|
.timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
|
2010-06-23 11:31:28 +00:00
|
|
|
.offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
|
2010-09-20 08:43:42 +00:00
|
|
|
NETIF_F_RXHASH | NETIF_F_NTUPLE),
|
2009-11-29 15:15:25 +00:00
|
|
|
};
|