2019-05-27 06:55:01 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2016-09-30 02:33:01 +00:00
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/*
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* Ptrace test for VMX/VSX registers in the TM Suspend context
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*
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* Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
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*/
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#include "ptrace.h"
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#include "tm.h"
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#include "ptrace-vsx.h"
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int shm_id;
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int *cptr, *pptr;
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unsigned long fp_load[VEC_MAX];
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unsigned long fp_load_new[VEC_MAX];
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unsigned long fp_store[VEC_MAX];
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unsigned long fp_load_ckpt[VEC_MAX];
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unsigned long fp_load_ckpt_new[VEC_MAX];
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__attribute__((used)) void load_vsx(void)
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{
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loadvsx(fp_load, 0);
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}
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__attribute__((used)) void load_vsx_new(void)
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{
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loadvsx(fp_load_new, 0);
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}
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__attribute__((used)) void load_vsx_ckpt(void)
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{
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loadvsx(fp_load_ckpt, 0);
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}
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__attribute__((used)) void wait_parent(void)
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{
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cptr[2] = 1;
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while (!cptr[1])
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asm volatile("" : : : "memory");
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}
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void tm_spd_vsx(void)
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{
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unsigned long result, texasr;
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int ret;
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cptr = (int *)shmat(shm_id, NULL, 0);
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trans:
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cptr[2] = 0;
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asm __volatile__(
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"bl load_vsx_ckpt;"
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"1: ;"
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"tbegin.;"
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"beq 2f;"
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"bl load_vsx_new;"
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"tsuspend.;"
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"bl load_vsx;"
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"bl wait_parent;"
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"tresume.;"
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"tend.;"
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"li 0, 0;"
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"ori %[res], 0, 0;"
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"b 3f;"
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"2: ;"
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"li 0, 1;"
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"ori %[res], 0, 0;"
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"mfspr %[texasr], %[sprn_texasr];"
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"3: ;"
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: [res] "=r" (result), [texasr] "=r" (texasr)
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selftests/powerpc: Allocate base registers
Some ptrace selftests are passing input operands using a constraint that
can allocate any register for the operand, and using these registers on
load/store operations.
If the register allocated by the compiler happens to be zero (r0), it might
cause an invalid memory address access, since load and store operations
consider the content of 0x0 address if the base register is r0, instead of
the content of the r0 register. For example:
r1 := 0xdeadbeef
r0 := 0xdeadbeef
ld r2, 0(1) /* will load into r2 the content of r1 address */
ld r2, 0(0) /* will load into r2 the content of 0x0 */
In order to avoid this possible problem, the inline assembly constraint
should be aware that these registers will be used as a base register, thus,
r0 should not be allocated.
Other than that, this patch removes inline assembly operands that are not
used by the tests.
Signed-off-by: Breno Leitao <leitao@debian.org>
Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
2018-10-31 14:38:20 +00:00
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: [sprn_texasr] "i" (SPRN_TEXASR)
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selftests/powerpc: Fixup clobbers for TM tests
Some of our TM (Transactional Memory) tests, list "r1" (the stack
pointer) as a clobbered register.
GCC >= 9 doesn't accept this, and the build breaks:
ptrace-tm-spd-tar.c: In function 'tm_spd_tar':
ptrace-tm-spd-tar.c:31:2: error: listing the stack pointer register 'r1' in a clobber list is deprecated [-Werror=deprecated]
31 | asm __volatile__(
| ^~~
ptrace-tm-spd-tar.c:31:2: note: the value of the stack pointer after an 'asm' statement must be the same as it was before the statement
We do have some fairly large inline asm blocks in these tests, and
some of them do change the value of r1. However they should all return
to C with the value in r1 restored, so I think it's legitimate to say
r1 is not clobbered.
As Segher points out, the r1 clobbers may have been added because of
the use of `or 1,1,1`, however that doesn't actually clobber r1.
Segher also points out that some of these tests do clobber LR, because
they call functions, and that is not listed in the clobbers, so add
that where appropriate.
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20191029095324.14669-1-mpe@ellerman.id.au
2019-10-14 02:30:43 +00:00
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: "memory", "r0", "r3", "r4",
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"r7", "r8", "r9", "r10", "r11", "lr"
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2016-09-30 02:33:01 +00:00
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);
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if (result) {
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if (!cptr[0])
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goto trans;
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shmdt((void *)cptr);
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storevsx(fp_store, 0);
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ret = compare_vsx_vmx(fp_store, fp_load_ckpt_new);
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if (ret)
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exit(1);
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exit(0);
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}
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shmdt((void *)cptr);
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exit(1);
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}
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int trace_tm_spd_vsx(pid_t child)
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{
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unsigned long vsx[VSX_MAX];
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unsigned long vmx[VMX_MAX + 2][2];
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FAIL_IF(start_trace(child));
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FAIL_IF(show_vsx(child, vsx));
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FAIL_IF(validate_vsx(vsx, fp_load));
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FAIL_IF(show_vmx(child, vmx));
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FAIL_IF(validate_vmx(vmx, fp_load));
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FAIL_IF(show_vsx_ckpt(child, vsx));
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FAIL_IF(validate_vsx(vsx, fp_load_ckpt));
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FAIL_IF(show_vmx_ckpt(child, vmx));
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FAIL_IF(validate_vmx(vmx, fp_load_ckpt));
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memset(vsx, 0, sizeof(vsx));
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memset(vmx, 0, sizeof(vmx));
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load_vsx_vmx(fp_load_ckpt_new, vsx, vmx);
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FAIL_IF(write_vsx_ckpt(child, vsx));
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FAIL_IF(write_vmx_ckpt(child, vmx));
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pptr[0] = 1;
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pptr[1] = 1;
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FAIL_IF(stop_trace(child));
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return TEST_PASS;
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}
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int ptrace_tm_spd_vsx(void)
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{
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pid_t pid;
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int ret, status, i;
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2023-07-25 00:58:39 +00:00
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SKIP_IF_MSG(!have_htm(), "Don't have transactional memory");
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SKIP_IF_MSG(htm_is_synthetic(), "Transactional memory is synthetic");
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2016-09-30 02:33:01 +00:00
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shm_id = shmget(IPC_PRIVATE, sizeof(int) * 3, 0777|IPC_CREAT);
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for (i = 0; i < 128; i++) {
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fp_load[i] = 1 + rand();
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fp_load_new[i] = 1 + 2 * rand();
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fp_load_ckpt[i] = 1 + 3 * rand();
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fp_load_ckpt_new[i] = 1 + 4 * rand();
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}
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pid = fork();
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if (pid < 0) {
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perror("fork() failed");
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return TEST_FAIL;
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}
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if (pid == 0)
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tm_spd_vsx();
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if (pid) {
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pptr = (int *)shmat(shm_id, NULL, 0);
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while (!pptr[2])
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asm volatile("" : : : "memory");
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ret = trace_tm_spd_vsx(pid);
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if (ret) {
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kill(pid, SIGKILL);
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shmdt((void *)pptr);
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shmctl(shm_id, IPC_RMID, NULL);
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return TEST_FAIL;
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}
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shmdt((void *)pptr);
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ret = wait(&status);
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shmctl(shm_id, IPC_RMID, NULL);
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if (ret != pid) {
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printf("Child's exit status not captured\n");
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return TEST_FAIL;
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}
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return (WIFEXITED(status) && WEXITSTATUS(status)) ? TEST_FAIL :
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TEST_PASS;
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}
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return TEST_PASS;
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}
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int main(int argc, char *argv[])
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{
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return test_harness(ptrace_tm_spd_vsx, "ptrace_tm_spd_vsx");
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}
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