2019-06-04 08:11:32 +00:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
2008-07-22 19:27:11 +00:00
|
|
|
/*
|
2007-10-10 15:16:19 +00:00
|
|
|
* Kernel-based Virtual Machine driver for Linux
|
|
|
|
*
|
|
|
|
* This header defines architecture specific interfaces, x86 version
|
|
|
|
*/
|
|
|
|
|
2008-10-23 05:26:29 +00:00
|
|
|
#ifndef _ASM_X86_KVM_HOST_H
|
|
|
|
#define _ASM_X86_KVM_HOST_H
|
2007-10-10 15:16:19 +00:00
|
|
|
|
2007-10-20 07:34:38 +00:00
|
|
|
#include <linux/types.h>
|
|
|
|
#include <linux/mm.h>
|
2008-07-25 14:24:52 +00:00
|
|
|
#include <linux/mmu_notifier.h>
|
2009-06-17 12:22:14 +00:00
|
|
|
#include <linux/tracepoint.h>
|
2010-06-30 04:25:15 +00:00
|
|
|
#include <linux/cpumask.h>
|
2011-11-10 12:57:22 +00:00
|
|
|
#include <linux/irq_work.h>
|
2018-07-29 10:15:33 +00:00
|
|
|
#include <linux/irq.h>
|
2007-10-20 07:34:38 +00:00
|
|
|
|
|
|
|
#include <linux/kvm.h>
|
|
|
|
#include <linux/kvm_para.h>
|
2007-12-16 09:02:48 +00:00
|
|
|
#include <linux/kvm_types.h>
|
2011-11-10 12:57:22 +00:00
|
|
|
#include <linux/perf_event.h>
|
2012-11-28 01:29:01 +00:00
|
|
|
#include <linux/pvclock_gtod.h>
|
|
|
|
#include <linux/clocksource.h>
|
2015-09-18 14:29:40 +00:00
|
|
|
#include <linux/irqbypass.h>
|
2015-11-10 12:36:34 +00:00
|
|
|
#include <linux/hyperv.h>
|
2007-10-20 07:34:38 +00:00
|
|
|
|
2016-06-15 22:23:45 +00:00
|
|
|
#include <asm/apic.h>
|
2008-06-03 14:17:31 +00:00
|
|
|
#include <asm/pvclock-abi.h>
|
2007-12-03 21:30:25 +00:00
|
|
|
#include <asm/desc.h>
|
2008-10-09 08:01:54 +00:00
|
|
|
#include <asm/mtrr.h>
|
2008-11-25 19:17:02 +00:00
|
|
|
#include <asm/msr-index.h>
|
2012-04-20 20:41:59 +00:00
|
|
|
#include <asm/asm.h>
|
KVM: page track: add the framework of guest page tracking
The array, gfn_track[mode][gfn], is introduced in memory slot for every
guest page, this is the tracking count for the gust page on different
modes. If the page is tracked then the count is increased, the page is
not tracked after the count reaches zero
We use 'unsigned short' as the tracking count which should be enough as
shadow page table only can use 2^14 (2^3 for level, 2^1 for cr4_pae, 2^2
for quadrant, 2^3 for access, 2^1 for nxe, 2^1 for cr0_wp, 2^1 for
smep_andnot_wp, 2^1 for smap_andnot_wp, and 2^1 for smm) at most, there
is enough room for other trackers
Two callbacks, kvm_page_track_create_memslot() and
kvm_page_track_free_memslot() are implemented in this patch, they are
internally used to initialize and reclaim the memory of the array
Currently, only write track mode is supported
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-24 09:51:09 +00:00
|
|
|
#include <asm/kvm_page_track.h>
|
2019-01-25 15:41:09 +00:00
|
|
|
#include <asm/kvm_vcpu_regs.h>
|
2018-03-20 14:02:05 +00:00
|
|
|
#include <asm/hyperv-tlfs.h>
|
2007-12-03 21:30:25 +00:00
|
|
|
|
2019-08-03 06:14:25 +00:00
|
|
|
#define __KVM_HAVE_ARCH_VCPU_DEBUGFS
|
|
|
|
|
2016-07-12 20:09:29 +00:00
|
|
|
#define KVM_MAX_VCPUS 288
|
2016-07-12 20:09:17 +00:00
|
|
|
#define KVM_SOFT_MAX_VCPUS 240
|
2016-07-12 20:09:30 +00:00
|
|
|
#define KVM_MAX_VCPU_ID 1023
|
2012-12-10 17:33:15 +00:00
|
|
|
/* memory slots that are not exposed to userspace */
|
|
|
|
#define KVM_PRIVATE_MEM_SLOTS 3
|
2011-11-24 09:37:48 +00:00
|
|
|
|
2017-04-18 10:41:18 +00:00
|
|
|
#define KVM_HALT_POLL_NS_DEFAULT 200000
|
2008-03-21 10:38:23 +00:00
|
|
|
|
2013-04-15 08:42:33 +00:00
|
|
|
#define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
|
|
|
|
|
2020-02-27 01:32:27 +00:00
|
|
|
#define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
|
|
|
|
KVM_DIRTY_LOG_INITIALLY_SET)
|
|
|
|
|
2020-11-06 09:03:14 +00:00
|
|
|
#define KVM_BUS_LOCK_DETECTION_VALID_MODE (KVM_BUS_LOCK_DETECTION_OFF | \
|
|
|
|
KVM_BUS_LOCK_DETECTION_EXIT)
|
|
|
|
|
2016-01-07 14:05:10 +00:00
|
|
|
/* x86-specific vcpu->requests bit members */
|
2017-06-04 12:43:51 +00:00
|
|
|
#define KVM_REQ_MIGRATE_TIMER KVM_ARCH_REQ(0)
|
|
|
|
#define KVM_REQ_REPORT_TPR_ACCESS KVM_ARCH_REQ(1)
|
|
|
|
#define KVM_REQ_TRIPLE_FAULT KVM_ARCH_REQ(2)
|
|
|
|
#define KVM_REQ_MMU_SYNC KVM_ARCH_REQ(3)
|
|
|
|
#define KVM_REQ_CLOCK_UPDATE KVM_ARCH_REQ(4)
|
2020-03-05 08:52:50 +00:00
|
|
|
#define KVM_REQ_LOAD_MMU_PGD KVM_ARCH_REQ(5)
|
2017-06-04 12:43:51 +00:00
|
|
|
#define KVM_REQ_EVENT KVM_ARCH_REQ(6)
|
|
|
|
#define KVM_REQ_APF_HALT KVM_ARCH_REQ(7)
|
|
|
|
#define KVM_REQ_STEAL_UPDATE KVM_ARCH_REQ(8)
|
|
|
|
#define KVM_REQ_NMI KVM_ARCH_REQ(9)
|
|
|
|
#define KVM_REQ_PMU KVM_ARCH_REQ(10)
|
|
|
|
#define KVM_REQ_PMI KVM_ARCH_REQ(11)
|
|
|
|
#define KVM_REQ_SMI KVM_ARCH_REQ(12)
|
|
|
|
#define KVM_REQ_MASTERCLOCK_UPDATE KVM_ARCH_REQ(13)
|
|
|
|
#define KVM_REQ_MCLOCK_INPROGRESS \
|
|
|
|
KVM_ARCH_REQ_FLAGS(14, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
|
|
|
|
#define KVM_REQ_SCAN_IOAPIC \
|
|
|
|
KVM_ARCH_REQ_FLAGS(15, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
|
|
|
|
#define KVM_REQ_GLOBAL_CLOCK_UPDATE KVM_ARCH_REQ(16)
|
|
|
|
#define KVM_REQ_APIC_PAGE_RELOAD \
|
|
|
|
KVM_ARCH_REQ_FLAGS(17, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
|
|
|
|
#define KVM_REQ_HV_CRASH KVM_ARCH_REQ(18)
|
|
|
|
#define KVM_REQ_IOAPIC_EOI_EXIT KVM_ARCH_REQ(19)
|
|
|
|
#define KVM_REQ_HV_RESET KVM_ARCH_REQ(20)
|
|
|
|
#define KVM_REQ_HV_EXIT KVM_ARCH_REQ(21)
|
|
|
|
#define KVM_REQ_HV_STIMER KVM_ARCH_REQ(22)
|
KVM: nVMX: Do not load EOI-exitmap while running L2
When L1 IOAPIC redirection-table is written, a request of
KVM_REQ_SCAN_IOAPIC is set on all vCPUs. This is done such that
all vCPUs will now recalc their IOAPIC handled vectors and load
it to their EOI-exitmap.
However, it could be that one of the vCPUs is currently running
L2. In this case, load_eoi_exitmap() will be called which would
write to vmcs02->eoi_exit_bitmap, which is wrong because
vmcs02->eoi_exit_bitmap should always be equal to
vmcs12->eoi_exit_bitmap. Furthermore, at this point
KVM_REQ_SCAN_IOAPIC was already consumed and therefore we will
never update vmcs01->eoi_exit_bitmap. This could lead to remote_irr
of some IOAPIC level-triggered entry to remain set forever.
Fix this issue by delaying the load of EOI-exitmap to when vCPU
is running L1.
One may wonder why not just delay entire KVM_REQ_SCAN_IOAPIC
processing to when vCPU is running L1. This is done in order to handle
correctly the case where LAPIC & IO-APIC of L1 is pass-throughed into
L2. In this case, vmcs12->virtual_interrupt_delivery should be 0. In
current nVMX implementation, that results in
vmcs02->virtual_interrupt_delivery to also be 0. Thus,
vmcs02->eoi_exit_bitmap is not used. Therefore, every L2 EOI cause
a #VMExit into L0 (either on MSR_WRITE to x2APIC MSR or
APIC_ACCESS/APIC_WRITE/EPT_MISCONFIG to APIC MMIO page).
In order for such L2 EOI to be broadcasted, if needed, from LAPIC
to IO-APIC, vcpu->arch.ioapic_handled_vectors must be updated
while L2 is running. Therefore, patch makes sure to delay only the
loading of EOI-exitmap but not the update of
vcpu->arch.ioapic_handled_vectors.
Reviewed-by: Arbel Moshe <arbel.moshe@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-21 00:50:31 +00:00
|
|
|
#define KVM_REQ_LOAD_EOI_EXITMAP KVM_ARCH_REQ(23)
|
2020-09-22 10:53:57 +00:00
|
|
|
#define KVM_REQ_GET_NESTED_STATE_PAGES KVM_ARCH_REQ(24)
|
2019-11-14 20:15:06 +00:00
|
|
|
#define KVM_REQ_APICV_UPDATE \
|
|
|
|
KVM_ARCH_REQ_FLAGS(25, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
|
2020-03-20 21:28:20 +00:00
|
|
|
#define KVM_REQ_TLB_FLUSH_CURRENT KVM_ARCH_REQ(26)
|
2020-03-25 16:28:24 +00:00
|
|
|
#define KVM_REQ_HV_TLB_FLUSH \
|
2020-03-20 21:28:20 +00:00
|
|
|
KVM_ARCH_REQ_FLAGS(27, KVM_REQUEST_NO_WAKEUP)
|
2020-05-25 14:41:21 +00:00
|
|
|
#define KVM_REQ_APF_READY KVM_ARCH_REQ(28)
|
2020-09-25 14:34:21 +00:00
|
|
|
#define KVM_REQ_MSR_FILTER_CHANGED KVM_ARCH_REQ(29)
|
2021-02-13 00:50:12 +00:00
|
|
|
#define KVM_REQ_UPDATE_CPU_DIRTY_LOGGING \
|
|
|
|
KVM_ARCH_REQ_FLAGS(30, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
|
2016-01-07 14:05:10 +00:00
|
|
|
|
2011-04-04 10:39:28 +00:00
|
|
|
#define CR0_RESERVED_BITS \
|
|
|
|
(~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
|
|
|
|
| X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
|
|
|
|
| X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
|
|
|
|
|
|
|
|
#define CR4_RESERVED_BITS \
|
|
|
|
(~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
|
|
|
|
| X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
|
2012-07-02 01:18:48 +00:00
|
|
|
| X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
|
2013-04-27 23:37:47 +00:00
|
|
|
| X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
|
2017-08-24 12:27:56 +00:00
|
|
|
| X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \
|
2016-07-12 08:36:41 +00:00
|
|
|
| X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP))
|
2011-04-04 10:39:28 +00:00
|
|
|
|
|
|
|
#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
|
|
|
|
|
|
|
|
|
2007-11-19 06:33:37 +00:00
|
|
|
|
|
|
|
#define INVALID_PAGE (~(hpa_t)0)
|
2010-07-03 08:02:42 +00:00
|
|
|
#define VALID_PAGE(x) ((x) != INVALID_PAGE)
|
|
|
|
|
2007-11-19 06:33:37 +00:00
|
|
|
#define UNMAPPED_GVA (~(gpa_t)0)
|
2021-05-03 12:54:43 +00:00
|
|
|
#define INVALID_GPA (~(gpa_t)0)
|
2007-11-19 06:33:37 +00:00
|
|
|
|
2009-06-19 13:16:23 +00:00
|
|
|
/* KVM Hugepage definitions for x86 */
|
2020-04-28 00:54:22 +00:00
|
|
|
#define KVM_MAX_HUGEPAGE_LEVEL PG_LEVEL_1G
|
|
|
|
#define KVM_NR_PAGE_SIZES (KVM_MAX_HUGEPAGE_LEVEL - PG_LEVEL_4K + 1)
|
2010-07-01 14:00:11 +00:00
|
|
|
#define KVM_HPAGE_GFN_SHIFT(x) (((x) - 1) * 9)
|
|
|
|
#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + KVM_HPAGE_GFN_SHIFT(x))
|
2009-06-19 13:16:23 +00:00
|
|
|
#define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
|
|
|
|
#define KVM_HPAGE_MASK(x) (~(KVM_HPAGE_SIZE(x) - 1))
|
|
|
|
#define KVM_PAGES_PER_HPAGE(x) (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
|
2008-02-23 14:44:30 +00:00
|
|
|
|
2013-10-02 21:22:28 +00:00
|
|
|
static inline gfn_t gfn_to_index(gfn_t gfn, gfn_t base_gfn, int level)
|
|
|
|
{
|
2020-04-28 00:54:22 +00:00
|
|
|
/* KVM_HPAGE_GFN_SHIFT(PG_LEVEL_4K) must be 0. */
|
2013-10-02 21:22:28 +00:00
|
|
|
return (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
|
|
|
|
(base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
|
|
|
|
}
|
|
|
|
|
2007-12-14 01:41:22 +00:00
|
|
|
#define KVM_PERMILLE_MMU_PAGES 20
|
2019-04-08 18:07:30 +00:00
|
|
|
#define KVM_MIN_ALLOC_MMU_PAGES 64UL
|
kvm: x86: reduce collisions in mmu_page_hash
When using two-dimensional paging, the mmu_page_hash (which provides
lookups for existing kvm_mmu_page structs), becomes imbalanced; with
too many collisions in buckets 0 and 512. This has been seen to cause
mmu_lock to be held for multiple milliseconds in kvm_mmu_get_page on
VMs with a large amount of RAM mapped with 4K pages.
The current hash function uses the lower 10 bits of gfn to index into
mmu_page_hash. When doing shadow paging, gfn is the address of the
guest page table being shadow. These tables are 4K-aligned, which
makes the low bits of gfn a good hash. However, with two-dimensional
paging, no guest page tables are being shadowed, so gfn is the base
address that is mapped by the table. Thus page tables (level=1) have
a 2MB aligned gfn, page directories (level=2) have a 1GB aligned gfn,
etc. This means hashes will only differ in their 10th bit.
hash_64() provides a better hash. For example, on a VM with ~200G
(99458 direct=1 kvm_mmu_page structs):
hash max_mmu_page_hash_collisions
--------------------------------------------
low 10 bits 49847
hash_64 105
perfect 97
While we're changing the hash, increase the table size by 4x to better
support large VMs (further reduces number of collisions in 200G VM to
29).
Note that hash_64() does not provide a good distribution prior to commit
ef703f49a6c5 ("Eliminate bad hash multipliers from hash_32() and
hash_64()").
Signed-off-by: David Matlack <dmatlack@google.com>
Change-Id: I5aa6b13c834722813c6cca46b8b1ed6f53368ade
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-19 21:58:25 +00:00
|
|
|
#define KVM_MMU_HASH_SHIFT 12
|
2008-01-07 11:20:25 +00:00
|
|
|
#define KVM_NUM_MMU_PAGES (1 << KVM_MMU_HASH_SHIFT)
|
2007-12-14 01:41:22 +00:00
|
|
|
#define KVM_MIN_FREE_MMU_PAGES 5
|
|
|
|
#define KVM_REFILL_PAGES 25
|
2020-10-01 13:05:41 +00:00
|
|
|
#define KVM_MAX_CPUID_ENTRIES 256
|
2008-10-09 08:01:54 +00:00
|
|
|
#define KVM_NR_FIXED_MTRR_REGION 88
|
2014-08-18 14:39:48 +00:00
|
|
|
#define KVM_NR_VAR_MTRR 8
|
2007-12-14 01:41:22 +00:00
|
|
|
|
2010-10-14 09:22:46 +00:00
|
|
|
#define ASYNC_PF_PER_VCPU 64
|
|
|
|
|
2008-06-27 17:58:02 +00:00
|
|
|
enum kvm_reg {
|
2019-01-25 15:41:09 +00:00
|
|
|
VCPU_REGS_RAX = __VCPU_REGS_RAX,
|
|
|
|
VCPU_REGS_RCX = __VCPU_REGS_RCX,
|
|
|
|
VCPU_REGS_RDX = __VCPU_REGS_RDX,
|
|
|
|
VCPU_REGS_RBX = __VCPU_REGS_RBX,
|
|
|
|
VCPU_REGS_RSP = __VCPU_REGS_RSP,
|
|
|
|
VCPU_REGS_RBP = __VCPU_REGS_RBP,
|
|
|
|
VCPU_REGS_RSI = __VCPU_REGS_RSI,
|
|
|
|
VCPU_REGS_RDI = __VCPU_REGS_RDI,
|
2007-11-19 06:56:05 +00:00
|
|
|
#ifdef CONFIG_X86_64
|
2019-01-25 15:41:09 +00:00
|
|
|
VCPU_REGS_R8 = __VCPU_REGS_R8,
|
|
|
|
VCPU_REGS_R9 = __VCPU_REGS_R9,
|
|
|
|
VCPU_REGS_R10 = __VCPU_REGS_R10,
|
|
|
|
VCPU_REGS_R11 = __VCPU_REGS_R11,
|
|
|
|
VCPU_REGS_R12 = __VCPU_REGS_R12,
|
|
|
|
VCPU_REGS_R13 = __VCPU_REGS_R13,
|
|
|
|
VCPU_REGS_R14 = __VCPU_REGS_R14,
|
|
|
|
VCPU_REGS_R15 = __VCPU_REGS_R15,
|
2007-11-19 06:56:05 +00:00
|
|
|
#endif
|
2008-06-27 17:58:02 +00:00
|
|
|
VCPU_REGS_RIP,
|
2019-09-27 21:45:21 +00:00
|
|
|
NR_VCPU_REGS,
|
2007-11-19 06:56:05 +00:00
|
|
|
|
2009-05-31 19:58:47 +00:00
|
|
|
VCPU_EXREG_PDPTR = NR_VCPU_REGS,
|
2020-05-02 04:32:31 +00:00
|
|
|
VCPU_EXREG_CR0,
|
2010-12-05 16:56:11 +00:00
|
|
|
VCPU_EXREG_CR3,
|
2020-05-02 04:32:30 +00:00
|
|
|
VCPU_EXREG_CR4,
|
2011-03-07 10:51:22 +00:00
|
|
|
VCPU_EXREG_RFLAGS,
|
2011-04-27 16:42:18 +00:00
|
|
|
VCPU_EXREG_SEGMENTS,
|
2020-04-15 20:34:53 +00:00
|
|
|
VCPU_EXREG_EXIT_INFO_1,
|
2020-04-15 20:34:54 +00:00
|
|
|
VCPU_EXREG_EXIT_INFO_2,
|
2009-05-31 19:58:47 +00:00
|
|
|
};
|
|
|
|
|
2007-11-19 06:56:05 +00:00
|
|
|
enum {
|
2008-05-27 13:26:01 +00:00
|
|
|
VCPU_SREG_ES,
|
2007-11-19 06:56:05 +00:00
|
|
|
VCPU_SREG_CS,
|
2008-05-27 13:26:01 +00:00
|
|
|
VCPU_SREG_SS,
|
2007-11-19 06:56:05 +00:00
|
|
|
VCPU_SREG_DS,
|
|
|
|
VCPU_SREG_FS,
|
|
|
|
VCPU_SREG_GS,
|
|
|
|
VCPU_SREG_TR,
|
|
|
|
VCPU_SREG_LDTR,
|
|
|
|
};
|
|
|
|
|
2019-11-21 03:17:11 +00:00
|
|
|
enum exit_fastpath_completion {
|
|
|
|
EXIT_FASTPATH_NONE,
|
2020-04-28 06:23:25 +00:00
|
|
|
EXIT_FASTPATH_REENTER_GUEST,
|
|
|
|
EXIT_FASTPATH_EXIT_HANDLED,
|
2019-11-21 03:17:11 +00:00
|
|
|
};
|
2020-04-28 06:23:25 +00:00
|
|
|
typedef enum exit_fastpath_completion fastpath_t;
|
2019-11-21 03:17:11 +00:00
|
|
|
|
2020-02-18 23:29:49 +00:00
|
|
|
struct x86_emulate_ctxt;
|
|
|
|
struct x86_exception;
|
|
|
|
enum x86_intercept;
|
|
|
|
enum x86_intercept_stage;
|
2007-11-19 06:56:05 +00:00
|
|
|
|
2008-12-15 12:52:10 +00:00
|
|
|
#define KVM_NR_DB_REGS 4
|
|
|
|
|
2021-02-02 09:04:32 +00:00
|
|
|
#define DR6_BUS_LOCK (1 << 11)
|
2008-12-15 12:52:10 +00:00
|
|
|
#define DR6_BD (1 << 13)
|
|
|
|
#define DR6_BS (1 << 14)
|
2018-09-21 17:36:17 +00:00
|
|
|
#define DR6_BT (1 << 15)
|
2014-07-15 14:37:46 +00:00
|
|
|
#define DR6_RTM (1 << 16)
|
2021-02-02 09:04:31 +00:00
|
|
|
/*
|
|
|
|
* DR6_ACTIVE_LOW combines fixed-1 and active-low bits.
|
|
|
|
* We can regard all the bits in DR6_FIXED_1 as active_low bits;
|
|
|
|
* they will never be 0 for now, but when they are defined
|
|
|
|
* in the future it will require no code change.
|
|
|
|
*
|
|
|
|
* DR6_ACTIVE_LOW is also used as the init/reset value for DR6.
|
|
|
|
*/
|
|
|
|
#define DR6_ACTIVE_LOW 0xffff0ff0
|
2021-02-02 09:04:32 +00:00
|
|
|
#define DR6_VOLATILE 0x0001e80f
|
2021-02-02 09:04:31 +00:00
|
|
|
#define DR6_FIXED_1 (DR6_ACTIVE_LOW & ~DR6_VOLATILE)
|
2008-12-15 12:52:10 +00:00
|
|
|
|
|
|
|
#define DR7_BP_EN_MASK 0x000000ff
|
|
|
|
#define DR7_GE (1 << 9)
|
|
|
|
#define DR7_GD (1 << 13)
|
|
|
|
#define DR7_FIXED_1 0x00000400
|
2014-07-15 14:37:46 +00:00
|
|
|
#define DR7_VOLATILE 0xffff2bff
|
2008-12-15 12:52:10 +00:00
|
|
|
|
2021-04-01 13:54:45 +00:00
|
|
|
#define KVM_GUESTDBG_VALID_MASK \
|
|
|
|
(KVM_GUESTDBG_ENABLE | \
|
|
|
|
KVM_GUESTDBG_SINGLESTEP | \
|
|
|
|
KVM_GUESTDBG_USE_HW_BP | \
|
|
|
|
KVM_GUESTDBG_USE_SW_BP | \
|
|
|
|
KVM_GUESTDBG_INJECT_BP | \
|
|
|
|
KVM_GUESTDBG_INJECT_DB)
|
|
|
|
|
|
|
|
|
2014-12-25 00:52:16 +00:00
|
|
|
#define PFERR_PRESENT_BIT 0
|
|
|
|
#define PFERR_WRITE_BIT 1
|
|
|
|
#define PFERR_USER_BIT 2
|
|
|
|
#define PFERR_RSVD_BIT 3
|
|
|
|
#define PFERR_FETCH_BIT 4
|
2016-03-22 08:51:20 +00:00
|
|
|
#define PFERR_PK_BIT 5
|
2021-04-12 04:21:34 +00:00
|
|
|
#define PFERR_SGX_BIT 15
|
2016-11-23 17:01:38 +00:00
|
|
|
#define PFERR_GUEST_FINAL_BIT 32
|
|
|
|
#define PFERR_GUEST_PAGE_BIT 33
|
2014-12-25 00:52:16 +00:00
|
|
|
|
|
|
|
#define PFERR_PRESENT_MASK (1U << PFERR_PRESENT_BIT)
|
|
|
|
#define PFERR_WRITE_MASK (1U << PFERR_WRITE_BIT)
|
|
|
|
#define PFERR_USER_MASK (1U << PFERR_USER_BIT)
|
|
|
|
#define PFERR_RSVD_MASK (1U << PFERR_RSVD_BIT)
|
|
|
|
#define PFERR_FETCH_MASK (1U << PFERR_FETCH_BIT)
|
2016-03-22 08:51:20 +00:00
|
|
|
#define PFERR_PK_MASK (1U << PFERR_PK_BIT)
|
2021-04-12 04:21:34 +00:00
|
|
|
#define PFERR_SGX_MASK (1U << PFERR_SGX_BIT)
|
2016-11-23 17:01:38 +00:00
|
|
|
#define PFERR_GUEST_FINAL_MASK (1ULL << PFERR_GUEST_FINAL_BIT)
|
|
|
|
#define PFERR_GUEST_PAGE_MASK (1ULL << PFERR_GUEST_PAGE_BIT)
|
|
|
|
|
|
|
|
#define PFERR_NESTED_GUEST_PAGE (PFERR_GUEST_PAGE_MASK | \
|
|
|
|
PFERR_WRITE_MASK | \
|
|
|
|
PFERR_PRESENT_MASK)
|
2014-12-25 00:52:16 +00:00
|
|
|
|
2012-04-19 11:06:29 +00:00
|
|
|
/* apic attention bits */
|
|
|
|
#define KVM_APIC_CHECK_VAPIC 0
|
2012-06-24 16:25:07 +00:00
|
|
|
/*
|
|
|
|
* The following bit is set with PV-EOI, unset on EOI.
|
|
|
|
* We detect PV-EOI changes by guest by comparing
|
|
|
|
* this bit with PV-EOI in guest memory.
|
|
|
|
* See the implementation in apic_update_pv_eoi.
|
|
|
|
*/
|
|
|
|
#define KVM_APIC_PV_EOI_PENDING 1
|
2012-04-19 11:06:29 +00:00
|
|
|
|
2015-09-18 14:29:49 +00:00
|
|
|
struct kvm_kernel_irq_routing_entry;
|
|
|
|
|
KVM: page track: add the framework of guest page tracking
The array, gfn_track[mode][gfn], is introduced in memory slot for every
guest page, this is the tracking count for the gust page on different
modes. If the page is tracked then the count is increased, the page is
not tracked after the count reaches zero
We use 'unsigned short' as the tracking count which should be enough as
shadow page table only can use 2^14 (2^3 for level, 2^1 for cr4_pae, 2^2
for quadrant, 2^3 for access, 2^1 for nxe, 2^1 for cr0_wp, 2^1 for
smep_andnot_wp, 2^1 for smap_andnot_wp, and 2^1 for smm) at most, there
is enough room for other trackers
Two callbacks, kvm_page_track_create_memslot() and
kvm_page_track_free_memslot() are implemented in this patch, they are
internally used to initialize and reclaim the memory of the array
Currently, only write track mode is supported
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-24 09:51:09 +00:00
|
|
|
/*
|
|
|
|
* the pages used as guest page table on soft mmu are tracked by
|
|
|
|
* kvm_memory_slot.arch.gfn_track which is 16 bits, so the role bits used
|
|
|
|
* by indirect shadow page can not be more than 15 bits.
|
|
|
|
*
|
KVM: x86: fix handling of role.cr4_pae and rename it to 'gpte_size'
The cr4_pae flag is a bit of a misnomer, its purpose is really to track
whether the guest PTE that is being shadowed is a 4-byte entry or an
8-byte entry. Prior to supporting nested EPT, the size of the gpte was
reflected purely by CR4.PAE. KVM fudged things a bit for direct sptes,
but it was mostly harmless since the size of the gpte never mattered.
Now that a spte may be tracking an indirect EPT entry, relying on
CR4.PAE is wrong and ill-named.
For direct shadow pages, force the gpte_size to '1' as they are always
8-byte entries; EPT entries can only be 8-bytes and KVM always uses
8-byte entries for NPT and its identity map (when running with EPT but
not unrestricted guest).
Likewise, nested EPT entries are always 8-bytes. Nested EPT presents a
unique scenario as the size of the entries are not dictated by CR4.PAE,
but neither is the shadow page a direct map. To handle this scenario,
set cr0_wp=1 and smap_andnot_wp=1, an otherwise impossible combination,
to denote a nested EPT shadow page. Use the information to avoid
incorrectly zapping an unsync'd indirect page in __kvm_sync_page().
Providing a consistent and accurate gpte_size fixes a bug reported by
Vitaly where fast_cr3_switch() always fails when switching from L2 to
L1 as kvm_mmu_get_page() would force role.cr4_pae=0 for direct pages,
whereas kvm_calc_mmu_role_common() would set it according to CR4.PAE.
Fixes: 7dcd575520082 ("x86/kvm/mmu: check if tdp/shadow MMU reconfiguration is needed")
Reported-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Tested-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-07 23:27:44 +00:00
|
|
|
* Currently, we used 14 bits that are @level, @gpte_is_8_bytes, @quadrant, @access,
|
KVM: page track: add the framework of guest page tracking
The array, gfn_track[mode][gfn], is introduced in memory slot for every
guest page, this is the tracking count for the gust page on different
modes. If the page is tracked then the count is increased, the page is
not tracked after the count reaches zero
We use 'unsigned short' as the tracking count which should be enough as
shadow page table only can use 2^14 (2^3 for level, 2^1 for cr4_pae, 2^2
for quadrant, 2^3 for access, 2^1 for nxe, 2^1 for cr0_wp, 2^1 for
smep_andnot_wp, 2^1 for smap_andnot_wp, and 2^1 for smm) at most, there
is enough room for other trackers
Two callbacks, kvm_page_track_create_memslot() and
kvm_page_track_free_memslot() are implemented in this patch, they are
internally used to initialize and reclaim the memory of the array
Currently, only write track mode is supported
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-24 09:51:09 +00:00
|
|
|
* @nxe, @cr0_wp, @smep_andnot_wp and @smap_andnot_wp.
|
|
|
|
*/
|
2007-12-14 01:41:22 +00:00
|
|
|
union kvm_mmu_page_role {
|
2018-10-08 19:28:10 +00:00
|
|
|
u32 word;
|
2007-12-14 01:41:22 +00:00
|
|
|
struct {
|
2008-03-23 08:02:34 +00:00
|
|
|
unsigned level:4;
|
KVM: x86: fix handling of role.cr4_pae and rename it to 'gpte_size'
The cr4_pae flag is a bit of a misnomer, its purpose is really to track
whether the guest PTE that is being shadowed is a 4-byte entry or an
8-byte entry. Prior to supporting nested EPT, the size of the gpte was
reflected purely by CR4.PAE. KVM fudged things a bit for direct sptes,
but it was mostly harmless since the size of the gpte never mattered.
Now that a spte may be tracking an indirect EPT entry, relying on
CR4.PAE is wrong and ill-named.
For direct shadow pages, force the gpte_size to '1' as they are always
8-byte entries; EPT entries can only be 8-bytes and KVM always uses
8-byte entries for NPT and its identity map (when running with EPT but
not unrestricted guest).
Likewise, nested EPT entries are always 8-bytes. Nested EPT presents a
unique scenario as the size of the entries are not dictated by CR4.PAE,
but neither is the shadow page a direct map. To handle this scenario,
set cr0_wp=1 and smap_andnot_wp=1, an otherwise impossible combination,
to denote a nested EPT shadow page. Use the information to avoid
incorrectly zapping an unsync'd indirect page in __kvm_sync_page().
Providing a consistent and accurate gpte_size fixes a bug reported by
Vitaly where fast_cr3_switch() always fails when switching from L2 to
L1 as kvm_mmu_get_page() would force role.cr4_pae=0 for direct pages,
whereas kvm_calc_mmu_role_common() would set it according to CR4.PAE.
Fixes: 7dcd575520082 ("x86/kvm/mmu: check if tdp/shadow MMU reconfiguration is needed")
Reported-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Tested-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-07 23:27:44 +00:00
|
|
|
unsigned gpte_is_8_bytes:1;
|
2008-03-23 08:02:34 +00:00
|
|
|
unsigned quadrant:2;
|
2009-01-11 11:02:10 +00:00
|
|
|
unsigned direct:1;
|
2008-03-23 08:02:34 +00:00
|
|
|
unsigned access:3;
|
2008-02-20 19:47:24 +00:00
|
|
|
unsigned invalid:1;
|
2009-03-31 08:31:54 +00:00
|
|
|
unsigned nxe:1;
|
2010-05-12 08:48:18 +00:00
|
|
|
unsigned cr0_wp:1;
|
2011-06-06 13:11:54 +00:00
|
|
|
unsigned smep_andnot_wp:1;
|
2015-05-11 14:55:21 +00:00
|
|
|
unsigned smap_andnot_wp:1;
|
2017-07-01 00:26:31 +00:00
|
|
|
unsigned ad_disabled:1;
|
2018-05-09 21:02:04 +00:00
|
|
|
unsigned guest_mode:1;
|
|
|
|
unsigned :6;
|
2015-05-18 13:03:39 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* This is left at the top of the word so that
|
|
|
|
* kvm_memslots_for_spte_role can extract it with a
|
|
|
|
* simple shift. While there is room, give it a whole
|
|
|
|
* byte so it is also faster to load it from memory.
|
|
|
|
*/
|
|
|
|
unsigned smm:8;
|
2007-12-14 01:41:22 +00:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2018-10-08 19:28:10 +00:00
|
|
|
union kvm_mmu_extended_role {
|
2018-10-08 19:28:11 +00:00
|
|
|
/*
|
|
|
|
* This structure complements kvm_mmu_page_role caching everything needed for
|
|
|
|
* MMU configuration. If nothing in both these structures changed, MMU
|
|
|
|
* re-configuration can be skipped. @valid bit is set on first usage so we don't
|
|
|
|
* treat all-zero structure as valid data.
|
|
|
|
*/
|
2018-10-08 19:28:10 +00:00
|
|
|
u32 word;
|
2018-10-08 19:28:11 +00:00
|
|
|
struct {
|
|
|
|
unsigned int valid:1;
|
|
|
|
unsigned int execonly:1;
|
2018-10-08 19:28:12 +00:00
|
|
|
unsigned int cr0_pg:1;
|
2019-04-30 17:33:26 +00:00
|
|
|
unsigned int cr4_pae:1;
|
2018-10-08 19:28:11 +00:00
|
|
|
unsigned int cr4_pse:1;
|
|
|
|
unsigned int cr4_pke:1;
|
|
|
|
unsigned int cr4_smap:1;
|
|
|
|
unsigned int cr4_smep:1;
|
2019-01-31 16:09:23 +00:00
|
|
|
unsigned int maxphyaddr:6;
|
2018-10-08 19:28:11 +00:00
|
|
|
};
|
2018-10-08 19:28:10 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
union kvm_mmu_role {
|
|
|
|
u64 as_u64;
|
|
|
|
struct {
|
|
|
|
union kvm_mmu_page_role base;
|
|
|
|
union kvm_mmu_extended_role ext;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2015-11-20 08:41:28 +00:00
|
|
|
struct kvm_rmap_head {
|
|
|
|
unsigned long val;
|
|
|
|
};
|
|
|
|
|
2009-01-04 10:39:07 +00:00
|
|
|
struct kvm_pio_request {
|
KVM: x86: update %rip after emulating IO
Most (all?) x86 platforms provide a port IO based reset mechanism, e.g.
OUT 92h or CF9h. Userspace may emulate said mechanism, i.e. reset a
vCPU in response to KVM_EXIT_IO, without explicitly announcing to KVM
that it is doing a reset, e.g. Qemu jams vCPU state and resumes running.
To avoid corruping %rip after such a reset, commit 0967b7bf1c22 ("KVM:
Skip pio instruction when it is emulated, not executed") changed the
behavior of PIO handlers, i.e. today's "fast" PIO handling to skip the
instruction prior to exiting to userspace. Full emulation doesn't need
such tricks becase re-emulating the instruction will naturally handle
%rip being changed to point at the reset vector.
Updating %rip prior to executing to userspace has several drawbacks:
- Userspace sees the wrong %rip on the exit, e.g. if PIO emulation
fails it will likely yell about the wrong address.
- Single step exits to userspace for are effectively dropped as
KVM_EXIT_DEBUG is overwritten with KVM_EXIT_IO.
- Behavior of PIO emulation is different depending on whether it
goes down the fast path or the slow path.
Rather than skip the PIO instruction before exiting to userspace,
snapshot the linear %rip and cancel PIO completion if the current
value does not match the snapshot. For a 64-bit vCPU, i.e. the most
common scenario, the snapshot and comparison has negligible overhead
as VMCS.GUEST_RIP will be cached regardless, i.e. there is no extra
VMREAD in this case.
All other alternatives to snapshotting the linear %rip that don't
rely on an explicit reset announcenment suffer from one corner case
or another. For example, canceling PIO completion on any write to
%rip fails if userspace does a save/restore of %rip, and attempting to
avoid that issue by canceling PIO only if %rip changed then fails if PIO
collides with the reset %rip. Attempting to zero in on the exact reset
vector won't work for APs, which means adding more hooks such as the
vCPU's MP_STATE, and so on and so forth.
Checking for a linear %rip match technically suffers from corner cases,
e.g. userspace could theoretically rewrite the underlying code page and
expect a different instruction to execute, or the guest hardcodes a PIO
reset at 0xfffffff0, but those are far, far outside of what can be
considered normal operation.
Fixes: 432baf60eee3 ("KVM: VMX: use kvm_fast_pio_in for handling IN I/O")
Cc: <stable@vger.kernel.org>
Reported-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-12 03:01:05 +00:00
|
|
|
unsigned long linear_rip;
|
2009-01-04 10:39:07 +00:00
|
|
|
unsigned long count;
|
|
|
|
int in;
|
|
|
|
int port;
|
|
|
|
int size;
|
|
|
|
};
|
|
|
|
|
2017-08-24 12:27:55 +00:00
|
|
|
#define PT64_ROOT_MAX_LEVEL 5
|
2017-08-24 12:27:54 +00:00
|
|
|
|
2015-08-05 04:04:21 +00:00
|
|
|
struct rsvd_bits_validate {
|
2017-08-24 12:27:54 +00:00
|
|
|
u64 rsvd_bits_mask[2][PT64_ROOT_MAX_LEVEL];
|
2015-08-05 04:04:21 +00:00
|
|
|
u64 bad_mt_xwr;
|
|
|
|
};
|
|
|
|
|
2018-06-27 21:59:06 +00:00
|
|
|
struct kvm_mmu_root_info {
|
2020-03-20 21:28:32 +00:00
|
|
|
gpa_t pgd;
|
2018-06-27 21:59:06 +00:00
|
|
|
hpa_t hpa;
|
|
|
|
};
|
|
|
|
|
|
|
|
#define KVM_MMU_ROOT_INFO_INVALID \
|
2020-03-20 21:28:32 +00:00
|
|
|
((struct kvm_mmu_root_info) { .pgd = INVALID_PAGE, .hpa = INVALID_PAGE })
|
2018-06-27 21:59:06 +00:00
|
|
|
|
2018-06-27 21:59:20 +00:00
|
|
|
#define KVM_MMU_NUM_PREV_ROOTS 3
|
|
|
|
|
2021-02-02 18:57:24 +00:00
|
|
|
#define KVM_HAVE_MMU_RWLOCK
|
|
|
|
|
2020-06-22 20:20:32 +00:00
|
|
|
struct kvm_mmu_page;
|
|
|
|
|
2007-12-14 01:41:22 +00:00
|
|
|
/*
|
2017-08-24 12:27:55 +00:00
|
|
|
* x86 supports 4 paging modes (5-level 64-bit, 4-level 64-bit, 3-level 32-bit,
|
|
|
|
* and 2-level 32-bit). The kvm_mmu structure abstracts the details of the
|
|
|
|
* current mmu mode.
|
2007-12-14 01:41:22 +00:00
|
|
|
*/
|
|
|
|
struct kvm_mmu {
|
2020-03-03 02:02:39 +00:00
|
|
|
unsigned long (*get_guest_pgd)(struct kvm_vcpu *vcpu);
|
2011-07-28 08:36:17 +00:00
|
|
|
u64 (*get_pdptr)(struct kvm_vcpu *vcpu, int index);
|
2019-12-06 23:57:14 +00:00
|
|
|
int (*page_fault)(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u32 err,
|
2010-12-07 02:48:06 +00:00
|
|
|
bool prefault);
|
2010-11-29 14:12:30 +00:00
|
|
|
void (*inject_page_fault)(struct kvm_vcpu *vcpu,
|
|
|
|
struct x86_exception *fault);
|
2019-12-06 23:57:14 +00:00
|
|
|
gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gpa_t gva_or_gpa,
|
|
|
|
u32 access, struct x86_exception *exception);
|
2014-09-02 11:23:06 +00:00
|
|
|
gpa_t (*translate_gpa)(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
|
|
|
|
struct x86_exception *exception);
|
2008-09-23 16:18:33 +00:00
|
|
|
int (*sync_page)(struct kvm_vcpu *vcpu,
|
2010-11-19 09:04:03 +00:00
|
|
|
struct kvm_mmu_page *sp);
|
2018-06-27 21:59:16 +00:00
|
|
|
void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root_hpa);
|
2007-12-14 01:41:22 +00:00
|
|
|
hpa_t root_hpa;
|
2020-03-20 21:28:32 +00:00
|
|
|
gpa_t root_pgd;
|
2018-10-08 19:28:10 +00:00
|
|
|
union kvm_mmu_role mmu_role;
|
2017-03-30 09:55:30 +00:00
|
|
|
u8 root_level;
|
|
|
|
u8 shadow_root_level;
|
|
|
|
u8 ept_ad;
|
2010-09-10 15:30:39 +00:00
|
|
|
bool direct_map;
|
2018-06-27 21:59:20 +00:00
|
|
|
struct kvm_mmu_root_info prev_roots[KVM_MMU_NUM_PREV_ROOTS];
|
2007-12-14 01:41:22 +00:00
|
|
|
|
KVM: MMU: Optimize pte permission checks
walk_addr_generic() permission checks are a maze of branchy code, which is
performed four times per lookup. It depends on the type of access, efer.nxe,
cr0.wp, cr4.smep, and in the near future, cr4.smap.
Optimize this away by precalculating all variants and storing them in a
bitmap. The bitmap is recalculated when rarely-changing variables change
(cr0, cr4) and is indexed by the often-changing variables (page fault error
code, pte access permissions).
The permission check is moved to the end of the loop, otherwise an SMEP
fault could be reported as a false positive, when PDE.U=1 but PTE.U=0.
Noted by Xiao Guangrong.
The result is short, branch-free code.
Reviewed-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2012-09-12 11:52:00 +00:00
|
|
|
/*
|
|
|
|
* Bitmap; bit set = permission fault
|
|
|
|
* Byte index: page fault error code [4:1]
|
|
|
|
* Bit index: pte permissions in ACC_* format
|
|
|
|
*/
|
|
|
|
u8 permissions[16];
|
|
|
|
|
2016-03-22 08:51:19 +00:00
|
|
|
/*
|
|
|
|
* The pkru_mask indicates if protection key checks are needed. It
|
|
|
|
* consists of 16 domains indexed by page fault error code bits [4:1],
|
|
|
|
* with PFEC.RSVD replaced by ACC_USER_MASK from the page tables.
|
|
|
|
* Each domain has 2 bits which are ANDed with AD and WD from PKRU.
|
|
|
|
*/
|
|
|
|
u32 pkru_mask;
|
|
|
|
|
2007-12-14 01:41:22 +00:00
|
|
|
u64 *pae_root;
|
2021-05-05 20:42:21 +00:00
|
|
|
u64 *pml4_root;
|
2015-08-05 04:04:24 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* check zero bits on shadow page table entries, these
|
|
|
|
* bits include not only hardware reserved bits but also
|
|
|
|
* the bits spte never used.
|
|
|
|
*/
|
|
|
|
struct rsvd_bits_validate shadow_zero_check;
|
|
|
|
|
2015-08-05 04:04:21 +00:00
|
|
|
struct rsvd_bits_validate guest_rsvd_check;
|
2010-09-10 15:30:57 +00:00
|
|
|
|
2016-02-23 11:51:19 +00:00
|
|
|
/* Can have large pages at levels 2..last_nonleaf_level-1. */
|
|
|
|
u8 last_nonleaf_level;
|
2012-09-12 17:46:56 +00:00
|
|
|
|
2010-09-10 15:31:01 +00:00
|
|
|
bool nx;
|
|
|
|
|
2010-09-10 15:30:57 +00:00
|
|
|
u64 pdptrs[4]; /* pae */
|
2007-12-14 01:41:22 +00:00
|
|
|
};
|
|
|
|
|
2018-12-06 13:21:04 +00:00
|
|
|
struct kvm_tlb_range {
|
|
|
|
u64 start_gfn;
|
|
|
|
u64 pages;
|
|
|
|
};
|
|
|
|
|
2011-11-10 12:57:22 +00:00
|
|
|
enum pmc_type {
|
|
|
|
KVM_PMC_GP = 0,
|
|
|
|
KVM_PMC_FIXED,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct kvm_pmc {
|
|
|
|
enum pmc_type type;
|
|
|
|
u8 idx;
|
|
|
|
u64 counter;
|
|
|
|
u64 eventsel;
|
|
|
|
struct perf_event *perf_event;
|
|
|
|
struct kvm_vcpu *vcpu;
|
KVM: x86/vPMU: Reuse perf_event to avoid unnecessary pmc_reprogram_counter
The perf_event_create_kernel_counter() in the pmc_reprogram_counter() is
a heavyweight and high-frequency operation, especially when host disables
the watchdog (maximum 21000000 ns) which leads to an unacceptable latency
of the guest NMI handler. It limits the use of vPMUs in the guest.
When a vPMC is fully enabled, the legacy reprogram_*_counter() would stop
and release its existing perf_event (if any) every time EVEN in most cases
almost the same requested perf_event will be created and configured again.
For each vPMC, if the reuqested config ('u64 eventsel' for gp and 'u8 ctrl'
for fixed) is the same as its current config AND a new sample period based
on pmc->counter is accepted by host perf interface, the current event could
be reused safely as a new created one does. Otherwise, do release the
undesirable perf_event and reprogram a new one as usual.
It's light-weight to call pmc_pause_counter (disable, read and reset event)
and pmc_resume_counter (recalibrate period and re-enable event) as guest
expects instead of release-and-create again on any condition. Compared to
use the filterable event->attr or hw.config, a new 'u64 current_config'
field is added to save the last original programed config for each vPMC.
Based on this implementation, the number of calls to pmc_reprogram_counter
is reduced by ~82.5% for a gp sampling event and ~99.9% for a fixed event.
In the usage of multiplexing perf sampling mode, the average latency of the
guest NMI handler is reduced from 104923 ns to 48393 ns (~2.16x speed up).
If host disables watchdog, the minimum latecy of guest NMI handler could be
speed up at ~3413x (from 20407603 to 5979 ns) and at ~786x in the average.
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-27 10:52:42 +00:00
|
|
|
/*
|
|
|
|
* eventsel value for general purpose counters,
|
|
|
|
* ctrl value for fixed counters.
|
|
|
|
*/
|
|
|
|
u64 current_config;
|
2011-11-10 12:57:22 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct kvm_pmu {
|
|
|
|
unsigned nr_arch_gp_counters;
|
|
|
|
unsigned nr_arch_fixed_counters;
|
|
|
|
unsigned available_event_types;
|
|
|
|
u64 fixed_ctr_ctrl;
|
|
|
|
u64 global_ctrl;
|
|
|
|
u64 global_status;
|
|
|
|
u64 global_ovf_ctrl;
|
|
|
|
u64 counter_bitmask[2];
|
|
|
|
u64 global_ctrl_mask;
|
2019-02-19 00:26:08 +00:00
|
|
|
u64 global_ovf_ctrl_mask;
|
2013-07-18 22:57:02 +00:00
|
|
|
u64 reserved_bits;
|
2011-11-10 12:57:22 +00:00
|
|
|
u8 version;
|
2012-06-20 18:46:33 +00:00
|
|
|
struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
|
|
|
|
struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
|
2011-11-10 12:57:22 +00:00
|
|
|
struct irq_work irq_work;
|
2019-10-21 10:55:04 +00:00
|
|
|
DECLARE_BITMAP(reprogram_pmi, X86_PMC_IDX_MAX);
|
2019-10-27 10:52:43 +00:00
|
|
|
DECLARE_BITMAP(all_valid_pmc_idx, X86_PMC_IDX_MAX);
|
|
|
|
DECLARE_BITMAP(pmc_in_use, X86_PMC_IDX_MAX);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The gate to release perf_events not marked in
|
|
|
|
* pmc_in_use only once in a vcpu time slice.
|
|
|
|
*/
|
|
|
|
bool need_cleanup;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The total number of programmed perf_events and it helps to avoid
|
|
|
|
* redundant check before cleanup if guest don't use vPMU at all.
|
|
|
|
*/
|
|
|
|
u8 event_count;
|
2011-11-10 12:57:22 +00:00
|
|
|
};
|
|
|
|
|
2015-06-19 13:45:05 +00:00
|
|
|
struct kvm_pmu_ops;
|
|
|
|
|
2014-02-21 08:55:56 +00:00
|
|
|
enum {
|
|
|
|
KVM_DEBUGREG_BP_ENABLED = 1,
|
2014-02-21 09:17:24 +00:00
|
|
|
KVM_DEBUGREG_WONT_EXIT = 2,
|
2015-04-02 00:10:37 +00:00
|
|
|
KVM_DEBUGREG_RELOAD = 4,
|
2014-02-21 08:55:56 +00:00
|
|
|
};
|
|
|
|
|
2015-06-15 08:55:27 +00:00
|
|
|
struct kvm_mtrr_range {
|
|
|
|
u64 base;
|
|
|
|
u64 mask;
|
2015-06-15 08:55:31 +00:00
|
|
|
struct list_head node;
|
2015-06-15 08:55:27 +00:00
|
|
|
};
|
|
|
|
|
2015-06-15 08:55:24 +00:00
|
|
|
struct kvm_mtrr {
|
2015-06-15 08:55:27 +00:00
|
|
|
struct kvm_mtrr_range var_ranges[KVM_NR_VAR_MTRR];
|
2015-06-15 08:55:24 +00:00
|
|
|
mtrr_type fixed_ranges[KVM_NR_FIXED_MTRR_REGION];
|
2015-06-15 08:55:26 +00:00
|
|
|
u64 deftype;
|
2015-06-15 08:55:31 +00:00
|
|
|
|
|
|
|
struct list_head head;
|
2015-06-15 08:55:24 +00:00
|
|
|
};
|
|
|
|
|
2015-11-30 16:22:21 +00:00
|
|
|
/* Hyper-V SynIC timer */
|
|
|
|
struct kvm_vcpu_hv_stimer {
|
|
|
|
struct hrtimer timer;
|
|
|
|
int index;
|
2018-11-26 15:47:30 +00:00
|
|
|
union hv_stimer_config config;
|
2015-11-30 16:22:21 +00:00
|
|
|
u64 count;
|
|
|
|
u64 exp_time;
|
|
|
|
struct hv_message msg;
|
|
|
|
bool msg_pending;
|
|
|
|
};
|
|
|
|
|
2015-11-10 12:36:34 +00:00
|
|
|
/* Hyper-V synthetic interrupt controller (SynIC)*/
|
|
|
|
struct kvm_vcpu_hv_synic {
|
|
|
|
u64 version;
|
|
|
|
u64 control;
|
|
|
|
u64 msg_page;
|
|
|
|
u64 evt_page;
|
|
|
|
atomic64_t sint[HV_SYNIC_SINT_COUNT];
|
|
|
|
atomic_t sint_to_gsi[HV_SYNIC_SINT_COUNT];
|
|
|
|
DECLARE_BITMAP(auto_eoi_bitmap, 256);
|
|
|
|
DECLARE_BITMAP(vec_bitmap, 256);
|
|
|
|
bool active;
|
kvm: x86: hyperv: add KVM_CAP_HYPERV_SYNIC2
There is a flaw in the Hyper-V SynIC implementation in KVM: when message
page or event flags page is enabled by setting the corresponding msr,
KVM zeroes it out. This is problematic because on migration the
corresponding MSRs are loaded on the destination, so the content of
those pages is lost.
This went unnoticed so far because the only user of those pages was
in-KVM hyperv synic timers, which could continue working despite that
zeroing.
Newer QEMU uses those pages for Hyper-V VMBus implementation, and
zeroing them breaks the migration.
Besides, in newer QEMU the content of those pages is fully managed by
QEMU, so zeroing them is undesirable even when writing the MSRs from the
guest side.
To support this new scheme, introduce a new capability,
KVM_CAP_HYPERV_SYNIC2, which, when enabled, makes sure that the synic
pages aren't zeroed out in KVM.
Signed-off-by: Roman Kagan <rkagan@virtuozzo.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2017-06-22 13:51:01 +00:00
|
|
|
bool dont_zero_synic_pages;
|
2015-11-10 12:36:34 +00:00
|
|
|
};
|
|
|
|
|
2015-07-03 12:01:34 +00:00
|
|
|
/* Hyper-V per vcpu emulation context */
|
|
|
|
struct kvm_vcpu_hv {
|
2021-01-26 13:48:13 +00:00
|
|
|
struct kvm_vcpu *vcpu;
|
2017-07-14 14:13:20 +00:00
|
|
|
u32 vp_index;
|
2015-07-03 12:01:34 +00:00
|
|
|
u64 hv_vapic;
|
2015-09-16 09:29:50 +00:00
|
|
|
s64 runtime_offset;
|
2015-11-10 12:36:34 +00:00
|
|
|
struct kvm_vcpu_hv_synic synic;
|
2015-11-10 12:36:35 +00:00
|
|
|
struct kvm_hyperv_exit exit;
|
2015-11-30 16:22:21 +00:00
|
|
|
struct kvm_vcpu_hv_stimer stimer[HV_SYNIC_STIMER_COUNT];
|
|
|
|
DECLARE_BITMAP(stimer_pending_bitmap, HV_SYNIC_STIMER_COUNT);
|
2018-10-08 17:19:04 +00:00
|
|
|
cpumask_t tlb_flush;
|
2015-07-03 12:01:34 +00:00
|
|
|
};
|
|
|
|
|
2018-06-13 13:55:44 +00:00
|
|
|
/* Xen HVM per vcpu emulation context */
|
|
|
|
struct kvm_vcpu_xen {
|
|
|
|
u64 hypercall_rip;
|
2021-03-01 12:53:09 +00:00
|
|
|
u32 current_runstate;
|
2018-06-29 14:52:52 +00:00
|
|
|
bool vcpu_info_set;
|
2018-07-23 15:20:57 +00:00
|
|
|
bool vcpu_time_info_set;
|
2021-03-01 12:53:09 +00:00
|
|
|
bool runstate_set;
|
2018-06-29 14:52:52 +00:00
|
|
|
struct gfn_to_hva_cache vcpu_info_cache;
|
2018-07-23 15:20:57 +00:00
|
|
|
struct gfn_to_hva_cache vcpu_time_info_cache;
|
2021-03-01 12:53:09 +00:00
|
|
|
struct gfn_to_hva_cache runstate_cache;
|
|
|
|
u64 last_steal;
|
|
|
|
u64 runstate_entry_time;
|
|
|
|
u64 runstate_times[4];
|
2018-06-13 13:55:44 +00:00
|
|
|
};
|
|
|
|
|
2007-12-13 15:50:52 +00:00
|
|
|
struct kvm_vcpu_arch {
|
2008-06-27 17:58:02 +00:00
|
|
|
/*
|
|
|
|
* rip and regs accesses must go through
|
|
|
|
* kvm_{register,rip}_{read,write} functions.
|
|
|
|
*/
|
|
|
|
unsigned long regs[NR_VCPU_REGS];
|
|
|
|
u32 regs_avail;
|
|
|
|
u32 regs_dirty;
|
2007-10-20 07:34:38 +00:00
|
|
|
|
|
|
|
unsigned long cr0;
|
2009-12-29 16:43:06 +00:00
|
|
|
unsigned long cr0_guest_owned_bits;
|
2007-10-20 07:34:38 +00:00
|
|
|
unsigned long cr2;
|
|
|
|
unsigned long cr3;
|
|
|
|
unsigned long cr4;
|
2009-12-07 10:16:48 +00:00
|
|
|
unsigned long cr4_guest_owned_bits;
|
2020-07-08 00:39:55 +00:00
|
|
|
unsigned long cr4_guest_rsvd_bits;
|
2007-10-20 07:34:38 +00:00
|
|
|
unsigned long cr8;
|
2020-05-12 23:59:06 +00:00
|
|
|
u32 host_pkru;
|
2017-08-23 21:14:38 +00:00
|
|
|
u32 pkru;
|
2008-11-25 19:17:04 +00:00
|
|
|
u32 hflags;
|
2010-01-21 13:31:50 +00:00
|
|
|
u64 efer;
|
2007-10-20 07:34:38 +00:00
|
|
|
u64 apic_base;
|
|
|
|
struct kvm_lapic *apic; /* kernel irqchip context */
|
2015-11-10 12:36:33 +00:00
|
|
|
bool apicv_active;
|
KVM: nVMX: Do not load EOI-exitmap while running L2
When L1 IOAPIC redirection-table is written, a request of
KVM_REQ_SCAN_IOAPIC is set on all vCPUs. This is done such that
all vCPUs will now recalc their IOAPIC handled vectors and load
it to their EOI-exitmap.
However, it could be that one of the vCPUs is currently running
L2. In this case, load_eoi_exitmap() will be called which would
write to vmcs02->eoi_exit_bitmap, which is wrong because
vmcs02->eoi_exit_bitmap should always be equal to
vmcs12->eoi_exit_bitmap. Furthermore, at this point
KVM_REQ_SCAN_IOAPIC was already consumed and therefore we will
never update vmcs01->eoi_exit_bitmap. This could lead to remote_irr
of some IOAPIC level-triggered entry to remain set forever.
Fix this issue by delaying the load of EOI-exitmap to when vCPU
is running L1.
One may wonder why not just delay entire KVM_REQ_SCAN_IOAPIC
processing to when vCPU is running L1. This is done in order to handle
correctly the case where LAPIC & IO-APIC of L1 is pass-throughed into
L2. In this case, vmcs12->virtual_interrupt_delivery should be 0. In
current nVMX implementation, that results in
vmcs02->virtual_interrupt_delivery to also be 0. Thus,
vmcs02->eoi_exit_bitmap is not used. Therefore, every L2 EOI cause
a #VMExit into L0 (either on MSR_WRITE to x2APIC MSR or
APIC_ACCESS/APIC_WRITE/EPT_MISCONFIG to APIC MMIO page).
In order for such L2 EOI to be broadcasted, if needed, from LAPIC
to IO-APIC, vcpu->arch.ioapic_handled_vectors must be updated
while L2 is running. Therefore, patch makes sure to delay only the
loading of EOI-exitmap but not the update of
vcpu->arch.ioapic_handled_vectors.
Reviewed-by: Arbel Moshe <arbel.moshe@oracle.com>
Reviewed-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-21 00:50:31 +00:00
|
|
|
bool load_eoi_exitmap_pending;
|
2015-11-10 12:36:32 +00:00
|
|
|
DECLARE_BITMAP(ioapic_handled_vectors, 256);
|
2012-04-19 11:06:29 +00:00
|
|
|
unsigned long apic_attention;
|
2009-03-05 14:34:59 +00:00
|
|
|
int32_t apic_arb_prio;
|
2007-10-20 07:34:38 +00:00
|
|
|
int mp_state;
|
|
|
|
u64 ia32_misc_enable_msr;
|
2015-05-07 09:36:11 +00:00
|
|
|
u64 smbase;
|
2017-11-15 11:43:14 +00:00
|
|
|
u64 smi_count;
|
2007-10-22 14:50:39 +00:00
|
|
|
bool tpr_access_reporting;
|
2019-10-21 23:30:20 +00:00
|
|
|
bool xsaves_enabled;
|
2014-12-02 11:14:59 +00:00
|
|
|
u64 ia32_xss;
|
2018-02-28 06:03:31 +00:00
|
|
|
u64 microcode_version;
|
2019-03-07 23:43:02 +00:00
|
|
|
u64 arch_capabilities;
|
2020-05-29 07:43:45 +00:00
|
|
|
u64 perf_capabilities;
|
2007-10-20 07:34:38 +00:00
|
|
|
|
2010-09-10 15:30:49 +00:00
|
|
|
/*
|
|
|
|
* Paging state of the vcpu
|
|
|
|
*
|
|
|
|
* If the vcpu runs in guest mode with two level paging this still saves
|
|
|
|
* the paging mode of the l1 guest. This context is always used to
|
|
|
|
* handle faults.
|
|
|
|
*/
|
2018-10-08 19:28:05 +00:00
|
|
|
struct kvm_mmu *mmu;
|
|
|
|
|
|
|
|
/* Non-nested MMU for L1 */
|
|
|
|
struct kvm_mmu root_mmu;
|
2010-09-10 15:30:46 +00:00
|
|
|
|
2018-10-08 19:28:08 +00:00
|
|
|
/* L1 MMU when running nested */
|
|
|
|
struct kvm_mmu guest_mmu;
|
|
|
|
|
2010-09-10 15:30:50 +00:00
|
|
|
/*
|
|
|
|
* Paging state of an L2 guest (used for nested npt)
|
|
|
|
*
|
|
|
|
* This context will save all necessary information to walk page tables
|
2019-12-11 06:26:25 +00:00
|
|
|
* of an L2 guest. This context is only initialized for page table
|
2010-09-10 15:30:50 +00:00
|
|
|
* walking and not for faulting since we never handle l2 page faults on
|
|
|
|
* the host.
|
|
|
|
*/
|
|
|
|
struct kvm_mmu nested_mmu;
|
|
|
|
|
2010-09-10 15:30:49 +00:00
|
|
|
/*
|
|
|
|
* Pointer to the mmu context currently used for
|
|
|
|
* gva_to_gpa translations.
|
|
|
|
*/
|
|
|
|
struct kvm_mmu *walk_mmu;
|
|
|
|
|
2011-05-15 15:26:20 +00:00
|
|
|
struct kvm_mmu_memory_cache mmu_pte_list_desc_cache;
|
2020-07-03 02:35:33 +00:00
|
|
|
struct kvm_mmu_memory_cache mmu_shadow_page_cache;
|
|
|
|
struct kvm_mmu_memory_cache mmu_gfn_array_cache;
|
2007-10-20 07:34:38 +00:00
|
|
|
struct kvm_mmu_memory_cache mmu_page_header_cache;
|
|
|
|
|
x86,kvm: move qemu/guest FPU switching out to vcpu_run
Currently, every time a VCPU is scheduled out, the host kernel will
first save the guest FPU/xstate context, then load the qemu userspace
FPU context, only to then immediately save the qemu userspace FPU
context back to memory. When scheduling in a VCPU, the same extraneous
FPU loads and saves are done.
This could be avoided by moving from a model where the guest FPU is
loaded and stored with preemption disabled, to a model where the
qemu userspace FPU is swapped out for the guest FPU context for
the duration of the KVM_RUN ioctl.
This is done under the VCPU mutex, which is also taken when other
tasks inspect the VCPU FPU context, so the code should already be
safe for this change. That should come as no surprise, given that
s390 already has this optimization.
This can fix a bug where KVM calls get_user_pages while owning the
FPU, and the file system ends up requesting the FPU again:
[258270.527947] __warn+0xcb/0xf0
[258270.527948] warn_slowpath_null+0x1d/0x20
[258270.527951] kernel_fpu_disable+0x3f/0x50
[258270.527953] __kernel_fpu_begin+0x49/0x100
[258270.527955] kernel_fpu_begin+0xe/0x10
[258270.527958] crc32c_pcl_intel_update+0x84/0xb0
[258270.527961] crypto_shash_update+0x3f/0x110
[258270.527968] crc32c+0x63/0x8a [libcrc32c]
[258270.527975] dm_bm_checksum+0x1b/0x20 [dm_persistent_data]
[258270.527978] node_prepare_for_write+0x44/0x70 [dm_persistent_data]
[258270.527985] dm_block_manager_write_callback+0x41/0x50 [dm_persistent_data]
[258270.527988] submit_io+0x170/0x1b0 [dm_bufio]
[258270.527992] __write_dirty_buffer+0x89/0x90 [dm_bufio]
[258270.527994] __make_buffer_clean+0x4f/0x80 [dm_bufio]
[258270.527996] __try_evict_buffer+0x42/0x60 [dm_bufio]
[258270.527998] dm_bufio_shrink_scan+0xc0/0x130 [dm_bufio]
[258270.528002] shrink_slab.part.40+0x1f5/0x420
[258270.528004] shrink_node+0x22c/0x320
[258270.528006] do_try_to_free_pages+0xf5/0x330
[258270.528008] try_to_free_pages+0xe9/0x190
[258270.528009] __alloc_pages_slowpath+0x40f/0xba0
[258270.528011] __alloc_pages_nodemask+0x209/0x260
[258270.528014] alloc_pages_vma+0x1f1/0x250
[258270.528017] do_huge_pmd_anonymous_page+0x123/0x660
[258270.528021] handle_mm_fault+0xfd3/0x1330
[258270.528025] __get_user_pages+0x113/0x640
[258270.528027] get_user_pages+0x4f/0x60
[258270.528063] __gfn_to_pfn_memslot+0x120/0x3f0 [kvm]
[258270.528108] try_async_pf+0x66/0x230 [kvm]
[258270.528135] tdp_page_fault+0x130/0x280 [kvm]
[258270.528149] kvm_mmu_page_fault+0x60/0x120 [kvm]
[258270.528158] handle_ept_violation+0x91/0x170 [kvm_intel]
[258270.528162] vmx_handle_exit+0x1ca/0x1400 [kvm_intel]
No performance changes were detected in quick ping-pong tests on
my 4 socket system, which is expected since an FPU+xstate load is
on the order of 0.1us, while ping-ponging between CPUs is on the
order of 20us, and somewhat noisy.
Cc: stable@vger.kernel.org
Signed-off-by: Rik van Riel <riel@redhat.com>
Suggested-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[Fixed a bug where reset_vcpu called put_fpu without preceding load_fpu,
which happened inside from KVM_CREATE_VCPU ioctl. - Radim]
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2017-11-14 21:54:23 +00:00
|
|
|
/*
|
|
|
|
* QEMU userspace and the guest each have their own FPU state.
|
2019-07-22 11:31:27 +00:00
|
|
|
* In vcpu_run, we switch between the user and guest FPU contexts.
|
|
|
|
* While running a VCPU, the VCPU thread will have the guest FPU
|
|
|
|
* context.
|
x86,kvm: move qemu/guest FPU switching out to vcpu_run
Currently, every time a VCPU is scheduled out, the host kernel will
first save the guest FPU/xstate context, then load the qemu userspace
FPU context, only to then immediately save the qemu userspace FPU
context back to memory. When scheduling in a VCPU, the same extraneous
FPU loads and saves are done.
This could be avoided by moving from a model where the guest FPU is
loaded and stored with preemption disabled, to a model where the
qemu userspace FPU is swapped out for the guest FPU context for
the duration of the KVM_RUN ioctl.
This is done under the VCPU mutex, which is also taken when other
tasks inspect the VCPU FPU context, so the code should already be
safe for this change. That should come as no surprise, given that
s390 already has this optimization.
This can fix a bug where KVM calls get_user_pages while owning the
FPU, and the file system ends up requesting the FPU again:
[258270.527947] __warn+0xcb/0xf0
[258270.527948] warn_slowpath_null+0x1d/0x20
[258270.527951] kernel_fpu_disable+0x3f/0x50
[258270.527953] __kernel_fpu_begin+0x49/0x100
[258270.527955] kernel_fpu_begin+0xe/0x10
[258270.527958] crc32c_pcl_intel_update+0x84/0xb0
[258270.527961] crypto_shash_update+0x3f/0x110
[258270.527968] crc32c+0x63/0x8a [libcrc32c]
[258270.527975] dm_bm_checksum+0x1b/0x20 [dm_persistent_data]
[258270.527978] node_prepare_for_write+0x44/0x70 [dm_persistent_data]
[258270.527985] dm_block_manager_write_callback+0x41/0x50 [dm_persistent_data]
[258270.527988] submit_io+0x170/0x1b0 [dm_bufio]
[258270.527992] __write_dirty_buffer+0x89/0x90 [dm_bufio]
[258270.527994] __make_buffer_clean+0x4f/0x80 [dm_bufio]
[258270.527996] __try_evict_buffer+0x42/0x60 [dm_bufio]
[258270.527998] dm_bufio_shrink_scan+0xc0/0x130 [dm_bufio]
[258270.528002] shrink_slab.part.40+0x1f5/0x420
[258270.528004] shrink_node+0x22c/0x320
[258270.528006] do_try_to_free_pages+0xf5/0x330
[258270.528008] try_to_free_pages+0xe9/0x190
[258270.528009] __alloc_pages_slowpath+0x40f/0xba0
[258270.528011] __alloc_pages_nodemask+0x209/0x260
[258270.528014] alloc_pages_vma+0x1f1/0x250
[258270.528017] do_huge_pmd_anonymous_page+0x123/0x660
[258270.528021] handle_mm_fault+0xfd3/0x1330
[258270.528025] __get_user_pages+0x113/0x640
[258270.528027] get_user_pages+0x4f/0x60
[258270.528063] __gfn_to_pfn_memslot+0x120/0x3f0 [kvm]
[258270.528108] try_async_pf+0x66/0x230 [kvm]
[258270.528135] tdp_page_fault+0x130/0x280 [kvm]
[258270.528149] kvm_mmu_page_fault+0x60/0x120 [kvm]
[258270.528158] handle_ept_violation+0x91/0x170 [kvm_intel]
[258270.528162] vmx_handle_exit+0x1ca/0x1400 [kvm_intel]
No performance changes were detected in quick ping-pong tests on
my 4 socket system, which is expected since an FPU+xstate load is
on the order of 0.1us, while ping-ponging between CPUs is on the
order of 20us, and somewhat noisy.
Cc: stable@vger.kernel.org
Signed-off-by: Rik van Riel <riel@redhat.com>
Suggested-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[Fixed a bug where reset_vcpu called put_fpu without preceding load_fpu,
which happened inside from KVM_CREATE_VCPU ioctl. - Radim]
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2017-11-14 21:54:23 +00:00
|
|
|
*
|
|
|
|
* Note that while the PKRU state lives inside the fpu registers,
|
|
|
|
* it is switched out separately at VMENTER and VMEXIT time. The
|
|
|
|
* "guest_fpu" state here contains the guest FPU context, with the
|
|
|
|
* host PRKU bits.
|
|
|
|
*/
|
2019-07-22 04:26:21 +00:00
|
|
|
struct fpu *user_fpu;
|
2018-11-06 22:53:56 +00:00
|
|
|
struct fpu *guest_fpu;
|
x86,kvm: move qemu/guest FPU switching out to vcpu_run
Currently, every time a VCPU is scheduled out, the host kernel will
first save the guest FPU/xstate context, then load the qemu userspace
FPU context, only to then immediately save the qemu userspace FPU
context back to memory. When scheduling in a VCPU, the same extraneous
FPU loads and saves are done.
This could be avoided by moving from a model where the guest FPU is
loaded and stored with preemption disabled, to a model where the
qemu userspace FPU is swapped out for the guest FPU context for
the duration of the KVM_RUN ioctl.
This is done under the VCPU mutex, which is also taken when other
tasks inspect the VCPU FPU context, so the code should already be
safe for this change. That should come as no surprise, given that
s390 already has this optimization.
This can fix a bug where KVM calls get_user_pages while owning the
FPU, and the file system ends up requesting the FPU again:
[258270.527947] __warn+0xcb/0xf0
[258270.527948] warn_slowpath_null+0x1d/0x20
[258270.527951] kernel_fpu_disable+0x3f/0x50
[258270.527953] __kernel_fpu_begin+0x49/0x100
[258270.527955] kernel_fpu_begin+0xe/0x10
[258270.527958] crc32c_pcl_intel_update+0x84/0xb0
[258270.527961] crypto_shash_update+0x3f/0x110
[258270.527968] crc32c+0x63/0x8a [libcrc32c]
[258270.527975] dm_bm_checksum+0x1b/0x20 [dm_persistent_data]
[258270.527978] node_prepare_for_write+0x44/0x70 [dm_persistent_data]
[258270.527985] dm_block_manager_write_callback+0x41/0x50 [dm_persistent_data]
[258270.527988] submit_io+0x170/0x1b0 [dm_bufio]
[258270.527992] __write_dirty_buffer+0x89/0x90 [dm_bufio]
[258270.527994] __make_buffer_clean+0x4f/0x80 [dm_bufio]
[258270.527996] __try_evict_buffer+0x42/0x60 [dm_bufio]
[258270.527998] dm_bufio_shrink_scan+0xc0/0x130 [dm_bufio]
[258270.528002] shrink_slab.part.40+0x1f5/0x420
[258270.528004] shrink_node+0x22c/0x320
[258270.528006] do_try_to_free_pages+0xf5/0x330
[258270.528008] try_to_free_pages+0xe9/0x190
[258270.528009] __alloc_pages_slowpath+0x40f/0xba0
[258270.528011] __alloc_pages_nodemask+0x209/0x260
[258270.528014] alloc_pages_vma+0x1f1/0x250
[258270.528017] do_huge_pmd_anonymous_page+0x123/0x660
[258270.528021] handle_mm_fault+0xfd3/0x1330
[258270.528025] __get_user_pages+0x113/0x640
[258270.528027] get_user_pages+0x4f/0x60
[258270.528063] __gfn_to_pfn_memslot+0x120/0x3f0 [kvm]
[258270.528108] try_async_pf+0x66/0x230 [kvm]
[258270.528135] tdp_page_fault+0x130/0x280 [kvm]
[258270.528149] kvm_mmu_page_fault+0x60/0x120 [kvm]
[258270.528158] handle_ept_violation+0x91/0x170 [kvm_intel]
[258270.528162] vmx_handle_exit+0x1ca/0x1400 [kvm_intel]
No performance changes were detected in quick ping-pong tests on
my 4 socket system, which is expected since an FPU+xstate load is
on the order of 0.1us, while ping-ponging between CPUs is on the
order of 20us, and somewhat noisy.
Cc: stable@vger.kernel.org
Signed-off-by: Rik van Riel <riel@redhat.com>
Suggested-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[Fixed a bug where reset_vcpu called put_fpu without preceding load_fpu,
which happened inside from KVM_CREATE_VCPU ioctl. - Radim]
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2017-11-14 21:54:23 +00:00
|
|
|
|
2010-06-10 03:27:12 +00:00
|
|
|
u64 xcr0;
|
2013-10-02 14:06:15 +00:00
|
|
|
u64 guest_supported_xcr0;
|
2007-10-20 07:34:38 +00:00
|
|
|
|
|
|
|
struct kvm_pio_request pio;
|
|
|
|
void *pio_data;
|
2020-12-10 17:09:54 +00:00
|
|
|
void *guest_ins_data;
|
2007-10-20 07:34:38 +00:00
|
|
|
|
2009-05-11 10:35:50 +00:00
|
|
|
u8 event_exit_inst_len;
|
|
|
|
|
2007-11-25 11:41:11 +00:00
|
|
|
struct kvm_queued_exception {
|
|
|
|
bool pending;
|
2017-08-24 10:35:09 +00:00
|
|
|
bool injected;
|
2007-11-25 11:41:11 +00:00
|
|
|
bool has_error_code;
|
|
|
|
u8 nr;
|
|
|
|
u32 error_code;
|
2018-10-16 21:29:19 +00:00
|
|
|
unsigned long payload;
|
|
|
|
bool has_payload;
|
2017-07-14 01:30:41 +00:00
|
|
|
u8 nested_apf;
|
2007-11-25 11:41:11 +00:00
|
|
|
} exception;
|
|
|
|
|
2008-07-03 12:17:01 +00:00
|
|
|
struct kvm_queued_interrupt {
|
KVM: x86: Rename interrupt.pending to interrupt.injected
For exceptions & NMIs events, KVM code use the following
coding convention:
*) "pending" represents an event that should be injected to guest at
some point but it's side-effects have not yet occurred.
*) "injected" represents an event that it's side-effects have already
occurred.
However, interrupts don't conform to this coding convention.
All current code flows mark interrupt.pending when it's side-effects
have already taken place (For example, bit moved from LAPIC IRR to
ISR). Therefore, it makes sense to just rename
interrupt.pending to interrupt.injected.
This change follows logic of previous commit 664f8e26b00c ("KVM: X86:
Fix loss of exception which has not yet been injected") which changed
exception to follow this coding convention as well.
It is important to note that in case !lapic_in_kernel(vcpu),
interrupt.pending usage was and still incorrect.
In this case, interrrupt.pending can only be set using one of the
following ioctls: KVM_INTERRUPT, KVM_SET_VCPU_EVENTS and
KVM_SET_SREGS. Looking at how QEMU uses these ioctls, one can see that
QEMU uses them either to re-set an "interrupt.pending" state it has
received from KVM (via KVM_GET_VCPU_EVENTS interrupt.pending or
via KVM_GET_SREGS interrupt_bitmap) or by dispatching a new interrupt
from QEMU's emulated LAPIC which reset bit in IRR and set bit in ISR
before sending ioctl to KVM. So it seems that indeed "interrupt.pending"
in this case is also suppose to represent "interrupt.injected".
However, kvm_cpu_has_interrupt() & kvm_cpu_has_injectable_intr()
is misusing (now named) interrupt.injected in order to return if
there is a pending interrupt.
This leads to nVMX/nSVM not be able to distinguish if it should exit
from L2 to L1 on EXTERNAL_INTERRUPT on pending interrupt or should
re-inject an injected interrupt.
Therefore, add a FIXME at these functions for handling this issue.
This patch introduce no semantics change.
Signed-off-by: Liran Alon <liran.alon@oracle.com>
Reviewed-by: Nikita Leshenko <nikita.leshchenko@oracle.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2018-03-23 00:01:31 +00:00
|
|
|
bool injected;
|
2009-05-11 10:35:50 +00:00
|
|
|
bool soft;
|
2008-07-03 12:17:01 +00:00
|
|
|
u8 nr;
|
|
|
|
} interrupt;
|
|
|
|
|
2007-10-20 07:34:38 +00:00
|
|
|
int halt_request; /* real mode on Intel only */
|
|
|
|
|
|
|
|
int cpuid_nent;
|
2020-10-01 13:05:40 +00:00
|
|
|
struct kvm_cpuid_entry2 *cpuid_entries;
|
2015-03-29 20:56:12 +00:00
|
|
|
|
KVM: x86: SEV: Treat C-bit as legal GPA bit regardless of vCPU mode
Rename cr3_lm_rsvd_bits to reserved_gpa_bits, and use it for all GPA
legality checks. AMD's APM states:
If the C-bit is an address bit, this bit is masked from the guest
physical address when it is translated through the nested page tables.
Thus, any access that can conceivably be run through NPT should ignore
the C-bit when checking for validity.
For features that KVM emulates in software, e.g. MTRRs, there is no
clear direction in the APM for how the C-bit should be handled. For
such cases, follow the SME behavior inasmuch as possible, since SEV is
is essentially a VM-specific variant of SME. For SME, the APM states:
In this case the upper physical address bits are treated as reserved
when the feature is enabled except where otherwise indicated.
Collecting the various relavant SME snippets in the APM and cross-
referencing the omissions with Linux kernel code, this leaves MTTRs and
APIC_BASE as the only flows that KVM emulates that should _not_ ignore
the C-bit.
Note, this means the reserved bit checks in the page tables are
technically broken. This will be remedied in a future patch.
Although the page table checks are technically broken, in practice, it's
all but guaranteed to be irrelevant. NPT is required for SEV, i.e.
shadowing page tables isn't needed in the common case. Theoretically,
the checks could be in play for nested NPT, but it's extremely unlikely
that anyone is running nested VMs on SEV, as doing so would require L1
to expose sensitive data to L0, e.g. the entire VMCB. And if anyone is
running nested VMs, L0 can't read the guest's encrypted memory, i.e. L1
would need to put its NPT in shared memory, in which case the C-bit will
never be set. Or, L1 could use shadow paging, but again, if L0 needs to
read page tables, e.g. to load PDPTRs, the memory can't be encrypted if
L1 has any expectation of L0 doing the right thing.
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210204000117.3303214-8-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-02-04 00:01:12 +00:00
|
|
|
u64 reserved_gpa_bits;
|
2015-03-29 20:56:12 +00:00
|
|
|
int maxphyaddr;
|
2020-07-16 03:41:20 +00:00
|
|
|
int max_tdp_level;
|
2015-03-29 20:56:12 +00:00
|
|
|
|
2007-10-20 07:34:38 +00:00
|
|
|
/* emulate context */
|
|
|
|
|
2020-02-18 23:29:48 +00:00
|
|
|
struct x86_emulate_ctxt *emulate_ctxt;
|
2011-03-31 10:06:41 +00:00
|
|
|
bool emulate_regs_need_sync_to_vcpu;
|
|
|
|
bool emulate_regs_need_sync_from_vcpu;
|
2012-09-03 12:24:26 +00:00
|
|
|
int (*complete_userspace_io)(struct kvm_vcpu *vcpu);
|
2008-02-15 19:52:47 +00:00
|
|
|
|
|
|
|
gpa_t time;
|
2008-06-03 14:17:31 +00:00
|
|
|
struct pvclock_vcpu_time_info hv_clock;
|
2010-08-20 08:07:23 +00:00
|
|
|
unsigned int hw_tsc_khz;
|
2013-02-20 22:48:10 +00:00
|
|
|
struct gfn_to_hva_cache pv_time;
|
|
|
|
bool pv_time_enabled;
|
2012-08-03 18:57:49 +00:00
|
|
|
/* set guest stopped flag in pvclock flags field */
|
|
|
|
bool pvclock_set_guest_stopped_request;
|
2011-07-11 19:28:14 +00:00
|
|
|
|
|
|
|
struct {
|
2019-12-06 15:36:12 +00:00
|
|
|
u8 preempted;
|
2011-07-11 19:28:14 +00:00
|
|
|
u64 msr_val;
|
|
|
|
u64 last_steal;
|
2019-12-05 01:30:51 +00:00
|
|
|
struct gfn_to_pfn_cache cache;
|
2011-07-11 19:28:14 +00:00
|
|
|
} st;
|
|
|
|
|
2020-05-02 04:32:25 +00:00
|
|
|
u64 l1_tsc_offset;
|
2021-05-26 18:44:09 +00:00
|
|
|
u64 tsc_offset; /* current tsc offset */
|
2010-08-20 08:07:30 +00:00
|
|
|
u64 last_guest_tsc;
|
2012-02-03 17:43:54 +00:00
|
|
|
u64 last_host_tsc;
|
2012-02-03 17:43:56 +00:00
|
|
|
u64 tsc_offset_adjustment;
|
2012-02-03 17:43:57 +00:00
|
|
|
u64 this_tsc_nsec;
|
|
|
|
u64 this_tsc_write;
|
2014-06-24 07:42:43 +00:00
|
|
|
u64 this_tsc_generation;
|
2010-09-19 00:38:15 +00:00
|
|
|
bool tsc_catchup;
|
KVM: Infrastructure for software and hardware based TSC rate scaling
This requires some restructuring; rather than use 'virtual_tsc_khz'
to indicate whether hardware rate scaling is in effect, we consider
each VCPU to always have a virtual TSC rate. Instead, there is new
logic above the vendor-specific hardware scaling that decides whether
it is even necessary to use and updates all rate variables used by
common code. This means we can simply query the virtual rate at
any point, which is needed for software rate scaling.
There is also now a threshold added to the TSC rate scaling; minor
differences and variations of measured TSC rate can accidentally
provoke rate scaling to be used when it is not needed. Instead,
we have a tolerance variable called tsc_tolerance_ppm, which is
the maximum variation from user requested rate at which scaling
will be used. The default is 250ppm, which is the half the
threshold for NTP adjustment, allowing for some hardware variation.
In the event that hardware rate scaling is not available, we can
kludge a bit by forcing TSC catchup to turn on when a faster than
hardware speed has been requested, but there is nothing available
yet for the reverse case; this requires a trap and emulate software
implementation for RDTSC, which is still forthcoming.
[avi: fix 64-bit division on i386]
Signed-off-by: Zachary Amsden <zamsden@gmail.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
2012-02-03 17:43:50 +00:00
|
|
|
bool tsc_always_catchup;
|
|
|
|
s8 virtual_tsc_shift;
|
|
|
|
u32 virtual_tsc_mult;
|
|
|
|
u32 virtual_tsc_khz;
|
2012-11-29 20:42:50 +00:00
|
|
|
s64 ia32_tsc_adjust_msr;
|
2019-06-06 12:32:59 +00:00
|
|
|
u64 msr_ia32_power_ctl;
|
2021-05-26 18:44:09 +00:00
|
|
|
u64 l1_tsc_scaling_ratio;
|
|
|
|
u64 tsc_scaling_ratio; /* current scaling ratio */
|
2008-05-15 01:52:48 +00:00
|
|
|
|
2011-09-20 10:43:14 +00:00
|
|
|
atomic_t nmi_queued; /* unprocessed asynchronous NMIs */
|
|
|
|
unsigned nmi_pending; /* NMI queued after currently running handler */
|
|
|
|
bool nmi_injected; /* Trying to inject an NMI this entry */
|
2015-04-01 13:06:40 +00:00
|
|
|
bool smi_pending; /* SMI queued after currently running handler */
|
2008-05-26 17:06:35 +00:00
|
|
|
|
2015-06-15 08:55:24 +00:00
|
|
|
struct kvm_mtrr mtrr_state;
|
2014-06-19 09:40:18 +00:00
|
|
|
u64 pat;
|
2008-12-15 12:52:10 +00:00
|
|
|
|
2014-02-21 08:55:56 +00:00
|
|
|
unsigned switch_db_regs;
|
2008-12-15 12:52:10 +00:00
|
|
|
unsigned long db[KVM_NR_DB_REGS];
|
|
|
|
unsigned long dr6;
|
|
|
|
unsigned long dr7;
|
|
|
|
unsigned long eff_db[KVM_NR_DB_REGS];
|
2012-09-21 03:42:55 +00:00
|
|
|
unsigned long guest_debug_dr7;
|
2017-03-20 08:16:28 +00:00
|
|
|
u64 msr_platform_info;
|
|
|
|
u64 msr_misc_features_enables;
|
2009-05-11 08:48:15 +00:00
|
|
|
|
|
|
|
u64 mcg_cap;
|
|
|
|
u64 mcg_status;
|
|
|
|
u64 mcg_ctl;
|
2016-06-22 06:59:56 +00:00
|
|
|
u64 mcg_ext_ctl;
|
2009-05-11 08:48:15 +00:00
|
|
|
u64 *mce_banks;
|
2009-10-18 11:24:44 +00:00
|
|
|
|
2011-07-11 19:23:20 +00:00
|
|
|
/* Cache MMIO info */
|
|
|
|
u64 mmio_gva;
|
2019-08-01 20:35:21 +00:00
|
|
|
unsigned mmio_access;
|
2011-07-11 19:23:20 +00:00
|
|
|
gfn_t mmio_gfn;
|
2014-08-18 22:46:07 +00:00
|
|
|
u64 mmio_gen;
|
2011-07-11 19:23:20 +00:00
|
|
|
|
2011-11-10 12:57:22 +00:00
|
|
|
struct kvm_pmu pmu;
|
|
|
|
|
2009-10-18 11:24:44 +00:00
|
|
|
/* used for guest single stepping over the given code position */
|
|
|
|
unsigned long singlestep_rip;
|
2010-02-23 16:47:55 +00:00
|
|
|
|
2021-01-26 13:48:14 +00:00
|
|
|
bool hyperv_enabled;
|
2021-01-26 13:48:13 +00:00
|
|
|
struct kvm_vcpu_hv *hyperv;
|
2018-06-13 13:55:44 +00:00
|
|
|
struct kvm_vcpu_xen xen;
|
2010-06-30 04:25:15 +00:00
|
|
|
|
|
|
|
cpumask_var_t wbinvd_dirty_mask;
|
2010-10-14 09:22:46 +00:00
|
|
|
|
2011-09-22 09:02:48 +00:00
|
|
|
unsigned long last_retry_eip;
|
|
|
|
unsigned long last_retry_addr;
|
|
|
|
|
2010-10-14 09:22:46 +00:00
|
|
|
struct {
|
|
|
|
bool halted;
|
2020-04-16 15:58:59 +00:00
|
|
|
gfn_t gfns[ASYNC_PF_PER_VCPU];
|
2010-10-14 09:22:50 +00:00
|
|
|
struct gfn_to_hva_cache data;
|
2020-05-25 14:41:20 +00:00
|
|
|
u64 msr_en_val; /* MSR_KVM_ASYNC_PF_EN */
|
|
|
|
u64 msr_int_val; /* MSR_KVM_ASYNC_PF_INT */
|
|
|
|
u16 vec;
|
2010-10-14 09:22:53 +00:00
|
|
|
u32 id;
|
2010-10-14 09:22:55 +00:00
|
|
|
bool send_user_only;
|
2020-05-25 14:41:17 +00:00
|
|
|
u32 host_apf_flags;
|
2017-07-14 01:30:41 +00:00
|
|
|
unsigned long nested_apf_token;
|
2017-07-14 01:30:42 +00:00
|
|
|
bool delivery_as_pf_vmexit;
|
2020-05-25 14:41:21 +00:00
|
|
|
bool pageready_pending;
|
2010-10-14 09:22:46 +00:00
|
|
|
} apf;
|
2012-01-09 19:00:35 +00:00
|
|
|
|
|
|
|
/* OSVW MSRs (AMD only) */
|
|
|
|
struct {
|
|
|
|
u64 length;
|
|
|
|
u64 status;
|
|
|
|
} osvw;
|
2012-06-24 16:25:07 +00:00
|
|
|
|
|
|
|
struct {
|
|
|
|
u64 msr_val;
|
|
|
|
struct gfn_to_hva_cache data;
|
|
|
|
} pv_eoi;
|
2013-01-13 15:49:07 +00:00
|
|
|
|
2019-06-03 22:52:44 +00:00
|
|
|
u64 msr_kvm_poll_control;
|
|
|
|
|
2013-01-13 15:49:07 +00:00
|
|
|
/*
|
2020-02-07 15:22:45 +00:00
|
|
|
* Indicates the guest is trying to write a gfn that contains one or
|
|
|
|
* more of the PTEs used to translate the write itself, i.e. the access
|
|
|
|
* is changing its own translation in the guest page tables. KVM exits
|
|
|
|
* to userspace if emulation of the faulting instruction fails and this
|
|
|
|
* flag is set, as KVM cannot make forward progress.
|
|
|
|
*
|
|
|
|
* If emulation fails for a write to guest page tables, KVM unprotects
|
|
|
|
* (zaps) the shadow page for the target gfn and resumes the guest to
|
|
|
|
* retry the non-emulatable instruction (on hardware). Unprotecting the
|
|
|
|
* gfn doesn't allow forward progress for a self-changing access because
|
|
|
|
* doing so also zaps the translation for the gfn, i.e. retrying the
|
|
|
|
* instruction will hit a !PRESENT fault, which results in a new shadow
|
|
|
|
* page and sends KVM back to square one.
|
2013-01-13 15:49:07 +00:00
|
|
|
*/
|
|
|
|
bool write_fault_to_shadow_pgtable;
|
2013-08-06 09:00:32 +00:00
|
|
|
|
|
|
|
/* set at EPT violation at this point */
|
|
|
|
unsigned long exit_qualification;
|
2013-08-26 08:48:34 +00:00
|
|
|
|
|
|
|
/* pv related host specific info */
|
|
|
|
struct {
|
|
|
|
bool pv_unhalted;
|
|
|
|
} pv;
|
2015-07-30 06:21:41 +00:00
|
|
|
|
|
|
|
int pending_ioapic_eoi;
|
KVM: x86: Add support for local interrupt requests from userspace
In order to enable userspace PIC support, the userspace PIC needs to
be able to inject local interrupts even when the APICs are in the
kernel.
KVM_INTERRUPT now supports sending local interrupts to an APIC when
APICs are in the kernel.
The ready_for_interrupt_request flag is now only set when the CPU/APIC
will immediately accept and inject an interrupt (i.e. APIC has not
masked the PIC).
When the PIC wishes to initiate an INTA cycle with, say, CPU0, it
kicks CPU0 out of the guest, and renedezvous with CPU0 once it arrives
in userspace.
When the CPU/APIC unmasks the PIC, a KVM_EXIT_IRQ_WINDOW_OPEN is
triggered, so that userspace has a chance to inject a PIC interrupt
if it had been pending.
Overall, this design can lead to a small number of spurious userspace
renedezvous. In particular, whenever the PIC transistions from low to
high while it is masked and whenever the PIC becomes unmasked while
it is low.
Note: this does not buffer more than one local interrupt in the
kernel, so the VMM needs to enter the guest in order to complete
interrupt injection before injecting an additional interrupt.
Compiles for x86.
Can pass the KVM Unit Tests.
Signed-off-by: Steve Rutherford <srutherford@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-30 09:27:16 +00:00
|
|
|
int pending_external_vector;
|
2016-12-14 19:59:23 +00:00
|
|
|
|
2017-08-08 04:05:33 +00:00
|
|
|
/* be preempted when it's in kernel-mode(cpl=0) */
|
|
|
|
bool preempted_in_kernel;
|
x86/KVM/VMX: Add L1D flush logic
Add the logic for flushing L1D on VMENTER. The flush depends on the static
key being enabled and the new l1tf_flush_l1d flag being set.
The flags is set:
- Always, if the flush module parameter is 'always'
- Conditionally at:
- Entry to vcpu_run(), i.e. after executing user space
- From the sched_in notifier, i.e. when switching to a vCPU thread.
- From vmexit handlers which are considered unsafe, i.e. where
sensitive data can be brought into L1D:
- The emulator, which could be a good target for other speculative
execution-based threats,
- The MMU, which can bring host page tables in the L1 cache.
- External interrupts
- Nested operations that require the MMU (see above). That is
vmptrld, vmptrst, vmclear,vmwrite,vmread.
- When handling invept,invvpid
[ tglx: Split out from combo patch and reduced to a single flag ]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2018-07-02 11:07:14 +00:00
|
|
|
|
|
|
|
/* Flush the L1 Data cache for L1TF mitigation on VMENTER */
|
|
|
|
bool l1tf_flush_l1d;
|
2019-04-18 16:32:50 +00:00
|
|
|
|
2020-06-03 23:56:22 +00:00
|
|
|
/* Host CPU on which VM-entry was most recently attempted */
|
|
|
|
unsigned int last_vmentry_cpu;
|
|
|
|
|
2019-04-18 16:32:50 +00:00
|
|
|
/* AMD MSRC001_0015 Hardware Configuration */
|
|
|
|
u64 msr_hwcr;
|
2020-08-18 15:24:28 +00:00
|
|
|
|
|
|
|
/* pv related cpuid info */
|
|
|
|
struct {
|
|
|
|
/*
|
|
|
|
* value of the eax register in the KVM_CPUID_FEATURES CPUID
|
|
|
|
* leaf.
|
|
|
|
*/
|
|
|
|
u32 features;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* indicates whether pv emulation should be disabled if features
|
|
|
|
* are not present in the guest's cpuid
|
|
|
|
*/
|
|
|
|
bool enforce;
|
|
|
|
} pv_cpuid;
|
2020-12-10 17:09:40 +00:00
|
|
|
|
|
|
|
/* Protected Guests */
|
|
|
|
bool guest_state_protected;
|
2007-10-20 07:34:38 +00:00
|
|
|
};
|
|
|
|
|
2012-02-08 04:02:18 +00:00
|
|
|
struct kvm_lpage_info {
|
2016-02-24 09:51:06 +00:00
|
|
|
int disallow_lpage;
|
2012-02-08 04:02:18 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
struct kvm_arch_memory_slot {
|
2015-11-20 08:41:28 +00:00
|
|
|
struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES];
|
2012-02-08 04:02:18 +00:00
|
|
|
struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES - 1];
|
KVM: page track: add the framework of guest page tracking
The array, gfn_track[mode][gfn], is introduced in memory slot for every
guest page, this is the tracking count for the gust page on different
modes. If the page is tracked then the count is increased, the page is
not tracked after the count reaches zero
We use 'unsigned short' as the tracking count which should be enough as
shadow page table only can use 2^14 (2^3 for level, 2^1 for cr4_pae, 2^2
for quadrant, 2^3 for access, 2^1 for nxe, 2^1 for cr0_wp, 2^1 for
smep_andnot_wp, 2^1 for smap_andnot_wp, and 2^1 for smm) at most, there
is enough room for other trackers
Two callbacks, kvm_page_track_create_memslot() and
kvm_page_track_free_memslot() are implemented in this patch, they are
internally used to initialize and reclaim the memory of the array
Currently, only write track mode is supported
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-24 09:51:09 +00:00
|
|
|
unsigned short *gfn_track[KVM_PAGE_TRACK_MAX];
|
2012-02-08 04:02:18 +00:00
|
|
|
};
|
|
|
|
|
2015-02-12 18:41:33 +00:00
|
|
|
/*
|
|
|
|
* We use as the mode the number of bits allocated in the LDR for the
|
|
|
|
* logical processor ID. It happens that these are all powers of two.
|
|
|
|
* This makes it is very easy to detect cases where the APICs are
|
|
|
|
* configured for multiple modes; in that case, we cannot use the map and
|
|
|
|
* hence cannot use kvm_irq_delivery_to_apic_fast either.
|
|
|
|
*/
|
|
|
|
#define KVM_APIC_MODE_XAPIC_CLUSTER 4
|
|
|
|
#define KVM_APIC_MODE_XAPIC_FLAT 8
|
|
|
|
#define KVM_APIC_MODE_X2APIC 16
|
|
|
|
|
2012-09-13 14:19:24 +00:00
|
|
|
struct kvm_apic_map {
|
|
|
|
struct rcu_head rcu;
|
2015-02-12 18:41:33 +00:00
|
|
|
u8 mode;
|
2016-07-12 20:09:20 +00:00
|
|
|
u32 max_apic_id;
|
2016-07-12 20:09:19 +00:00
|
|
|
union {
|
|
|
|
struct kvm_lapic *xapic_flat_map[8];
|
|
|
|
struct kvm_lapic *xapic_cluster_map[16][4];
|
|
|
|
};
|
2016-07-12 20:09:20 +00:00
|
|
|
struct kvm_lapic *phys_map[];
|
2012-09-13 14:19:24 +00:00
|
|
|
};
|
|
|
|
|
2020-05-29 13:45:40 +00:00
|
|
|
/* Hyper-V synthetic debugger (SynDbg)*/
|
|
|
|
struct kvm_hv_syndbg {
|
|
|
|
struct {
|
|
|
|
u64 control;
|
|
|
|
u64 status;
|
|
|
|
u64 send_page;
|
|
|
|
u64 recv_page;
|
|
|
|
u64 pending_page;
|
|
|
|
} control;
|
|
|
|
u64 options;
|
|
|
|
};
|
|
|
|
|
2021-03-16 14:37:35 +00:00
|
|
|
/* Current state of Hyper-V TSC page clocksource */
|
|
|
|
enum hv_tsc_page_status {
|
|
|
|
/* TSC page was not set up or disabled */
|
|
|
|
HV_TSC_PAGE_UNSET = 0,
|
|
|
|
/* TSC page MSR was written by the guest, update pending */
|
|
|
|
HV_TSC_PAGE_GUEST_CHANGED,
|
|
|
|
/* TSC page MSR was written by KVM userspace, update pending */
|
|
|
|
HV_TSC_PAGE_HOST_CHANGED,
|
|
|
|
/* TSC page was properly set up and is currently active */
|
|
|
|
HV_TSC_PAGE_SET,
|
|
|
|
/* TSC page is currently being updated and therefore is inactive */
|
|
|
|
HV_TSC_PAGE_UPDATING,
|
|
|
|
/* TSC page was set up with an inaccessible GPA */
|
|
|
|
HV_TSC_PAGE_BROKEN,
|
|
|
|
};
|
|
|
|
|
2015-07-03 12:01:34 +00:00
|
|
|
/* Hyper-V emulation context */
|
|
|
|
struct kvm_hv {
|
2016-12-12 09:12:53 +00:00
|
|
|
struct mutex hv_lock;
|
2015-07-03 12:01:34 +00:00
|
|
|
u64 hv_guest_os_id;
|
|
|
|
u64 hv_hypercall;
|
|
|
|
u64 hv_tsc_page;
|
2021-03-16 14:37:35 +00:00
|
|
|
enum hv_tsc_page_status hv_tsc_page_status;
|
2015-07-03 12:01:37 +00:00
|
|
|
|
|
|
|
/* Hyper-v based guest crash (NT kernel bugcheck) parameters */
|
|
|
|
u64 hv_crash_param[HV_X64_MSR_CRASH_PARAMS];
|
|
|
|
u64 hv_crash_ctl;
|
2016-02-08 11:54:12 +00:00
|
|
|
|
2020-04-22 19:57:34 +00:00
|
|
|
struct ms_hyperv_tsc_page tsc_ref;
|
2018-02-01 13:48:32 +00:00
|
|
|
|
|
|
|
struct idr conn_to_evt;
|
2018-03-01 14:15:12 +00:00
|
|
|
|
|
|
|
u64 hv_reenlightenment_control;
|
|
|
|
u64 hv_tsc_emulation_control;
|
|
|
|
u64 hv_tsc_emulation_status;
|
2018-09-26 17:02:56 +00:00
|
|
|
|
|
|
|
/* How many vCPUs have VP index != vCPU index */
|
|
|
|
atomic_t num_mismatched_vp_indexes;
|
2019-08-22 14:30:21 +00:00
|
|
|
|
|
|
|
struct hv_partition_assist_pg *hv_pa_pg;
|
2020-05-29 13:45:40 +00:00
|
|
|
struct kvm_hv_syndbg hv_syndbg;
|
2015-07-03 12:01:34 +00:00
|
|
|
};
|
|
|
|
|
2020-09-25 14:34:21 +00:00
|
|
|
struct msr_bitmap_range {
|
|
|
|
u32 flags;
|
|
|
|
u32 nmsrs;
|
|
|
|
u32 base;
|
|
|
|
unsigned long *bitmap;
|
|
|
|
};
|
|
|
|
|
2020-12-03 16:20:32 +00:00
|
|
|
/* Xen emulation context */
|
|
|
|
struct kvm_xen {
|
|
|
|
bool long_mode;
|
2018-06-16 01:17:14 +00:00
|
|
|
bool shinfo_set;
|
2020-12-09 20:08:30 +00:00
|
|
|
u8 upcall_vector;
|
2018-06-16 01:17:14 +00:00
|
|
|
struct gfn_to_hva_cache shinfo_cache;
|
2020-12-03 16:20:32 +00:00
|
|
|
};
|
|
|
|
|
2016-12-16 15:10:02 +00:00
|
|
|
enum kvm_irqchip_mode {
|
|
|
|
KVM_IRQCHIP_NONE,
|
|
|
|
KVM_IRQCHIP_KERNEL, /* created with KVM_CREATE_IRQCHIP */
|
|
|
|
KVM_IRQCHIP_SPLIT, /* created with KVM_CAP_SPLIT_IRQCHIP */
|
|
|
|
};
|
|
|
|
|
KVM: x86: Protect userspace MSR filter with SRCU, and set atomically-ish
Fix a plethora of issues with MSR filtering by installing the resulting
filter as an atomic bundle instead of updating the live filter one range
at a time. The KVM_X86_SET_MSR_FILTER ioctl() isn't truly atomic, as
the hardware MSR bitmaps won't be updated until the next VM-Enter, but
the relevant software struct is atomically updated, which is what KVM
really needs.
Similar to the approach used for modifying memslots, make arch.msr_filter
a SRCU-protected pointer, do all the work configuring the new filter
outside of kvm->lock, and then acquire kvm->lock only when the new filter
has been vetted and created. That way vCPU readers either see the old
filter or the new filter in their entirety, not some half-baked state.
Yuan Yao pointed out a use-after-free in ksm_msr_allowed() due to a
TOCTOU bug, but that's just the tip of the iceberg...
- Nothing is __rcu annotated, making it nigh impossible to audit the
code for correctness.
- kvm_add_msr_filter() has an unpaired smp_wmb(). Violation of kernel
coding style aside, the lack of a smb_rmb() anywhere casts all code
into doubt.
- kvm_clear_msr_filter() has a double free TOCTOU bug, as it grabs
count before taking the lock.
- kvm_clear_msr_filter() also has memory leak due to the same TOCTOU bug.
The entire approach of updating the live filter is also flawed. While
installing a new filter is inherently racy if vCPUs are running, fixing
the above issues also makes it trivial to ensure certain behavior is
deterministic, e.g. KVM can provide deterministic behavior for MSRs with
identical settings in the old and new filters. An atomic update of the
filter also prevents KVM from getting into a half-baked state, e.g. if
installing a filter fails, the existing approach would leave the filter
in a half-baked state, having already committed whatever bits of the
filter were already processed.
[*] https://lkml.kernel.org/r/20210312083157.25403-1-yaoyuan0329os@gmail.com
Fixes: 1a155254ff93 ("KVM: x86: Introduce MSR filtering")
Cc: stable@vger.kernel.org
Cc: Alexander Graf <graf@amazon.com>
Reported-by: Yuan Yao <yaoyuan0329os@gmail.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210316184436.2544875-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-03-16 18:44:33 +00:00
|
|
|
struct kvm_x86_msr_filter {
|
|
|
|
u8 count;
|
|
|
|
bool default_allow:1;
|
|
|
|
struct msr_bitmap_range ranges[16];
|
|
|
|
};
|
|
|
|
|
2019-11-14 20:15:05 +00:00
|
|
|
#define APICV_INHIBIT_REASON_DISABLE 0
|
2019-11-14 20:15:13 +00:00
|
|
|
#define APICV_INHIBIT_REASON_HYPERV 1
|
2019-11-14 20:15:14 +00:00
|
|
|
#define APICV_INHIBIT_REASON_NESTED 2
|
2019-11-14 20:15:15 +00:00
|
|
|
#define APICV_INHIBIT_REASON_IRQWIN 3
|
2019-11-14 20:15:16 +00:00
|
|
|
#define APICV_INHIBIT_REASON_PIT_REINJ 4
|
2020-02-28 08:59:04 +00:00
|
|
|
#define APICV_INHIBIT_REASON_X2APIC 5
|
2019-11-14 20:15:05 +00:00
|
|
|
|
2009-12-23 16:35:17 +00:00
|
|
|
struct kvm_arch {
|
2019-04-08 18:07:30 +00:00
|
|
|
unsigned long n_used_mmu_pages;
|
|
|
|
unsigned long n_requested_mmu_pages;
|
|
|
|
unsigned long n_max_mmu_pages;
|
2011-05-15 15:20:27 +00:00
|
|
|
unsigned int indirect_shadow_pages;
|
2019-09-13 02:46:11 +00:00
|
|
|
u8 mmu_valid_gen;
|
2007-12-14 02:01:48 +00:00
|
|
|
struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
|
|
|
|
struct list_head active_mmu_pages;
|
2019-09-13 02:46:09 +00:00
|
|
|
struct list_head zapped_obsolete_pages;
|
2019-11-04 19:26:00 +00:00
|
|
|
struct list_head lpage_disallowed_mmu_pages;
|
2016-02-24 09:51:16 +00:00
|
|
|
struct kvm_page_track_notifier_node mmu_sp_tracker;
|
2016-02-24 09:51:13 +00:00
|
|
|
struct kvm_page_track_notifier_head track_notifier_head;
|
2013-05-31 00:36:29 +00:00
|
|
|
|
2008-07-28 16:26:26 +00:00
|
|
|
struct list_head assigned_dev_head;
|
2008-12-03 13:43:34 +00:00
|
|
|
struct iommu_domain *iommu_domain;
|
2013-10-30 17:02:23 +00:00
|
|
|
bool iommu_noncoherent;
|
2013-10-30 17:02:30 +00:00
|
|
|
#define __KVM_HAVE_ARCH_NONCOHERENT_DMA
|
|
|
|
atomic_t noncoherent_dma_count;
|
2015-07-07 13:41:58 +00:00
|
|
|
#define __KVM_HAVE_ARCH_ASSIGNED_DEVICE
|
|
|
|
atomic_t assigned_device_count;
|
2007-12-14 02:17:34 +00:00
|
|
|
struct kvm_pic *vpic;
|
|
|
|
struct kvm_ioapic *vioapic;
|
2008-01-27 21:10:22 +00:00
|
|
|
struct kvm_pit *vpit;
|
2015-07-01 13:31:49 +00:00
|
|
|
atomic_t vapics_in_nmi_mode;
|
2012-09-13 14:19:24 +00:00
|
|
|
struct mutex apic_map_lock;
|
2021-03-05 19:11:23 +00:00
|
|
|
struct kvm_apic_map __rcu *apic_map;
|
2020-06-22 14:37:42 +00:00
|
|
|
atomic_t apic_map_dirty;
|
2007-12-14 02:20:16 +00:00
|
|
|
|
2014-09-24 07:57:58 +00:00
|
|
|
bool apic_access_page_done;
|
2019-11-14 20:15:05 +00:00
|
|
|
unsigned long apicv_inhibit_reasons;
|
2008-02-15 19:52:47 +00:00
|
|
|
|
|
|
|
gpa_t wall_clock;
|
2008-04-25 13:44:52 +00:00
|
|
|
|
2018-03-12 11:53:02 +00:00
|
|
|
bool mwait_in_guest;
|
2018-03-12 11:53:03 +00:00
|
|
|
bool hlt_in_guest;
|
2018-03-12 11:53:04 +00:00
|
|
|
bool pause_in_guest;
|
2019-05-21 06:06:53 +00:00
|
|
|
bool cstate_in_guest;
|
2018-03-12 11:53:02 +00:00
|
|
|
|
2008-10-15 12:15:06 +00:00
|
|
|
unsigned long irq_sources_bitmap;
|
2009-10-16 19:28:36 +00:00
|
|
|
s64 kvmclock_offset;
|
2011-02-04 09:49:11 +00:00
|
|
|
raw_spinlock_t tsc_write_lock;
|
2010-08-20 08:07:20 +00:00
|
|
|
u64 last_tsc_nsec;
|
|
|
|
u64 last_tsc_write;
|
KVM: Improve TSC offset matching
There are a few improvements that can be made to the TSC offset
matching code. First, we don't need to call the 128-bit multiply
(especially on a constant number), the code works much nicer to
do computation in nanosecond units.
Second, the way everything is setup with software TSC rate scaling,
we currently have per-cpu rates. Obviously this isn't too desirable
to use in practice, but if for some reason we do change the rate of
all VCPUs at runtime, then reset the TSCs, we will only want to
match offsets for VCPUs running at the same rate.
Finally, for the case where we have an unstable host TSC, but
rate scaling is being done in hardware, we should call the platform
code to compute the TSC offset, so the math is reorganized to recompute
the base instead, then transform the base into an offset using the
existing API.
[avi: fix 64-bit division on i386]
Signed-off-by: Zachary Amsden <zamsden@gmail.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
KVM: Fix 64-bit division in kvm_write_tsc()
Breaks i386 build.
Signed-off-by: Avi Kivity <avi@redhat.com>
2012-02-03 17:43:51 +00:00
|
|
|
u32 last_tsc_khz;
|
2012-02-03 17:43:57 +00:00
|
|
|
u64 cur_tsc_nsec;
|
|
|
|
u64 cur_tsc_write;
|
|
|
|
u64 cur_tsc_offset;
|
2014-06-24 07:42:43 +00:00
|
|
|
u64 cur_tsc_generation;
|
2012-11-28 01:29:03 +00:00
|
|
|
int nr_vcpus_matched_tsc;
|
2009-10-15 22:21:43 +00:00
|
|
|
|
2012-11-28 01:29:01 +00:00
|
|
|
spinlock_t pvclock_gtod_sync_lock;
|
|
|
|
bool use_master_clock;
|
|
|
|
u64 master_kernel_ns;
|
2016-12-21 19:32:01 +00:00
|
|
|
u64 master_cycle_now;
|
2014-02-28 11:52:54 +00:00
|
|
|
struct delayed_work kvmclock_update_work;
|
2014-02-28 11:52:55 +00:00
|
|
|
struct delayed_work kvmclock_sync_work;
|
2012-11-28 01:29:01 +00:00
|
|
|
|
2009-10-15 22:21:43 +00:00
|
|
|
struct kvm_xen_hvm_config xen_hvm_config;
|
2010-01-17 13:51:22 +00:00
|
|
|
|
2014-11-20 12:45:31 +00:00
|
|
|
/* reads protected by irq_srcu, writes by irq_lock */
|
|
|
|
struct hlist_head mask_notifier_list;
|
|
|
|
|
2015-07-03 12:01:34 +00:00
|
|
|
struct kvm_hv hyperv;
|
2020-12-03 16:20:32 +00:00
|
|
|
struct kvm_xen xen;
|
2010-12-23 08:08:35 +00:00
|
|
|
|
|
|
|
#ifdef CONFIG_KVM_MMU_AUDIT
|
|
|
|
int audit_point;
|
|
|
|
#endif
|
2015-01-20 17:54:52 +00:00
|
|
|
|
2017-06-26 07:56:43 +00:00
|
|
|
bool backwards_tsc_observed;
|
2015-01-20 17:54:52 +00:00
|
|
|
bool boot_vcpu_runs_old_kvmclock;
|
2015-07-29 09:56:48 +00:00
|
|
|
u32 bsp_vcpu_id;
|
2015-04-12 22:53:41 +00:00
|
|
|
|
|
|
|
u64 disabled_quirks;
|
2021-02-13 00:50:12 +00:00
|
|
|
int cpu_dirty_logging_count;
|
2015-07-30 06:21:40 +00:00
|
|
|
|
2016-12-16 15:10:02 +00:00
|
|
|
enum kvm_irqchip_mode irqchip_mode;
|
2015-07-30 06:32:35 +00:00
|
|
|
u8 nr_reserved_ioapic_pins;
|
2016-01-25 08:53:33 +00:00
|
|
|
|
|
|
|
bool disabled_lapic_found;
|
2016-05-04 19:09:46 +00:00
|
|
|
|
2016-07-12 20:09:27 +00:00
|
|
|
bool x2apic_format;
|
2016-07-12 20:09:28 +00:00
|
|
|
bool x2apic_broadcast_quirk_disabled;
|
2018-08-20 17:32:15 +00:00
|
|
|
|
|
|
|
bool guest_can_read_msr_platform_info;
|
2018-10-16 21:29:20 +00:00
|
|
|
bool exception_payload_enabled;
|
2019-07-11 01:25:15 +00:00
|
|
|
|
KVM: x86: Protect userspace MSR filter with SRCU, and set atomically-ish
Fix a plethora of issues with MSR filtering by installing the resulting
filter as an atomic bundle instead of updating the live filter one range
at a time. The KVM_X86_SET_MSR_FILTER ioctl() isn't truly atomic, as
the hardware MSR bitmaps won't be updated until the next VM-Enter, but
the relevant software struct is atomically updated, which is what KVM
really needs.
Similar to the approach used for modifying memslots, make arch.msr_filter
a SRCU-protected pointer, do all the work configuring the new filter
outside of kvm->lock, and then acquire kvm->lock only when the new filter
has been vetted and created. That way vCPU readers either see the old
filter or the new filter in their entirety, not some half-baked state.
Yuan Yao pointed out a use-after-free in ksm_msr_allowed() due to a
TOCTOU bug, but that's just the tip of the iceberg...
- Nothing is __rcu annotated, making it nigh impossible to audit the
code for correctness.
- kvm_add_msr_filter() has an unpaired smp_wmb(). Violation of kernel
coding style aside, the lack of a smb_rmb() anywhere casts all code
into doubt.
- kvm_clear_msr_filter() has a double free TOCTOU bug, as it grabs
count before taking the lock.
- kvm_clear_msr_filter() also has memory leak due to the same TOCTOU bug.
The entire approach of updating the live filter is also flawed. While
installing a new filter is inherently racy if vCPUs are running, fixing
the above issues also makes it trivial to ensure certain behavior is
deterministic, e.g. KVM can provide deterministic behavior for MSRs with
identical settings in the old and new filters. An atomic update of the
filter also prevents KVM from getting into a half-baked state, e.g. if
installing a filter fails, the existing approach would leave the filter
in a half-baked state, having already committed whatever bits of the
filter were already processed.
[*] https://lkml.kernel.org/r/20210312083157.25403-1-yaoyuan0329os@gmail.com
Fixes: 1a155254ff93 ("KVM: x86: Introduce MSR filtering")
Cc: stable@vger.kernel.org
Cc: Alexander Graf <graf@amazon.com>
Reported-by: Yuan Yao <yaoyuan0329os@gmail.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210316184436.2544875-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-03-16 18:44:33 +00:00
|
|
|
bool bus_lock_detection_enabled;
|
|
|
|
|
2020-09-25 14:34:16 +00:00
|
|
|
/* Deflect RDMSR and WRMSR to user space when they trigger a #GP */
|
|
|
|
u32 user_space_msr_mask;
|
KVM: x86: Protect userspace MSR filter with SRCU, and set atomically-ish
Fix a plethora of issues with MSR filtering by installing the resulting
filter as an atomic bundle instead of updating the live filter one range
at a time. The KVM_X86_SET_MSR_FILTER ioctl() isn't truly atomic, as
the hardware MSR bitmaps won't be updated until the next VM-Enter, but
the relevant software struct is atomically updated, which is what KVM
really needs.
Similar to the approach used for modifying memslots, make arch.msr_filter
a SRCU-protected pointer, do all the work configuring the new filter
outside of kvm->lock, and then acquire kvm->lock only when the new filter
has been vetted and created. That way vCPU readers either see the old
filter or the new filter in their entirety, not some half-baked state.
Yuan Yao pointed out a use-after-free in ksm_msr_allowed() due to a
TOCTOU bug, but that's just the tip of the iceberg...
- Nothing is __rcu annotated, making it nigh impossible to audit the
code for correctness.
- kvm_add_msr_filter() has an unpaired smp_wmb(). Violation of kernel
coding style aside, the lack of a smb_rmb() anywhere casts all code
into doubt.
- kvm_clear_msr_filter() has a double free TOCTOU bug, as it grabs
count before taking the lock.
- kvm_clear_msr_filter() also has memory leak due to the same TOCTOU bug.
The entire approach of updating the live filter is also flawed. While
installing a new filter is inherently racy if vCPUs are running, fixing
the above issues also makes it trivial to ensure certain behavior is
deterministic, e.g. KVM can provide deterministic behavior for MSRs with
identical settings in the old and new filters. An atomic update of the
filter also prevents KVM from getting into a half-baked state, e.g. if
installing a filter fails, the existing approach would leave the filter
in a half-baked state, having already committed whatever bits of the
filter were already processed.
[*] https://lkml.kernel.org/r/20210312083157.25403-1-yaoyuan0329os@gmail.com
Fixes: 1a155254ff93 ("KVM: x86: Introduce MSR filtering")
Cc: stable@vger.kernel.org
Cc: Alexander Graf <graf@amazon.com>
Reported-by: Yuan Yao <yaoyuan0329os@gmail.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210316184436.2544875-2-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-03-16 18:44:33 +00:00
|
|
|
struct kvm_x86_msr_filter __rcu *msr_filter;
|
2020-11-06 09:03:14 +00:00
|
|
|
|
2021-04-12 04:21:39 +00:00
|
|
|
/* Guest can access the SGX PROVISIONKEY. */
|
|
|
|
bool sgx_provisioning_allowed;
|
|
|
|
|
2021-03-05 19:11:23 +00:00
|
|
|
struct kvm_pmu_event_filter __rcu *pmu_event_filter;
|
2019-11-04 19:26:00 +00:00
|
|
|
struct task_struct *nx_lpage_recovery_thread;
|
2020-10-14 18:26:43 +00:00
|
|
|
|
2021-02-06 14:53:33 +00:00
|
|
|
#ifdef CONFIG_X86_64
|
2020-10-14 18:26:43 +00:00
|
|
|
/*
|
|
|
|
* Whether the TDP MMU is enabled for this VM. This contains a
|
|
|
|
* snapshot of the TDP MMU module parameter from when the VM was
|
|
|
|
* created and remains unchanged for the life of the VM. If this is
|
|
|
|
* true, TDP MMU handler functions will run for various MMU
|
|
|
|
* operations.
|
|
|
|
*/
|
|
|
|
bool tdp_mmu_enabled;
|
2020-10-14 18:26:51 +00:00
|
|
|
|
2021-01-07 00:19:35 +00:00
|
|
|
/*
|
2021-04-01 23:37:31 +00:00
|
|
|
* List of struct kvm_mmu_pages being used as roots.
|
2021-01-07 00:19:35 +00:00
|
|
|
* All struct kvm_mmu_pages in the list should have
|
|
|
|
* tdp_mmu_page set.
|
2021-04-01 23:37:31 +00:00
|
|
|
*
|
|
|
|
* For reads, this list is protected by:
|
|
|
|
* the MMU lock in read mode + RCU or
|
|
|
|
* the MMU lock in write mode
|
|
|
|
*
|
|
|
|
* For writes, this list is protected by:
|
|
|
|
* the MMU lock in read mode + the tdp_mmu_pages_lock or
|
|
|
|
* the MMU lock in write mode
|
|
|
|
*
|
|
|
|
* Roots will remain in the list until their tdp_mmu_root_count
|
|
|
|
* drops to zero, at which point the thread that decremented the
|
|
|
|
* count to zero should removed the root from the list and clean
|
|
|
|
* it up, freeing the root after an RCU grace period.
|
2021-01-07 00:19:35 +00:00
|
|
|
*/
|
2020-10-14 18:26:44 +00:00
|
|
|
struct list_head tdp_mmu_roots;
|
2021-01-07 00:19:35 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* List of struct kvmp_mmu_pages not being used as roots.
|
|
|
|
* All struct kvm_mmu_pages in the list should have
|
2021-04-01 23:37:31 +00:00
|
|
|
* tdp_mmu_page set and a tdp_mmu_root_count of 0.
|
2021-01-07 00:19:35 +00:00
|
|
|
*/
|
2020-10-14 18:26:51 +00:00
|
|
|
struct list_head tdp_mmu_pages;
|
2021-02-02 18:57:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Protects accesses to the following fields when the MMU lock
|
|
|
|
* is held in read mode:
|
2021-04-01 23:37:31 +00:00
|
|
|
* - tdp_mmu_roots (above)
|
2021-02-02 18:57:26 +00:00
|
|
|
* - tdp_mmu_pages (above)
|
|
|
|
* - the link field of struct kvm_mmu_pages used by the TDP MMU
|
|
|
|
* - lpage_disallowed_mmu_pages
|
|
|
|
* - the lpage_disallowed_link field of struct kvm_mmu_pages used
|
|
|
|
* by the TDP MMU
|
|
|
|
* It is acceptable, but not necessary, to acquire this lock when
|
|
|
|
* the thread holds the MMU lock in write mode.
|
|
|
|
*/
|
|
|
|
spinlock_t tdp_mmu_pages_lock;
|
2021-02-06 14:53:33 +00:00
|
|
|
#endif /* CONFIG_X86_64 */
|
2021-05-18 17:34:12 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If set, rmaps have been allocated for all memslots and should be
|
|
|
|
* allocated for any newly created or modified memslots.
|
|
|
|
*/
|
|
|
|
bool memslots_have_rmaps;
|
2007-12-14 01:54:20 +00:00
|
|
|
};
|
|
|
|
|
2007-12-14 02:23:23 +00:00
|
|
|
struct kvm_vm_stat {
|
2016-08-02 04:03:22 +00:00
|
|
|
ulong mmu_shadow_zapped;
|
|
|
|
ulong mmu_pte_write;
|
|
|
|
ulong mmu_pde_zapped;
|
|
|
|
ulong mmu_flooded;
|
|
|
|
ulong mmu_recycled;
|
|
|
|
ulong mmu_cache_miss;
|
|
|
|
ulong mmu_unsync;
|
|
|
|
ulong remote_tlb_flush;
|
|
|
|
ulong lpages;
|
2019-11-04 11:22:02 +00:00
|
|
|
ulong nx_lpage_splits;
|
2016-12-20 23:25:57 +00:00
|
|
|
ulong max_mmu_page_hash_collisions;
|
2007-12-14 02:23:23 +00:00
|
|
|
};
|
|
|
|
|
2007-12-14 01:49:26 +00:00
|
|
|
struct kvm_vcpu_stat {
|
2016-08-02 04:03:22 +00:00
|
|
|
u64 pf_fixed;
|
|
|
|
u64 pf_guest;
|
|
|
|
u64 tlb_flush;
|
|
|
|
u64 invlpg;
|
|
|
|
|
|
|
|
u64 exits;
|
|
|
|
u64 io_exits;
|
|
|
|
u64 mmio_exits;
|
|
|
|
u64 signal_exits;
|
|
|
|
u64 irq_window_exits;
|
|
|
|
u64 nmi_window_exits;
|
x86/KVM/VMX: Add L1D flush logic
Add the logic for flushing L1D on VMENTER. The flush depends on the static
key being enabled and the new l1tf_flush_l1d flag being set.
The flags is set:
- Always, if the flush module parameter is 'always'
- Conditionally at:
- Entry to vcpu_run(), i.e. after executing user space
- From the sched_in notifier, i.e. when switching to a vCPU thread.
- From vmexit handlers which are considered unsafe, i.e. where
sensitive data can be brought into L1D:
- The emulator, which could be a good target for other speculative
execution-based threats,
- The MMU, which can bring host page tables in the L1 cache.
- External interrupts
- Nested operations that require the MMU (see above). That is
vmptrld, vmptrst, vmclear,vmwrite,vmread.
- When handling invept,invvpid
[ tglx: Split out from combo patch and reduced to a single flag ]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2018-07-02 11:07:14 +00:00
|
|
|
u64 l1d_flush;
|
2016-08-02 04:03:22 +00:00
|
|
|
u64 halt_exits;
|
|
|
|
u64 halt_successful_poll;
|
|
|
|
u64 halt_attempted_poll;
|
|
|
|
u64 halt_poll_invalid;
|
|
|
|
u64 halt_wakeup;
|
|
|
|
u64 request_irq_exits;
|
|
|
|
u64 irq_exits;
|
|
|
|
u64 host_state_reload;
|
|
|
|
u64 fpu_reload;
|
|
|
|
u64 insn_emulation;
|
|
|
|
u64 insn_emulation_fail;
|
|
|
|
u64 hypercalls;
|
|
|
|
u64 irq_injections;
|
|
|
|
u64 nmi_injections;
|
2016-12-17 15:05:19 +00:00
|
|
|
u64 req_event;
|
2020-05-08 18:22:40 +00:00
|
|
|
u64 halt_poll_success_ns;
|
|
|
|
u64 halt_poll_fail_ns;
|
2021-03-05 22:57:47 +00:00
|
|
|
u64 nested_run;
|
2021-04-09 04:18:30 +00:00
|
|
|
u64 directed_yield_attempted;
|
|
|
|
u64 directed_yield_successful;
|
2007-12-14 01:49:26 +00:00
|
|
|
};
|
2007-12-13 15:50:52 +00:00
|
|
|
|
2011-04-04 10:39:27 +00:00
|
|
|
struct x86_instruction_info;
|
|
|
|
|
2012-11-29 20:42:12 +00:00
|
|
|
struct msr_data {
|
|
|
|
bool host_initiated;
|
|
|
|
u32 index;
|
|
|
|
u64 data;
|
|
|
|
};
|
|
|
|
|
2014-12-17 17:17:20 +00:00
|
|
|
struct kvm_lapic_irq {
|
|
|
|
u32 vector;
|
2015-04-21 12:57:05 +00:00
|
|
|
u16 delivery_mode;
|
|
|
|
u16 dest_mode;
|
|
|
|
bool level;
|
|
|
|
u16 trig_mode;
|
2014-12-17 17:17:20 +00:00
|
|
|
u32 shorthand;
|
|
|
|
u32 dest_id;
|
2015-03-19 01:26:03 +00:00
|
|
|
bool msi_redir_hint;
|
2014-12-17 17:17:20 +00:00
|
|
|
};
|
|
|
|
|
2019-12-04 19:07:18 +00:00
|
|
|
static inline u16 kvm_lapic_irq_dest_mode(bool dest_mode_logical)
|
|
|
|
{
|
|
|
|
return dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL;
|
|
|
|
}
|
|
|
|
|
2007-11-19 06:40:47 +00:00
|
|
|
struct kvm_x86_ops {
|
2014-08-28 13:13:03 +00:00
|
|
|
int (*hardware_enable)(void);
|
|
|
|
void (*hardware_disable)(void);
|
2020-03-21 20:26:01 +00:00
|
|
|
void (*hardware_unsetup)(void);
|
2007-12-26 11:57:04 +00:00
|
|
|
bool (*cpu_has_accelerated_tpr)(void);
|
2020-12-10 17:10:00 +00:00
|
|
|
bool (*has_emulated_msr)(struct kvm *kvm, u32 index);
|
2020-07-09 04:34:25 +00:00
|
|
|
void (*vcpu_after_set_cpuid)(struct kvm_vcpu *vcpu);
|
2007-11-19 06:40:47 +00:00
|
|
|
|
2020-01-27 00:41:13 +00:00
|
|
|
unsigned int vm_size;
|
2016-05-04 19:09:42 +00:00
|
|
|
int (*vm_init)(struct kvm *kvm);
|
|
|
|
void (*vm_destroy)(struct kvm *kvm);
|
|
|
|
|
2007-11-19 06:40:47 +00:00
|
|
|
/* Create, but do not attach this VCPU */
|
2019-12-18 21:54:55 +00:00
|
|
|
int (*vcpu_create)(struct kvm_vcpu *vcpu);
|
2007-11-19 06:40:47 +00:00
|
|
|
void (*vcpu_free)(struct kvm_vcpu *vcpu);
|
KVM: x86: INIT and reset sequences are different
x86 architecture defines differences between the reset and INIT sequences.
INIT does not initialize the FPU (including MMX, XMM, YMM, etc.), TSC, PMU,
MSRs (in general), MTRRs machine-check, APIC ID, APIC arbitration ID and BSP.
References (from Intel SDM):
"If the MP protocol has completed and a BSP is chosen, subsequent INITs (either
to a specific processor or system wide) do not cause the MP protocol to be
repeated." [8.4.2: MP Initialization Protocol Requirements and Restrictions]
[Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT]
"If the processor is reset by asserting the INIT# pin, the x87 FPU state is not
changed." [9.2: X87 FPU INITIALIZATION]
"The state of the local APIC following an INIT reset is the same as it is after
a power-up or hardware reset, except that the APIC ID and arbitration ID
registers are not affected." [10.4.7.3: Local APIC State After an INIT Reset
("Wait-for-SIPI" State)]
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Message-Id: <1428924848-28212-1-git-send-email-namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-13 11:34:08 +00:00
|
|
|
void (*vcpu_reset)(struct kvm_vcpu *vcpu, bool init_event);
|
2007-11-19 06:40:47 +00:00
|
|
|
|
|
|
|
void (*prepare_guest_switch)(struct kvm_vcpu *vcpu);
|
|
|
|
void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu);
|
|
|
|
void (*vcpu_put)(struct kvm_vcpu *vcpu);
|
|
|
|
|
2020-07-10 15:48:06 +00:00
|
|
|
void (*update_exception_bitmap)(struct kvm_vcpu *vcpu);
|
2015-04-08 13:30:38 +00:00
|
|
|
int (*get_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
|
2012-11-29 20:42:12 +00:00
|
|
|
int (*set_msr)(struct kvm_vcpu *vcpu, struct msr_data *msr);
|
2007-11-19 06:40:47 +00:00
|
|
|
u64 (*get_segment_base)(struct kvm_vcpu *vcpu, int seg);
|
|
|
|
void (*get_segment)(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_segment *var, int seg);
|
2008-03-24 17:38:34 +00:00
|
|
|
int (*get_cpl)(struct kvm_vcpu *vcpu);
|
2007-11-19 06:40:47 +00:00
|
|
|
void (*set_segment)(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_segment *var, int seg);
|
|
|
|
void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
|
|
|
|
void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
|
2020-10-07 01:44:15 +00:00
|
|
|
bool (*is_valid_cr4)(struct kvm_vcpu *vcpu, unsigned long cr0);
|
|
|
|
void (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
|
2020-10-01 11:29:53 +00:00
|
|
|
int (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
|
2010-02-16 08:51:48 +00:00
|
|
|
void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
|
|
|
|
void (*set_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
|
|
|
|
void (*get_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
|
|
|
|
void (*set_gdt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt);
|
2014-02-21 09:17:24 +00:00
|
|
|
void (*sync_dirty_debug_regs)(struct kvm_vcpu *vcpu);
|
2010-04-13 07:05:23 +00:00
|
|
|
void (*set_dr7)(struct kvm_vcpu *vcpu, unsigned long value);
|
2008-06-27 17:58:02 +00:00
|
|
|
void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
|
2007-11-19 06:40:47 +00:00
|
|
|
unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
|
|
|
|
void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
|
|
|
|
|
2020-03-20 21:28:18 +00:00
|
|
|
void (*tlb_flush_all)(struct kvm_vcpu *vcpu);
|
2020-03-20 21:28:20 +00:00
|
|
|
void (*tlb_flush_current)(struct kvm_vcpu *vcpu);
|
2018-07-19 08:40:17 +00:00
|
|
|
int (*tlb_remote_flush)(struct kvm *kvm);
|
2018-12-06 13:21:04 +00:00
|
|
|
int (*tlb_remote_flush_with_range)(struct kvm *kvm,
|
|
|
|
struct kvm_tlb_range *range);
|
2007-11-19 06:40:47 +00:00
|
|
|
|
2018-06-29 20:10:05 +00:00
|
|
|
/*
|
|
|
|
* Flush any TLB entries associated with the given GVA.
|
|
|
|
* Does not need to flush GPA->HPA mappings.
|
|
|
|
* Can potentially get non-canonical addresses through INVLPGs, which
|
|
|
|
* the implementation may choose to ignore if appropriate.
|
|
|
|
*/
|
|
|
|
void (*tlb_flush_gva)(struct kvm_vcpu *vcpu, gva_t addr);
|
2007-11-19 06:40:47 +00:00
|
|
|
|
KVM: x86: Move "flush guest's TLB" logic to separate kvm_x86_ops hook
Add a dedicated hook to handle flushing TLB entries on behalf of the
guest, i.e. for a paravirtualized TLB flush, and use it directly instead
of bouncing through kvm_vcpu_flush_tlb().
For VMX, change the effective implementation implementation to never do
INVEPT and flush only the current context, i.e. to always flush via
INVVPID(SINGLE_CONTEXT). The INVEPT performed by __vmx_flush_tlb() when
@invalidate_gpa=false and enable_vpid=0 is unnecessary, as it will only
flush guest-physical mappings; linear and combined mappings are flushed
by VM-Enter when VPID is disabled, and changes in the guest pages tables
do not affect guest-physical mappings.
When EPT and VPID are enabled, doing INVVPID is not required (by Intel's
architecture) to invalidate guest-physical mappings, i.e. TLB entries
that cache guest-physical mappings can live across INVVPID as the
mappings are associated with an EPTP, not a VPID. The intent of
@invalidate_gpa is to inform vmx_flush_tlb() that it must "invalidate
gpa mappings", i.e. do INVEPT and not simply INVVPID. Other than nested
VPID handling, which now calls vpid_sync_context() directly, the only
scenario where KVM can safely do INVVPID instead of INVEPT (when EPT is
enabled) is if KVM is flushing TLB entries from the guest's perspective,
i.e. is only required to invalidate linear mappings.
For SVM, flushing TLB entries from the guest's perspective can be done
by flushing the current ASID, as changes to the guest's page tables are
associated only with the current ASID.
Adding a dedicated ->tlb_flush_guest() paves the way toward removing
@invalidate_gpa, which is a potentially dangerous control flag as its
meaning is not exactly crystal clear, even for those who are familiar
with the subtleties of what mappings Intel CPUs are/aren't allowed to
keep across various invalidation scenarios.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Message-Id: <20200320212833.3507-15-sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-03-20 21:28:10 +00:00
|
|
|
/*
|
|
|
|
* Flush any TLB entries created by the guest. Like tlb_flush_gva(),
|
|
|
|
* does not need to flush GPA->HPA mappings.
|
|
|
|
*/
|
|
|
|
void (*tlb_flush_guest)(struct kvm_vcpu *vcpu);
|
|
|
|
|
2020-04-10 17:47:03 +00:00
|
|
|
enum exit_fastpath_completion (*run)(struct kvm_vcpu *vcpu);
|
2019-11-21 03:17:11 +00:00
|
|
|
int (*handle_exit)(struct kvm_vcpu *vcpu,
|
|
|
|
enum exit_fastpath_completion exit_fastpath);
|
x86: kvm: svm: propagate errors from skip_emulated_instruction()
On AMD, kvm_x86_ops->skip_emulated_instruction(vcpu) can, in theory,
fail: in !nrips case we call kvm_emulate_instruction(EMULTYPE_SKIP).
Currently, we only do printk(KERN_DEBUG) when this happens and this
is not ideal. Propagate the error up the stack.
On VMX, skip_emulated_instruction() doesn't fail, we have two call
sites calling it explicitly: handle_exception_nmi() and
handle_task_switch(), we can just ignore the result.
On SVM, we also have two explicit call sites:
svm_queue_exception() and it seems we don't need to do anything there as
we check if RIP was advanced or not. In task_switch_interception(),
however, we are better off not proceeding to kvm_task_switch() in case
skip_emulated_instruction() failed.
Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-08-13 13:53:30 +00:00
|
|
|
int (*skip_emulated_instruction)(struct kvm_vcpu *vcpu);
|
2020-02-07 10:36:07 +00:00
|
|
|
void (*update_emulated_instruction)(struct kvm_vcpu *vcpu);
|
2009-05-12 20:21:05 +00:00
|
|
|
void (*set_interrupt_shadow)(struct kvm_vcpu *vcpu, int mask);
|
2014-05-20 12:29:47 +00:00
|
|
|
u32 (*get_interrupt_shadow)(struct kvm_vcpu *vcpu);
|
2007-11-19 06:40:47 +00:00
|
|
|
void (*patch_hypercall)(struct kvm_vcpu *vcpu,
|
|
|
|
unsigned char *hypercall_addr);
|
2009-05-11 10:35:50 +00:00
|
|
|
void (*set_irq)(struct kvm_vcpu *vcpu);
|
2009-04-21 14:45:08 +00:00
|
|
|
void (*set_nmi)(struct kvm_vcpu *vcpu);
|
2017-07-14 01:30:39 +00:00
|
|
|
void (*queue_exception)(struct kvm_vcpu *vcpu);
|
2010-07-20 12:06:17 +00:00
|
|
|
void (*cancel_injection)(struct kvm_vcpu *vcpu);
|
2020-05-22 15:21:49 +00:00
|
|
|
int (*interrupt_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
|
|
|
|
int (*nmi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
|
2009-11-12 00:04:25 +00:00
|
|
|
bool (*get_nmi_mask)(struct kvm_vcpu *vcpu);
|
|
|
|
void (*set_nmi_mask)(struct kvm_vcpu *vcpu, bool masked);
|
2014-03-07 19:03:15 +00:00
|
|
|
void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
|
|
|
|
void (*enable_irq_window)(struct kvm_vcpu *vcpu);
|
2009-04-21 14:45:08 +00:00
|
|
|
void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
|
2019-11-14 20:15:10 +00:00
|
|
|
bool (*check_apicv_inhibit_reasons)(ulong bit);
|
2019-11-14 20:15:11 +00:00
|
|
|
void (*pre_update_apicv_exec_ctrl)(struct kvm *kvm, bool activate);
|
2015-11-10 12:36:33 +00:00
|
|
|
void (*refresh_apicv_exec_ctrl)(struct kvm_vcpu *vcpu);
|
2013-01-25 02:18:51 +00:00
|
|
|
void (*hwapic_irr_update)(struct kvm_vcpu *vcpu, int max_irr);
|
2016-05-10 15:01:23 +00:00
|
|
|
void (*hwapic_isr_update)(struct kvm_vcpu *vcpu, int isr);
|
2018-09-04 07:56:52 +00:00
|
|
|
bool (*guest_apic_has_interrupt)(struct kvm_vcpu *vcpu);
|
2015-11-10 12:36:32 +00:00
|
|
|
void (*load_eoi_exitmap)(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap);
|
2018-05-09 20:56:05 +00:00
|
|
|
void (*set_virtual_apic_mode)(struct kvm_vcpu *vcpu);
|
2020-03-20 21:28:24 +00:00
|
|
|
void (*set_apic_access_page_addr)(struct kvm_vcpu *vcpu);
|
2020-02-20 17:22:05 +00:00
|
|
|
int (*deliver_posted_interrupt)(struct kvm_vcpu *vcpu, int vector);
|
2016-12-19 16:17:11 +00:00
|
|
|
int (*sync_pir_to_irr)(struct kvm_vcpu *vcpu);
|
2007-11-19 06:40:47 +00:00
|
|
|
int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
|
2018-03-20 19:17:19 +00:00
|
|
|
int (*set_identity_map_addr)(struct kvm *kvm, u64 ident_addr);
|
2009-04-27 12:35:42 +00:00
|
|
|
u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
|
2009-07-27 14:30:48 +00:00
|
|
|
|
KVM: x86: Get active PCID only when writing a CR3 value
Retrieve the active PCID only when writing a guest CR3 value, i.e. don't
get the PCID when using EPT or NPT. The PCID is especially problematic
for EPT as the bits have different meaning, and so the PCID and must be
manually stripped, which is annoying and unnecessary. And on VMX,
getting the active PCID also involves reading the guest's CR3 and
CR4.PCIDE, i.e. may add pointless VMREADs.
Opportunistically rename the pgd/pgd_level params to root_hpa and
root_level to better reflect their new roles. Keep the function names,
as "load the guest PGD" is still accurate/correct.
Last, and probably least, pass root_hpa as a hpa_t/u64 instead of an
unsigned long. The EPTP holds a 64-bit value, even in 32-bit mode, so
in theory EPT could support HIGHMEM for 32-bit KVM. Never mind that
doing so would require changing the MMU page allocators and reworking
the MMU to use kmap().
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210305183123.3978098-2-seanjc@google.com>
Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-03-05 18:31:13 +00:00
|
|
|
void (*load_mmu_pgd)(struct kvm_vcpu *vcpu, hpa_t root_hpa,
|
|
|
|
int root_level);
|
2020-03-05 08:52:50 +00:00
|
|
|
|
2010-06-30 04:25:15 +00:00
|
|
|
bool (*has_wbinvd_exit)(void);
|
|
|
|
|
2021-05-26 18:44:13 +00:00
|
|
|
u64 (*get_l2_tsc_offset)(struct kvm_vcpu *vcpu);
|
|
|
|
u64 (*get_l2_tsc_multiplier)(struct kvm_vcpu *vcpu);
|
2021-05-26 18:44:15 +00:00
|
|
|
void (*write_tsc_offset)(struct kvm_vcpu *vcpu, u64 offset);
|
2010-08-20 08:07:17 +00:00
|
|
|
|
2020-09-23 20:13:46 +00:00
|
|
|
/*
|
|
|
|
* Retrieve somewhat arbitrary exit information. Intended to be used
|
|
|
|
* only from within tracepoints to avoid VMREADs when tracing is off.
|
|
|
|
*/
|
|
|
|
void (*get_exit_info)(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
|
|
|
|
u32 *exit_int_info, u32 *exit_int_info_err_code);
|
2011-04-04 10:39:27 +00:00
|
|
|
|
|
|
|
int (*check_intercept)(struct kvm_vcpu *vcpu,
|
|
|
|
struct x86_instruction_info *info,
|
2020-02-18 23:29:42 +00:00
|
|
|
enum x86_intercept_stage stage,
|
|
|
|
struct x86_exception *exception);
|
2020-04-10 17:47:03 +00:00
|
|
|
void (*handle_exit_irqoff)(struct kvm_vcpu *vcpu);
|
2020-03-02 23:56:24 +00:00
|
|
|
|
KVM: VMX: use preemption timer to force immediate VMExit
A VMX preemption timer value of '0' is guaranteed to cause a VMExit
prior to the CPU executing any instructions in the guest. Use the
preemption timer (if it's supported) to trigger immediate VMExit
in place of the current method of sending a self-IPI. This ensures
that pending VMExit injection to L1 occurs prior to executing any
instructions in the guest (regardless of nesting level).
When deferring VMExit injection, KVM generates an immediate VMExit
from the (possibly nested) guest by sending itself an IPI. Because
hardware interrupts are blocked prior to VMEnter and are unblocked
(in hardware) after VMEnter, this results in taking a VMExit(INTR)
before any guest instruction is executed. But, as this approach
relies on the IPI being received before VMEnter executes, it only
works as intended when KVM is running as L0. Because there are no
architectural guarantees regarding when IPIs are delivered, when
running nested the INTR may "arrive" long after L2 is running e.g.
L0 KVM doesn't force an immediate switch to L1 to deliver an INTR.
For the most part, this unintended delay is not an issue since the
events being injected to L1 also do not have architectural guarantees
regarding their timing. The notable exception is the VMX preemption
timer[1], which is architecturally guaranteed to cause a VMExit prior
to executing any instructions in the guest if the timer value is '0'
at VMEnter. Specifically, the delay in injecting the VMExit causes
the preemption timer KVM unit test to fail when run in a nested guest.
Note: this approach is viable even on CPUs with a broken preemption
timer, as broken in this context only means the timer counts at the
wrong rate. There are no known errata affecting timer value of '0'.
[1] I/O SMIs also have guarantees on when they arrive, but I have
no idea if/how those are emulated in KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Use a hook for SVM instead of leaving the default in x86.c - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-08-27 22:21:12 +00:00
|
|
|
void (*request_immediate_exit)(struct kvm_vcpu *vcpu);
|
2014-08-21 16:08:06 +00:00
|
|
|
|
|
|
|
void (*sched_in)(struct kvm_vcpu *kvm, int cpu);
|
2015-01-28 02:54:27 +00:00
|
|
|
|
|
|
|
/*
|
2021-02-13 00:50:10 +00:00
|
|
|
* Size of the CPU's dirty log buffer, i.e. VMX's PML buffer. A zero
|
|
|
|
* value indicates CPU dirty logging is unsupported or disabled.
|
2015-01-28 02:54:27 +00:00
|
|
|
*/
|
2021-02-13 00:50:09 +00:00
|
|
|
int cpu_dirty_log_size;
|
2021-02-13 00:50:12 +00:00
|
|
|
void (*update_cpu_dirty_logging)(struct kvm_vcpu *vcpu);
|
2017-05-05 19:25:13 +00:00
|
|
|
|
2015-06-19 13:45:05 +00:00
|
|
|
/* pmu operations of sub-arch */
|
|
|
|
const struct kvm_pmu_ops *pmu_ops;
|
2020-04-17 14:24:18 +00:00
|
|
|
const struct kvm_x86_nested_ops *nested_ops;
|
2015-09-18 14:29:51 +00:00
|
|
|
|
2015-09-18 14:29:55 +00:00
|
|
|
/*
|
|
|
|
* Architecture specific hooks for vCPU blocking due to
|
|
|
|
* HLT instruction.
|
|
|
|
* Returns for .pre_block():
|
|
|
|
* - 0 means continue to block the vCPU.
|
|
|
|
* - 1 means we cannot block the vCPU since some event
|
|
|
|
* happens during this period, such as, 'ON' bit in
|
|
|
|
* posted-interrupts descriptor is set.
|
|
|
|
*/
|
|
|
|
int (*pre_block)(struct kvm_vcpu *vcpu);
|
|
|
|
void (*post_block)(struct kvm_vcpu *vcpu);
|
2016-05-04 19:09:43 +00:00
|
|
|
|
|
|
|
void (*vcpu_blocking)(struct kvm_vcpu *vcpu);
|
|
|
|
void (*vcpu_unblocking)(struct kvm_vcpu *vcpu);
|
|
|
|
|
2015-09-18 14:29:51 +00:00
|
|
|
int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq,
|
|
|
|
uint32_t guest_irq, bool set);
|
2021-05-25 13:41:16 +00:00
|
|
|
void (*start_assignment)(struct kvm *kvm);
|
2016-05-04 19:09:49 +00:00
|
|
|
void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu);
|
2019-08-05 02:03:19 +00:00
|
|
|
bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu);
|
2016-06-13 21:20:01 +00:00
|
|
|
|
2019-04-16 20:32:46 +00:00
|
|
|
int (*set_hv_timer)(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc,
|
|
|
|
bool *expired);
|
2016-06-13 21:20:01 +00:00
|
|
|
void (*cancel_hv_timer)(struct kvm_vcpu *vcpu);
|
2016-06-22 06:59:56 +00:00
|
|
|
|
|
|
|
void (*setup_mce)(struct kvm_vcpu *vcpu);
|
2017-10-11 14:54:40 +00:00
|
|
|
|
2020-05-22 15:21:49 +00:00
|
|
|
int (*smi_allowed)(struct kvm_vcpu *vcpu, bool for_injection);
|
2017-10-11 14:54:40 +00:00
|
|
|
int (*pre_enter_smm)(struct kvm_vcpu *vcpu, char *smstate);
|
2019-04-02 15:03:09 +00:00
|
|
|
int (*pre_leave_smm)(struct kvm_vcpu *vcpu, const char *smstate);
|
2020-05-22 15:21:49 +00:00
|
|
|
void (*enable_smi_window)(struct kvm_vcpu *vcpu);
|
2017-12-04 16:57:26 +00:00
|
|
|
|
|
|
|
int (*mem_enc_op)(struct kvm *kvm, void __user *argp);
|
2017-12-04 16:57:26 +00:00
|
|
|
int (*mem_enc_reg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
|
|
|
|
int (*mem_enc_unreg_region)(struct kvm *kvm, struct kvm_enc_region *argp);
|
2021-04-08 22:32:14 +00:00
|
|
|
int (*vm_copy_enc_context_from)(struct kvm *kvm, unsigned int source_fd);
|
2018-02-21 19:39:51 +00:00
|
|
|
|
|
|
|
int (*get_msr_feature)(struct kvm_msr_entry *entry);
|
2018-10-16 16:50:01 +00:00
|
|
|
|
2020-09-15 23:27:02 +00:00
|
|
|
bool (*can_emulate_instruction)(struct kvm_vcpu *vcpu, void *insn, int insn_len);
|
2019-08-26 10:24:49 +00:00
|
|
|
|
|
|
|
bool (*apic_init_signal_blocked)(struct kvm_vcpu *vcpu);
|
2019-08-22 14:30:20 +00:00
|
|
|
int (*enable_direct_tlbflush)(struct kvm_vcpu *vcpu);
|
2020-05-08 20:36:43 +00:00
|
|
|
|
|
|
|
void (*migrate_timers)(struct kvm_vcpu *vcpu);
|
2020-09-25 14:34:17 +00:00
|
|
|
void (*msr_filter_changed)(struct kvm_vcpu *vcpu);
|
2020-12-14 15:26:51 +00:00
|
|
|
int (*complete_emulated_msr)(struct kvm_vcpu *vcpu, int err);
|
KVM: SVM: Add support for booting APs in an SEV-ES guest
Typically under KVM, an AP is booted using the INIT-SIPI-SIPI sequence,
where the guest vCPU register state is updated and then the vCPU is VMRUN
to begin execution of the AP. For an SEV-ES guest, this won't work because
the guest register state is encrypted.
Following the GHCB specification, the hypervisor must not alter the guest
register state, so KVM must track an AP/vCPU boot. Should the guest want
to park the AP, it must use the AP Reset Hold exit event in place of, for
example, a HLT loop.
First AP boot (first INIT-SIPI-SIPI sequence):
Execute the AP (vCPU) as it was initialized and measured by the SEV-ES
support. It is up to the guest to transfer control of the AP to the
proper location.
Subsequent AP boot:
KVM will expect to receive an AP Reset Hold exit event indicating that
the vCPU is being parked and will require an INIT-SIPI-SIPI sequence to
awaken it. When the AP Reset Hold exit event is received, KVM will place
the vCPU into a simulated HLT mode. Upon receiving the INIT-SIPI-SIPI
sequence, KVM will make the vCPU runnable. It is again up to the guest
to then transfer control of the AP to the proper location.
To differentiate between an actual HLT and an AP Reset Hold, a new MP
state is introduced, KVM_MP_STATE_AP_RESET_HOLD, which the vCPU is
placed in upon receiving the AP Reset Hold exit event. Additionally, to
communicate the AP Reset Hold exit event up to userspace (if needed), a
new exit reason is introduced, KVM_EXIT_AP_RESET_HOLD.
A new x86 ops function is introduced, vcpu_deliver_sipi_vector, in order
to accomplish AP booting. For VMX, vcpu_deliver_sipi_vector is set to the
original SIPI delivery function, kvm_vcpu_deliver_sipi_vector(). SVM adds
a new function that, for non SEV-ES guests, invokes the original SIPI
delivery function, kvm_vcpu_deliver_sipi_vector(), but for SEV-ES guests,
implements the logic above.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <e8fbebe8eb161ceaabdad7c01a5859a78b424d5e.1609791600.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-04 20:20:01 +00:00
|
|
|
|
|
|
|
void (*vcpu_deliver_sipi_vector)(struct kvm_vcpu *vcpu, u8 vector);
|
2007-11-19 06:40:47 +00:00
|
|
|
};
|
|
|
|
|
2020-04-17 14:24:18 +00:00
|
|
|
struct kvm_x86_nested_ops {
|
|
|
|
int (*check_events)(struct kvm_vcpu *vcpu);
|
2020-04-23 02:25:39 +00:00
|
|
|
bool (*hv_timer_pending)(struct kvm_vcpu *vcpu);
|
2021-03-02 17:45:14 +00:00
|
|
|
void (*triple_fault)(struct kvm_vcpu *vcpu);
|
2020-04-17 14:24:18 +00:00
|
|
|
int (*get_state)(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_nested_state __user *user_kvm_nested_state,
|
|
|
|
unsigned user_data_size);
|
|
|
|
int (*set_state)(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_nested_state __user *user_kvm_nested_state,
|
|
|
|
struct kvm_nested_state *kvm_state);
|
2020-09-22 10:53:57 +00:00
|
|
|
bool (*get_nested_state_pages)(struct kvm_vcpu *vcpu);
|
2020-06-22 21:58:32 +00:00
|
|
|
int (*write_log_dirty)(struct kvm_vcpu *vcpu, gpa_t l2_gpa);
|
2020-04-17 14:24:18 +00:00
|
|
|
|
|
|
|
int (*enable_evmcs)(struct kvm_vcpu *vcpu,
|
|
|
|
uint16_t *vmcs_version);
|
|
|
|
uint16_t (*get_evmcs_version)(struct kvm_vcpu *vcpu);
|
2007-11-19 06:40:47 +00:00
|
|
|
};
|
|
|
|
|
2020-03-21 20:25:56 +00:00
|
|
|
struct kvm_x86_init_ops {
|
|
|
|
int (*cpu_has_kvm_support)(void);
|
|
|
|
int (*disabled_by_bios)(void);
|
|
|
|
int (*check_processor_compatibility)(void);
|
|
|
|
int (*hardware_setup)(void);
|
|
|
|
|
|
|
|
struct kvm_x86_ops *runtime_ops;
|
|
|
|
};
|
|
|
|
|
2010-10-14 09:22:46 +00:00
|
|
|
struct kvm_arch_async_pf {
|
2010-10-14 09:22:53 +00:00
|
|
|
u32 token;
|
2010-10-14 09:22:46 +00:00
|
|
|
gfn_t gfn;
|
2010-12-07 02:35:25 +00:00
|
|
|
unsigned long cr3;
|
2010-11-12 06:49:55 +00:00
|
|
|
bool direct_map;
|
2010-10-14 09:22:46 +00:00
|
|
|
};
|
|
|
|
|
2021-05-04 17:17:31 +00:00
|
|
|
extern u32 __read_mostly kvm_nr_uret_msrs;
|
2020-03-02 23:57:06 +00:00
|
|
|
extern u64 __read_mostly host_efer;
|
2020-07-10 15:48:11 +00:00
|
|
|
extern bool __read_mostly allow_smaller_maxphyaddr;
|
2020-03-21 20:26:00 +00:00
|
|
|
extern struct kvm_x86_ops kvm_x86_ops;
|
2007-11-14 12:09:30 +00:00
|
|
|
|
2021-01-15 03:27:55 +00:00
|
|
|
#define KVM_X86_OP(func) \
|
|
|
|
DECLARE_STATIC_CALL(kvm_x86_##func, *(((struct kvm_x86_ops *)0)->func));
|
|
|
|
#define KVM_X86_OP_NULL KVM_X86_OP
|
|
|
|
#include <asm/kvm-x86-ops.h>
|
|
|
|
|
|
|
|
static inline void kvm_ops_static_call_update(void)
|
|
|
|
{
|
|
|
|
#define KVM_X86_OP(func) \
|
|
|
|
static_call_update(kvm_x86_##func, kvm_x86_ops.func);
|
|
|
|
#define KVM_X86_OP_NULL KVM_X86_OP
|
|
|
|
#include <asm/kvm-x86-ops.h>
|
|
|
|
}
|
|
|
|
|
2018-03-20 19:17:18 +00:00
|
|
|
#define __KVM_HAVE_ARCH_VM_ALLOC
|
|
|
|
static inline struct kvm *kvm_arch_alloc_vm(void)
|
|
|
|
{
|
2020-06-02 04:51:40 +00:00
|
|
|
return __vmalloc(kvm_x86_ops.vm_size, GFP_KERNEL_ACCOUNT | __GFP_ZERO);
|
2018-03-20 19:17:18 +00:00
|
|
|
}
|
2020-01-27 00:41:13 +00:00
|
|
|
void kvm_arch_free_vm(struct kvm *kvm);
|
2018-03-20 19:17:18 +00:00
|
|
|
|
2018-07-19 08:40:17 +00:00
|
|
|
#define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLB
|
|
|
|
static inline int kvm_arch_flush_remote_tlb(struct kvm *kvm)
|
|
|
|
{
|
2020-03-21 20:26:00 +00:00
|
|
|
if (kvm_x86_ops.tlb_remote_flush &&
|
2021-01-15 03:27:56 +00:00
|
|
|
!static_call(kvm_x86_tlb_remote_flush)(kvm))
|
2018-07-19 08:40:17 +00:00
|
|
|
return 0;
|
|
|
|
else
|
|
|
|
return -ENOTSUPP;
|
|
|
|
}
|
|
|
|
|
2007-11-19 07:24:28 +00:00
|
|
|
int kvm_mmu_module_init(void);
|
|
|
|
void kvm_mmu_module_exit(void);
|
|
|
|
|
|
|
|
void kvm_mmu_destroy(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_mmu_create(struct kvm_vcpu *vcpu);
|
2016-02-24 09:51:16 +00:00
|
|
|
void kvm_mmu_init_vm(struct kvm *kvm);
|
|
|
|
void kvm_mmu_uninit_vm(struct kvm *kvm);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2013-10-02 14:56:13 +00:00
|
|
|
void kvm_mmu_reset_context(struct kvm_vcpu *vcpu);
|
2015-01-28 02:54:26 +00:00
|
|
|
void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
|
2020-02-27 01:32:27 +00:00
|
|
|
struct kvm_memory_slot *memslot,
|
|
|
|
int start_level);
|
2015-04-03 07:40:25 +00:00
|
|
|
void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
|
2015-05-18 11:20:23 +00:00
|
|
|
const struct kvm_memory_slot *memslot);
|
2015-01-28 02:54:24 +00:00
|
|
|
void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
|
|
|
|
struct kvm_memory_slot *memslot);
|
2007-11-19 07:24:28 +00:00
|
|
|
void kvm_mmu_zap_all(struct kvm *kvm);
|
2019-02-05 20:54:17 +00:00
|
|
|
void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen);
|
2019-04-08 18:07:30 +00:00
|
|
|
unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm);
|
|
|
|
void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long kvm_nr_mmu_pages);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2010-09-10 15:30:57 +00:00
|
|
|
int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3);
|
2016-11-30 15:03:10 +00:00
|
|
|
bool pdptrs_changed(struct kvm_vcpu *vcpu);
|
2008-02-07 12:47:43 +00:00
|
|
|
|
2008-03-29 23:17:59 +00:00
|
|
|
int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
|
2008-03-02 12:06:05 +00:00
|
|
|
const void *val, int bytes);
|
2008-02-22 17:21:37 +00:00
|
|
|
|
2014-11-20 12:45:31 +00:00
|
|
|
struct kvm_irq_mask_notifier {
|
|
|
|
void (*func)(struct kvm_irq_mask_notifier *kimn, bool masked);
|
|
|
|
int irq;
|
|
|
|
struct hlist_node link;
|
|
|
|
};
|
|
|
|
|
|
|
|
void kvm_register_irq_mask_notifier(struct kvm *kvm, int irq,
|
|
|
|
struct kvm_irq_mask_notifier *kimn);
|
|
|
|
void kvm_unregister_irq_mask_notifier(struct kvm *kvm, int irq,
|
|
|
|
struct kvm_irq_mask_notifier *kimn);
|
|
|
|
void kvm_fire_mask_notifiers(struct kvm *kvm, unsigned irqchip, unsigned pin,
|
|
|
|
bool mask);
|
|
|
|
|
2008-02-22 17:21:37 +00:00
|
|
|
extern bool tdp_enabled;
|
2008-03-02 12:06:05 +00:00
|
|
|
|
2011-09-22 08:55:52 +00:00
|
|
|
u64 vcpu_tsc_khz(struct kvm_vcpu *vcpu);
|
|
|
|
|
2011-03-25 08:44:51 +00:00
|
|
|
/* control of guest tsc rate supported? */
|
|
|
|
extern bool kvm_has_tsc_control;
|
|
|
|
/* maximum supported tsc_khz for guests */
|
|
|
|
extern u32 kvm_max_guest_tsc_khz;
|
2015-10-20 07:39:01 +00:00
|
|
|
/* number of bits of the fractional part of the TSC scaling ratio */
|
|
|
|
extern u8 kvm_tsc_scaling_ratio_frac_bits;
|
|
|
|
/* maximum allowed value of TSC scaling ratio */
|
|
|
|
extern u64 kvm_max_tsc_scaling_ratio;
|
2016-06-13 21:19:59 +00:00
|
|
|
/* 1ull << kvm_tsc_scaling_ratio_frac_bits */
|
|
|
|
extern u64 kvm_default_tsc_scaling_ratio;
|
2020-11-06 09:03:14 +00:00
|
|
|
/* bus lock detection supported? */
|
|
|
|
extern bool kvm_has_bus_lock_exit;
|
2011-03-25 08:44:51 +00:00
|
|
|
|
2016-06-22 06:59:56 +00:00
|
|
|
extern u64 kvm_mce_cap_supported;
|
2011-03-25 08:44:51 +00:00
|
|
|
|
2019-08-27 21:40:40 +00:00
|
|
|
/*
|
|
|
|
* EMULTYPE_NO_DECODE - Set when re-emulating an instruction (after completing
|
|
|
|
* userspace I/O) to indicate that the emulation context
|
2021-03-18 14:28:01 +00:00
|
|
|
* should be reused as is, i.e. skip initialization of
|
2019-08-27 21:40:40 +00:00
|
|
|
* emulation context, instruction fetch and decode.
|
|
|
|
*
|
|
|
|
* EMULTYPE_TRAP_UD - Set when emulating an intercepted #UD from hardware.
|
|
|
|
* Indicates that only select instructions (tagged with
|
|
|
|
* EmulateOnUD) should be emulated (to minimize the emulator
|
|
|
|
* attack surface). See also EMULTYPE_TRAP_UD_FORCED.
|
|
|
|
*
|
|
|
|
* EMULTYPE_SKIP - Set when emulating solely to skip an instruction, i.e. to
|
|
|
|
* decode the instruction length. For use *only* by
|
2020-03-21 20:26:00 +00:00
|
|
|
* kvm_x86_ops.skip_emulated_instruction() implementations.
|
2019-08-27 21:40:40 +00:00
|
|
|
*
|
2020-02-18 23:03:08 +00:00
|
|
|
* EMULTYPE_ALLOW_RETRY_PF - Set when the emulator should resume the guest to
|
|
|
|
* retry native execution under certain conditions,
|
|
|
|
* Can only be set in conjunction with EMULTYPE_PF.
|
2019-08-27 21:40:40 +00:00
|
|
|
*
|
|
|
|
* EMULTYPE_TRAP_UD_FORCED - Set when emulating an intercepted #UD that was
|
|
|
|
* triggered by KVM's magic "force emulation" prefix,
|
|
|
|
* which is opt in via module param (off by default).
|
|
|
|
* Bypasses EmulateOnUD restriction despite emulating
|
|
|
|
* due to an intercepted #UD (see EMULTYPE_TRAP_UD).
|
|
|
|
* Used to test the full emulator from userspace.
|
|
|
|
*
|
|
|
|
* EMULTYPE_VMWARE_GP - Set when emulating an intercepted #GP for VMware
|
|
|
|
* backdoor emulation, which is opt in via module param.
|
2021-03-18 14:28:01 +00:00
|
|
|
* VMware backdoor emulation handles select instructions
|
2019-08-27 21:40:40 +00:00
|
|
|
* and reinjects the #GP for all other cases.
|
2020-02-18 23:03:08 +00:00
|
|
|
*
|
|
|
|
* EMULTYPE_PF - Set when emulating MMIO by way of an intercepted #PF, in which
|
|
|
|
* case the CR2/GPA value pass on the stack is valid.
|
2019-08-27 21:40:40 +00:00
|
|
|
*/
|
KVM: x86 emulator: Only allow VMCALL/VMMCALL trapped by #UD
When executing a test program called "crashme", we found the KVM guest cannot
survive more than ten seconds, then encounterd kernel panic. The basic concept
of "crashme" is generating random assembly code and trying to execute it.
After some fixes on emulator insn validity judgment, we found it's hard to
get the current emulator handle the invalid instructions correctly, for the
#UD trap for hypercall patching caused troubles. The problem is, if the opcode
itself was OK, but combination of opcode and modrm_reg was invalid, and one
operand of the opcode was memory (SrcMem or DstMem), the emulator will fetch
the memory operand first rather than checking the validity, and may encounter
an error there. For example, ".byte 0xfe, 0x34, 0xcd" has this problem.
In the patch, we simply check that if the invalid opcode wasn't vmcall/vmmcall,
then return from emulate_instruction() and inject a #UD to guest. With the
patch, the guest had been running for more than 12 hours.
Signed-off-by: Feng (Eric) Liu <eric.e.liu@intel.com>
Signed-off-by: Sheng Yang <sheng.yang@intel.com>
Signed-off-by: Avi Kivity <avi@qumranet.com>
2008-01-02 06:49:22 +00:00
|
|
|
#define EMULTYPE_NO_DECODE (1 << 0)
|
|
|
|
#define EMULTYPE_TRAP_UD (1 << 1)
|
2009-04-12 10:36:57 +00:00
|
|
|
#define EMULTYPE_SKIP (1 << 2)
|
2020-02-18 23:03:08 +00:00
|
|
|
#define EMULTYPE_ALLOW_RETRY_PF (1 << 3)
|
2019-08-27 21:40:32 +00:00
|
|
|
#define EMULTYPE_TRAP_UD_FORCED (1 << 4)
|
2019-08-27 21:40:31 +00:00
|
|
|
#define EMULTYPE_VMWARE_GP (1 << 5)
|
2020-02-18 23:03:08 +00:00
|
|
|
#define EMULTYPE_PF (1 << 6)
|
|
|
|
|
2018-08-23 20:56:53 +00:00
|
|
|
int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type);
|
|
|
|
int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
|
|
|
|
void *insn, int insn_len);
|
2018-08-23 20:56:47 +00:00
|
|
|
|
2008-01-31 13:57:37 +00:00
|
|
|
void kvm_enable_efer_bits(u64);
|
2013-04-20 08:52:36 +00:00
|
|
|
bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer);
|
2019-11-18 17:23:00 +00:00
|
|
|
int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data, bool host_initiated);
|
2019-09-05 21:22:54 +00:00
|
|
|
int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data);
|
|
|
|
int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data);
|
2019-09-05 21:22:55 +00:00
|
|
|
int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu);
|
2021-02-05 00:57:47 +00:00
|
|
|
int kvm_emulate_as_nop(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_emulate_invd(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_emulate_mwait(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_handle_invalid_op(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_emulate_monitor(struct kvm_vcpu *vcpu);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2018-03-08 16:57:27 +00:00
|
|
|
int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in);
|
2016-11-29 20:40:37 +00:00
|
|
|
int kvm_emulate_cpuid(struct kvm_vcpu *vcpu);
|
2007-11-19 07:24:28 +00:00
|
|
|
int kvm_emulate_halt(struct kvm_vcpu *vcpu);
|
2015-03-02 19:43:31 +00:00
|
|
|
int kvm_vcpu_halt(struct kvm_vcpu *vcpu);
|
KVM: SVM: Add support for booting APs in an SEV-ES guest
Typically under KVM, an AP is booted using the INIT-SIPI-SIPI sequence,
where the guest vCPU register state is updated and then the vCPU is VMRUN
to begin execution of the AP. For an SEV-ES guest, this won't work because
the guest register state is encrypted.
Following the GHCB specification, the hypervisor must not alter the guest
register state, so KVM must track an AP/vCPU boot. Should the guest want
to park the AP, it must use the AP Reset Hold exit event in place of, for
example, a HLT loop.
First AP boot (first INIT-SIPI-SIPI sequence):
Execute the AP (vCPU) as it was initialized and measured by the SEV-ES
support. It is up to the guest to transfer control of the AP to the
proper location.
Subsequent AP boot:
KVM will expect to receive an AP Reset Hold exit event indicating that
the vCPU is being parked and will require an INIT-SIPI-SIPI sequence to
awaken it. When the AP Reset Hold exit event is received, KVM will place
the vCPU into a simulated HLT mode. Upon receiving the INIT-SIPI-SIPI
sequence, KVM will make the vCPU runnable. It is again up to the guest
to then transfer control of the AP to the proper location.
To differentiate between an actual HLT and an AP Reset Hold, a new MP
state is introduced, KVM_MP_STATE_AP_RESET_HOLD, which the vCPU is
placed in upon receiving the AP Reset Hold exit event. Additionally, to
communicate the AP Reset Hold exit event up to userspace (if needed), a
new exit reason is introduced, KVM_EXIT_AP_RESET_HOLD.
A new x86 ops function is introduced, vcpu_deliver_sipi_vector, in order
to accomplish AP booting. For VMX, vcpu_deliver_sipi_vector is set to the
original SIPI delivery function, kvm_vcpu_deliver_sipi_vector(). SVM adds
a new function that, for non SEV-ES guests, invokes the original SIPI
delivery function, kvm_vcpu_deliver_sipi_vector(), but for SEV-ES guests,
implements the logic above.
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <e8fbebe8eb161ceaabdad7c01a5859a78b424d5e.1609791600.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-04 20:20:01 +00:00
|
|
|
int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu);
|
2010-06-30 04:25:15 +00:00
|
|
|
int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2008-05-27 08:18:46 +00:00
|
|
|
void kvm_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
|
2010-02-18 10:15:01 +00:00
|
|
|
int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector, int seg);
|
2014-11-24 13:35:24 +00:00
|
|
|
void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
|
2008-05-27 08:18:46 +00:00
|
|
|
|
2012-02-08 13:34:38 +00:00
|
|
|
int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
|
|
|
|
int reason, bool has_error_code, u32 error_code);
|
2008-03-24 21:14:53 +00:00
|
|
|
|
2020-12-10 17:10:01 +00:00
|
|
|
void kvm_free_guest_fpu(struct kvm_vcpu *vcpu);
|
|
|
|
|
2020-12-10 17:09:56 +00:00
|
|
|
void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0);
|
2020-12-10 17:09:57 +00:00
|
|
|
void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4);
|
2010-06-10 14:02:14 +00:00
|
|
|
int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
|
2010-06-10 14:02:16 +00:00
|
|
|
int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
|
2010-06-10 14:02:15 +00:00
|
|
|
int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
|
2010-12-21 10:12:00 +00:00
|
|
|
int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8);
|
2010-04-13 07:05:23 +00:00
|
|
|
int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val);
|
2021-02-03 08:42:41 +00:00
|
|
|
void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val);
|
2008-02-24 09:20:43 +00:00
|
|
|
unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu);
|
|
|
|
void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw);
|
2007-11-19 07:24:28 +00:00
|
|
|
void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l);
|
2021-02-05 00:57:46 +00:00
|
|
|
int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2015-04-08 13:30:38 +00:00
|
|
|
int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
|
2012-11-29 20:42:12 +00:00
|
|
|
int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2009-10-05 11:07:21 +00:00
|
|
|
unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu);
|
|
|
|
void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
|
2021-02-05 00:57:48 +00:00
|
|
|
int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu);
|
2009-10-05 11:07:21 +00:00
|
|
|
|
2007-11-25 11:41:11 +00:00
|
|
|
void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
|
|
|
|
void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
|
2020-05-05 11:33:20 +00:00
|
|
|
void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr, unsigned long payload);
|
2010-04-22 10:33:13 +00:00
|
|
|
void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr);
|
|
|
|
void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
|
2010-11-29 14:12:30 +00:00
|
|
|
void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
|
2020-03-20 21:28:01 +00:00
|
|
|
bool kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
|
|
|
|
struct x86_exception *fault);
|
2010-09-10 15:30:51 +00:00
|
|
|
int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
|
|
|
|
gfn_t gfn, void *data, int offset, int len,
|
|
|
|
u32 access);
|
2009-09-01 09:03:25 +00:00
|
|
|
bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
|
2014-10-02 22:10:05 +00:00
|
|
|
bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr);
|
2007-11-25 11:41:11 +00:00
|
|
|
|
2012-07-19 10:45:20 +00:00
|
|
|
static inline int __kvm_irq_line_state(unsigned long *irq_state,
|
|
|
|
int irq_source_id, int level)
|
|
|
|
{
|
|
|
|
/* Logical OR for level trig interrupt */
|
|
|
|
if (level)
|
|
|
|
__set_bit(irq_source_id, irq_state);
|
|
|
|
else
|
|
|
|
__clear_bit(irq_source_id, irq_state);
|
|
|
|
|
|
|
|
return !!(*irq_state);
|
|
|
|
}
|
|
|
|
|
2018-06-27 21:59:20 +00:00
|
|
|
#define KVM_MMU_ROOT_CURRENT BIT(0)
|
|
|
|
#define KVM_MMU_ROOT_PREVIOUS(i) BIT(1+i)
|
|
|
|
#define KVM_MMU_ROOTS_ALL (~0UL)
|
2018-06-27 21:59:17 +00:00
|
|
|
|
2012-07-19 10:45:20 +00:00
|
|
|
int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
|
|
|
|
void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
|
2008-10-06 05:48:45 +00:00
|
|
|
|
2008-05-15 01:52:48 +00:00
|
|
|
void kvm_inject_nmi(struct kvm_vcpu *vcpu);
|
|
|
|
|
2020-05-16 12:42:28 +00:00
|
|
|
void kvm_update_dr7(struct kvm_vcpu *vcpu);
|
|
|
|
|
2011-09-22 09:02:48 +00:00
|
|
|
int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn);
|
2007-11-19 07:24:28 +00:00
|
|
|
void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
|
2018-10-08 19:28:07 +00:00
|
|
|
void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
|
|
|
|
ulong roots_to_free);
|
2014-09-02 11:23:06 +00:00
|
|
|
gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
|
|
|
|
struct x86_exception *exception);
|
2010-11-22 15:53:26 +00:00
|
|
|
gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
|
|
|
|
struct x86_exception *exception);
|
|
|
|
gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
|
|
|
|
struct x86_exception *exception);
|
|
|
|
gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
|
|
|
|
struct x86_exception *exception);
|
|
|
|
gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
|
|
|
|
struct x86_exception *exception);
|
2007-11-19 07:24:28 +00:00
|
|
|
|
2019-11-14 20:15:05 +00:00
|
|
|
bool kvm_apicv_activated(struct kvm *kvm);
|
|
|
|
void kvm_apicv_init(struct kvm *kvm, bool enable);
|
2019-11-14 20:15:06 +00:00
|
|
|
void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu);
|
|
|
|
void kvm_request_apicv_update(struct kvm *kvm, bool activate,
|
|
|
|
unsigned long bit);
|
2015-11-10 12:36:33 +00:00
|
|
|
|
2007-11-19 07:24:28 +00:00
|
|
|
int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
|
|
|
|
|
2019-12-06 23:57:14 +00:00
|
|
|
int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
|
2010-12-21 10:12:07 +00:00
|
|
|
void *insn, int insn_len);
|
2008-09-23 16:18:35 +00:00
|
|
|
void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
|
2020-03-24 00:42:57 +00:00
|
|
|
void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
|
|
|
|
gva_t gva, hpa_t root_hpa);
|
2018-06-27 21:59:14 +00:00
|
|
|
void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid);
|
2020-03-20 21:28:32 +00:00
|
|
|
void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd, bool skip_tlb_flush,
|
2020-03-20 21:28:27 +00:00
|
|
|
bool skip_mmu_sync);
|
2007-10-20 07:34:38 +00:00
|
|
|
|
2020-07-16 03:41:22 +00:00
|
|
|
void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
|
|
|
|
int tdp_huge_page_level);
|
2008-02-07 12:47:41 +00:00
|
|
|
|
2008-07-10 13:53:33 +00:00
|
|
|
static inline u16 kvm_read_ldt(void)
|
2007-11-19 07:08:31 +00:00
|
|
|
{
|
|
|
|
u16 ldt;
|
|
|
|
asm("sldt %0" : "=g"(ldt));
|
|
|
|
return ldt;
|
|
|
|
}
|
|
|
|
|
2008-07-10 13:53:33 +00:00
|
|
|
static inline void kvm_load_ldt(u16 sel)
|
2007-11-19 07:08:31 +00:00
|
|
|
{
|
|
|
|
asm("lldt %0" : : "rm"(sel));
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_X86_64
|
|
|
|
static inline unsigned long read_msr(unsigned long msr)
|
|
|
|
{
|
|
|
|
u64 value;
|
|
|
|
|
|
|
|
rdmsrl(msr, value);
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static inline u32 get_rdx_init_val(void)
|
|
|
|
{
|
|
|
|
return 0x600; /* P6 family */
|
|
|
|
}
|
|
|
|
|
2007-11-25 12:12:03 +00:00
|
|
|
static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
|
|
|
|
{
|
|
|
|
kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
|
|
|
|
}
|
|
|
|
|
2007-11-19 07:08:31 +00:00
|
|
|
#define TSS_IOPB_BASE_OFFSET 0x66
|
|
|
|
#define TSS_BASE_SIZE 0x68
|
|
|
|
#define TSS_IOPB_SIZE (65536 / 8)
|
|
|
|
#define TSS_REDIRECTION_SIZE (256 / 8)
|
2008-03-23 08:02:34 +00:00
|
|
|
#define RMODE_TSS_SIZE \
|
|
|
|
(TSS_BASE_SIZE + TSS_REDIRECTION_SIZE + TSS_IOPB_SIZE + 1)
|
2007-12-03 22:15:26 +00:00
|
|
|
|
2008-03-24 21:14:53 +00:00
|
|
|
enum {
|
|
|
|
TASK_SWITCH_CALL = 0,
|
|
|
|
TASK_SWITCH_IRET = 1,
|
|
|
|
TASK_SWITCH_JMP = 2,
|
|
|
|
TASK_SWITCH_GATE = 3,
|
|
|
|
};
|
|
|
|
|
2008-11-25 19:17:04 +00:00
|
|
|
#define HF_GIF_MASK (1 << 0)
|
2009-04-21 14:45:08 +00:00
|
|
|
#define HF_NMI_MASK (1 << 3)
|
2009-05-11 10:35:52 +00:00
|
|
|
#define HF_IRET_MASK (1 << 4)
|
2010-11-29 16:51:47 +00:00
|
|
|
#define HF_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
|
2015-04-01 13:06:40 +00:00
|
|
|
#define HF_SMM_MASK (1 << 6)
|
|
|
|
#define HF_SMM_INSIDE_NMI_MASK (1 << 7)
|
2008-11-25 19:17:04 +00:00
|
|
|
|
2015-05-18 13:03:39 +00:00
|
|
|
#define __KVM_VCPU_MULTIPLE_ADDRESS_SPACE
|
|
|
|
#define KVM_ADDRESS_SPACE_NUM 2
|
|
|
|
|
|
|
|
#define kvm_arch_vcpu_memslots_id(vcpu) ((vcpu)->arch.hflags & HF_SMM_MASK ? 1 : 0)
|
|
|
|
#define kvm_memslots_for_spte_role(kvm, role) __kvm_memslots(kvm, (role).smm)
|
2008-11-25 19:17:04 +00:00
|
|
|
|
2019-07-19 20:41:06 +00:00
|
|
|
asmlinkage void kvm_spurious_fault(void);
|
2019-07-18 01:36:39 +00:00
|
|
|
|
2008-05-13 10:23:38 +00:00
|
|
|
/*
|
|
|
|
* Hardware virtualization extension instructions may fault if a
|
|
|
|
* reboot turns off virtualization while processes are running.
|
2019-07-18 01:36:39 +00:00
|
|
|
* Usually after catching the fault we just panic; during reboot
|
|
|
|
* instead the instruction is ignored.
|
2008-05-13 10:23:38 +00:00
|
|
|
*/
|
2019-07-19 20:41:09 +00:00
|
|
|
#define __kvm_handle_fault_on_reboot(insn) \
|
2019-07-18 01:36:39 +00:00
|
|
|
"666: \n\t" \
|
|
|
|
insn "\n\t" \
|
|
|
|
"jmp 668f \n\t" \
|
|
|
|
"667: \n\t" \
|
2020-07-08 19:51:57 +00:00
|
|
|
"1: \n\t" \
|
|
|
|
".pushsection .discard.instr_begin \n\t" \
|
|
|
|
".long 1b - . \n\t" \
|
|
|
|
".popsection \n\t" \
|
2019-07-18 01:36:39 +00:00
|
|
|
"call kvm_spurious_fault \n\t" \
|
2020-07-08 19:51:57 +00:00
|
|
|
"1: \n\t" \
|
|
|
|
".pushsection .discard.instr_end \n\t" \
|
|
|
|
".long 1b - . \n\t" \
|
|
|
|
".popsection \n\t" \
|
2019-07-18 01:36:39 +00:00
|
|
|
"668: \n\t" \
|
2019-07-19 20:41:10 +00:00
|
|
|
_ASM_EXTABLE(666b, 667b)
|
2008-05-13 10:23:38 +00:00
|
|
|
|
2008-07-25 14:24:52 +00:00
|
|
|
#define KVM_ARCH_WANT_MMU_NOTIFIER
|
2021-03-26 02:19:47 +00:00
|
|
|
|
2013-01-25 02:18:51 +00:00
|
|
|
int kvm_cpu_has_injectable_intr(struct kvm_vcpu *v);
|
2009-07-09 12:33:52 +00:00
|
|
|
int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
|
KVM: x86: Fix split-irqchip vs interrupt injection window request
kvm_cpu_accept_dm_intr and kvm_vcpu_ready_for_interrupt_injection are
a hodge-podge of conditions, hacked together to get something that
more or less works. But what is actually needed is much simpler;
in both cases the fundamental question is, do we have a place to stash
an interrupt if userspace does KVM_INTERRUPT?
In userspace irqchip mode, that is !vcpu->arch.interrupt.injected.
Currently kvm_event_needs_reinjection(vcpu) covers it, but it is
unnecessarily restrictive.
In split irqchip mode it's a bit more complicated, we need to check
kvm_apic_accept_pic_intr(vcpu) (the IRQ window exit is basically an INTACK
cycle and thus requires ExtINTs not to be masked) as well as
!pending_userspace_extint(vcpu). However, there is no need to
check kvm_event_needs_reinjection(vcpu), since split irqchip keeps
pending ExtINT state separate from event injection state, and checking
kvm_cpu_has_interrupt(vcpu) is wrong too since ExtINT has higher
priority than APIC interrupts. In fact the latter fixes a bug:
when userspace requests an IRQ window vmexit, an interrupt in the
local APIC can cause kvm_cpu_has_interrupt() to be true and thus
kvm_vcpu_ready_for_interrupt_injection() to return false. When this
happens, vcpu_run does not exit to userspace but the interrupt window
vmexits keep occurring. The VM loops without any hope of making progress.
Once we try to fix these with something like
return kvm_arch_interrupt_allowed(vcpu) &&
- !kvm_cpu_has_interrupt(vcpu) &&
- !kvm_event_needs_reinjection(vcpu) &&
- kvm_cpu_accept_dm_intr(vcpu);
+ (!lapic_in_kernel(vcpu)
+ ? !vcpu->arch.interrupt.injected
+ : (kvm_apic_accept_pic_intr(vcpu)
+ && !pending_userspace_extint(v)));
we realize two things. First, thanks to the previous patch the complex
conditional can reuse !kvm_cpu_has_extint(vcpu). Second, the interrupt
window request in vcpu_enter_guest()
bool req_int_win =
dm_request_for_irq_injection(vcpu) &&
kvm_cpu_accept_dm_intr(vcpu);
should be kept in sync with kvm_vcpu_ready_for_interrupt_injection():
it is unnecessary to ask the processor for an interrupt window
if we would not be able to return to userspace. Therefore,
kvm_cpu_accept_dm_intr(vcpu) is basically !kvm_cpu_has_extint(vcpu)
ANDed with the existing check for masked ExtINT. It all makes sense:
- we can accept an interrupt from userspace if there is a place
to stash it (and, for irqchip split, ExtINTs are not masked).
Interrupts from userspace _can_ be accepted even if right now
EFLAGS.IF=0.
- in order to tell userspace we will inject its interrupt ("IRQ
window open" i.e. kvm_vcpu_ready_for_interrupt_injection), both
KVM and the vCPU need to be ready to accept the interrupt.
... and this is what the patch implements.
Reported-by: David Woodhouse <dwmw@amazon.co.uk>
Analyzed-by: David Woodhouse <dwmw@amazon.co.uk>
Cc: stable@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Nikos Tsironis <ntsironis@arrikto.com>
Reviewed-by: David Woodhouse <dwmw@amazon.co.uk>
Tested-by: David Woodhouse <dwmw@amazon.co.uk>
2020-11-27 08:18:20 +00:00
|
|
|
int kvm_cpu_has_extint(struct kvm_vcpu *v);
|
2009-07-09 12:33:52 +00:00
|
|
|
int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
|
2009-07-09 12:33:53 +00:00
|
|
|
int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
|
KVM: x86: INIT and reset sequences are different
x86 architecture defines differences between the reset and INIT sequences.
INIT does not initialize the FPU (including MMX, XMM, YMM, etc.), TSC, PMU,
MSRs (in general), MTRRs machine-check, APIC ID, APIC arbitration ID and BSP.
References (from Intel SDM):
"If the MP protocol has completed and a BSP is chosen, subsequent INITs (either
to a specific processor or system wide) do not cause the MP protocol to be
repeated." [8.4.2: MP Initialization Protocol Requirements and Restrictions]
[Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT]
"If the processor is reset by asserting the INIT# pin, the x87 FPU state is not
changed." [9.2: X87 FPU INITIALIZATION]
"The state of the local APIC following an INIT reset is the same as it is after
a power-up or hardware reset, except that the APIC ID and arbitration ID
registers are not affected." [10.4.7.3: Local APIC State After an INIT Reset
("Wait-for-SIPI" State)]
Signed-off-by: Nadav Amit <namit@cs.technion.ac.il>
Message-Id: <1428924848-28212-1-git-send-email-namit@cs.technion.ac.il>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-04-13 11:34:08 +00:00
|
|
|
void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event);
|
2014-09-24 07:57:54 +00:00
|
|
|
void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu);
|
2008-07-25 14:24:52 +00:00
|
|
|
|
KVM: X86: Implement "send IPI" hypercall
Using hypercall to send IPIs by one vmexit instead of one by one for
xAPIC/x2APIC physical mode and one vmexit per-cluster for x2APIC cluster
mode. Intel guest can enter x2apic cluster mode when interrupt remmaping
is enabled in qemu, however, latest AMD EPYC still just supports xapic
mode which can get great improvement by Exit-less IPIs. This patchset
lets a guest send multicast IPIs, with at most 128 destinations per
hypercall in 64-bit mode and 64 vCPUs per hypercall in 32-bit mode.
Hardware: Xeon Skylake 2.5GHz, 2 sockets, 40 cores, 80 threads, the VM
is 80 vCPUs, IPI microbenchmark(https://lkml.org/lkml/2017/12/19/141):
x2apic cluster mode, vanilla
Dry-run: 0, 2392199 ns
Self-IPI: 6907514, 15027589 ns
Normal IPI: 223910476, 251301666 ns
Broadcast IPI: 0, 9282161150 ns
Broadcast lock: 0, 8812934104 ns
x2apic cluster mode, pv-ipi
Dry-run: 0, 2449341 ns
Self-IPI: 6720360, 15028732 ns
Normal IPI: 228643307, 255708477 ns
Broadcast IPI: 0, 7572293590 ns => 22% performance boost
Broadcast lock: 0, 8316124651 ns
x2apic physical mode, vanilla
Dry-run: 0, 3135933 ns
Self-IPI: 8572670, 17901757 ns
Normal IPI: 226444334, 255421709 ns
Broadcast IPI: 0, 19845070887 ns
Broadcast lock: 0, 19827383656 ns
x2apic physical mode, pv-ipi
Dry-run: 0, 2446381 ns
Self-IPI: 6788217, 15021056 ns
Normal IPI: 219454441, 249583458 ns
Broadcast IPI: 0, 7806540019 ns => 154% performance boost
Broadcast lock: 0, 9143618799 ns
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-07-23 06:39:54 +00:00
|
|
|
int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
|
2018-08-30 02:03:30 +00:00
|
|
|
unsigned long ipi_bitmap_high, u32 min,
|
KVM: X86: Implement "send IPI" hypercall
Using hypercall to send IPIs by one vmexit instead of one by one for
xAPIC/x2APIC physical mode and one vmexit per-cluster for x2APIC cluster
mode. Intel guest can enter x2apic cluster mode when interrupt remmaping
is enabled in qemu, however, latest AMD EPYC still just supports xapic
mode which can get great improvement by Exit-less IPIs. This patchset
lets a guest send multicast IPIs, with at most 128 destinations per
hypercall in 64-bit mode and 64 vCPUs per hypercall in 32-bit mode.
Hardware: Xeon Skylake 2.5GHz, 2 sockets, 40 cores, 80 threads, the VM
is 80 vCPUs, IPI microbenchmark(https://lkml.org/lkml/2017/12/19/141):
x2apic cluster mode, vanilla
Dry-run: 0, 2392199 ns
Self-IPI: 6907514, 15027589 ns
Normal IPI: 223910476, 251301666 ns
Broadcast IPI: 0, 9282161150 ns
Broadcast lock: 0, 8812934104 ns
x2apic cluster mode, pv-ipi
Dry-run: 0, 2449341 ns
Self-IPI: 6720360, 15028732 ns
Normal IPI: 228643307, 255708477 ns
Broadcast IPI: 0, 7572293590 ns => 22% performance boost
Broadcast lock: 0, 8316124651 ns
x2apic physical mode, vanilla
Dry-run: 0, 3135933 ns
Self-IPI: 8572670, 17901757 ns
Normal IPI: 226444334, 255421709 ns
Broadcast IPI: 0, 19845070887 ns
Broadcast lock: 0, 19827383656 ns
x2apic physical mode, pv-ipi
Dry-run: 0, 2446381 ns
Self-IPI: 6788217, 15021056 ns
Normal IPI: 219454441, 249583458 ns
Broadcast IPI: 0, 7806540019 ns => 154% performance boost
Broadcast lock: 0, 9143618799 ns
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Wanpeng Li <wanpengli@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-07-23 06:39:54 +00:00
|
|
|
unsigned long icr, int op_64_bit);
|
|
|
|
|
2021-05-04 17:17:32 +00:00
|
|
|
int kvm_add_user_return_msr(u32 msr);
|
2021-05-04 17:17:29 +00:00
|
|
|
int kvm_find_user_return_msr(u32 msr);
|
2020-09-23 18:03:55 +00:00
|
|
|
int kvm_set_user_return_msr(unsigned index, u64 val, u64 mask);
|
2009-09-07 08:12:18 +00:00
|
|
|
|
2021-05-04 17:17:33 +00:00
|
|
|
static inline bool kvm_is_supported_user_return_msr(u32 msr)
|
|
|
|
{
|
|
|
|
return kvm_find_user_return_msr(msr) >= 0;
|
|
|
|
}
|
|
|
|
|
2021-05-26 18:44:11 +00:00
|
|
|
u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc, u64 ratio);
|
2015-10-20 07:39:07 +00:00
|
|
|
u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc);
|
2021-05-26 18:44:14 +00:00
|
|
|
u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier);
|
|
|
|
u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier);
|
2015-10-20 07:39:03 +00:00
|
|
|
|
2014-11-02 09:54:45 +00:00
|
|
|
unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu);
|
2010-02-23 16:47:55 +00:00
|
|
|
bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip);
|
|
|
|
|
2016-01-07 14:05:10 +00:00
|
|
|
void kvm_make_mclock_inprogress_request(struct kvm *kvm);
|
|
|
|
void kvm_make_scan_ioapic_request(struct kvm *kvm);
|
2019-11-07 12:53:43 +00:00
|
|
|
void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
|
|
|
|
unsigned long *vcpu_bitmap);
|
2016-01-07 14:05:10 +00:00
|
|
|
|
2020-06-10 17:55:32 +00:00
|
|
|
bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
|
2010-10-14 09:22:46 +00:00
|
|
|
struct kvm_async_pf *work);
|
|
|
|
void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_async_pf *work);
|
2010-10-17 16:13:42 +00:00
|
|
|
void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu,
|
|
|
|
struct kvm_async_pf *work);
|
2020-05-25 14:41:21 +00:00
|
|
|
void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu);
|
2020-05-25 14:41:18 +00:00
|
|
|
bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu);
|
2010-10-14 09:22:46 +00:00
|
|
|
extern bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn);
|
|
|
|
|
KVM: x86: Add kvm_skip_emulated_instruction and use it.
kvm_skip_emulated_instruction calls both
kvm_x86_ops->skip_emulated_instruction and kvm_vcpu_check_singlestep,
skipping the emulated instruction and generating a trap if necessary.
Replacing skip_emulated_instruction calls with
kvm_skip_emulated_instruction is straightforward, except for:
- ICEBP, which is already inside a trap, so avoid triggering another trap.
- Instructions that can trigger exits to userspace, such as the IO insns,
MOVs to CR8, and HALT. If kvm_skip_emulated_instruction does trigger a
KVM_GUESTDBG_SINGLESTEP exit, and the handling code for
IN/OUT/MOV CR8/HALT also triggers an exit to userspace, the latter will
take precedence. The singlestep will be triggered again on the next
instruction, which is the current behavior.
- Task switch instructions which would require additional handling (e.g.
the task switch bit) and are instead left alone.
- Cases where VMLAUNCH/VMRESUME do not proceed to the next instruction,
which do not trigger singlestep traps as mentioned previously.
Signed-off-by: Kyle Huey <khuey@kylehuey.com>
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
2016-11-29 20:40:40 +00:00
|
|
|
int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu);
|
|
|
|
int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err);
|
KVM: VMX: use preemption timer to force immediate VMExit
A VMX preemption timer value of '0' is guaranteed to cause a VMExit
prior to the CPU executing any instructions in the guest. Use the
preemption timer (if it's supported) to trigger immediate VMExit
in place of the current method of sending a self-IPI. This ensures
that pending VMExit injection to L1 occurs prior to executing any
instructions in the guest (regardless of nesting level).
When deferring VMExit injection, KVM generates an immediate VMExit
from the (possibly nested) guest by sending itself an IPI. Because
hardware interrupts are blocked prior to VMEnter and are unblocked
(in hardware) after VMEnter, this results in taking a VMExit(INTR)
before any guest instruction is executed. But, as this approach
relies on the IPI being received before VMEnter executes, it only
works as intended when KVM is running as L0. Because there are no
architectural guarantees regarding when IPIs are delivered, when
running nested the INTR may "arrive" long after L2 is running e.g.
L0 KVM doesn't force an immediate switch to L1 to deliver an INTR.
For the most part, this unintended delay is not an issue since the
events being injected to L1 also do not have architectural guarantees
regarding their timing. The notable exception is the VMX preemption
timer[1], which is architecturally guaranteed to cause a VMExit prior
to executing any instructions in the guest if the timer value is '0'
at VMEnter. Specifically, the delay in injecting the VMExit causes
the preemption timer KVM unit test to fail when run in a nested guest.
Note: this approach is viable even on CPUs with a broken preemption
timer, as broken in this context only means the timer counts at the
wrong rate. There are no known errata affecting timer value of '0'.
[1] I/O SMIs also have guarantees on when they arrive, but I have
no idea if/how those are emulated in KVM.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
[Use a hook for SVM instead of leaving the default in x86.c - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-08-27 22:21:12 +00:00
|
|
|
void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu);
|
2010-12-21 10:12:01 +00:00
|
|
|
|
2011-11-10 12:57:22 +00:00
|
|
|
int kvm_is_in_guest(void);
|
|
|
|
|
2020-10-01 01:20:33 +00:00
|
|
|
void __user *__x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
|
|
|
|
u32 size);
|
2015-07-29 09:56:48 +00:00
|
|
|
bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu);
|
|
|
|
bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu);
|
2011-11-10 12:57:22 +00:00
|
|
|
|
2015-09-18 14:29:47 +00:00
|
|
|
bool kvm_intr_is_single_vcpu(struct kvm *kvm, struct kvm_lapic_irq *irq,
|
|
|
|
struct kvm_vcpu **dest_vcpu);
|
|
|
|
|
2016-07-12 20:09:27 +00:00
|
|
|
void kvm_set_msi_irq(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
|
2015-09-18 14:29:49 +00:00
|
|
|
struct kvm_lapic_irq *irq);
|
KVM/ARM Changes for v4.4-rc1
Includes a number of fixes for the arch-timer, introducing proper
level-triggered semantics for the arch-timers, a series of patches to
synchronously halt a guest (prerequisite for IRQ forwarding), some tracepoint
improvements, a tweak for the EL2 panic handlers, some more VGIC cleanups
getting rid of redundant state, and finally a stylistic change that gets rid of
some ctags warnings.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJWOhgAAAoJEEtpOizt6ddyKS8H/2ZHMTPjo6yChnrusNWy4Qbr
6laPDlzL+g45oMQRwNL7GnM1deRftaxvT2Wi+X84D/6Y/BD6MPds4HgtBfuWcSZ1
CyRJ0Ot/zrxenucSuJuOjq+a9gdizdAczkbB1MfYDULJH8fb6D+7RYLo3zgh4Xo4
pla3L9U6gSWe+YopBjZtZH43m3fwiwSM/v+uHOTIcXrsbR+fEgx/EFSKmA/DUCuo
P5cFO/ceUGu7nATCexu5V82TgR2hvurrsR7mqfwY8YcF6HRM+NEOoS29xWC77v5S
u/F08TKuKQLv0YTEFTyLETI/oEeuC0cHtrRQBNf4+9kXEOzKyXaae0wR/I6X2Ss=
=GMNk
-----END PGP SIGNATURE-----
Merge tag 'kvm-arm-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
KVM/ARM Changes for v4.4-rc1
Includes a number of fixes for the arch-timer, introducing proper
level-triggered semantics for the arch-timers, a series of patches to
synchronously halt a guest (prerequisite for IRQ forwarding), some tracepoint
improvements, a tweak for the EL2 panic handlers, some more VGIC cleanups
getting rid of redundant state, and finally a stylistic change that gets rid of
some ctags warnings.
Conflicts:
arch/x86/include/asm/kvm_host.h
2015-11-04 15:24:17 +00:00
|
|
|
|
2019-09-05 12:58:18 +00:00
|
|
|
static inline bool kvm_irq_is_postable(struct kvm_lapic_irq *irq)
|
|
|
|
{
|
|
|
|
/* We can only post Fixed and LowPrio IRQs */
|
2020-04-07 06:13:09 +00:00
|
|
|
return (irq->delivery_mode == APIC_DM_FIXED ||
|
|
|
|
irq->delivery_mode == APIC_DM_LOWEST);
|
2019-09-05 12:58:18 +00:00
|
|
|
}
|
|
|
|
|
2016-05-04 19:09:43 +00:00
|
|
|
static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2021-01-15 03:27:56 +00:00
|
|
|
static_call_cond(kvm_x86_vcpu_blocking)(vcpu);
|
2016-05-04 19:09:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu)
|
|
|
|
{
|
2021-01-15 03:27:56 +00:00
|
|
|
static_call_cond(kvm_x86_vcpu_unblocking)(vcpu);
|
2016-05-04 19:09:43 +00:00
|
|
|
}
|
|
|
|
|
2016-05-13 10:16:35 +00:00
|
|
|
static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
|
2015-08-27 14:41:15 +00:00
|
|
|
|
2016-06-15 22:23:45 +00:00
|
|
|
static inline int kvm_cpu_get_apicid(int mps_cpu)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_X86_LOCAL_APIC
|
2017-09-13 21:29:21 +00:00
|
|
|
return default_cpu_present_to_apicid(mps_cpu);
|
2016-06-15 22:23:45 +00:00
|
|
|
#else
|
|
|
|
WARN_ON_ONCE(1);
|
|
|
|
return BAD_APICID;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-10-11 14:54:45 +00:00
|
|
|
#define put_smstate(type, buf, offset, val) \
|
|
|
|
*(type *)((buf) + (offset) - 0x7e00) = val
|
|
|
|
|
2019-04-02 15:03:09 +00:00
|
|
|
#define GET_SMSTATE(type, buf, offset) \
|
|
|
|
(*(type *)((buf) + (offset) - 0x7e00))
|
|
|
|
|
2020-10-01 01:22:22 +00:00
|
|
|
int kvm_cpu_dirty_log_size(void);
|
|
|
|
|
2021-05-18 17:34:14 +00:00
|
|
|
int alloc_all_memslots_rmaps(struct kvm *kvm);
|
|
|
|
|
2008-10-23 05:26:29 +00:00
|
|
|
#endif /* _ASM_X86_KVM_HOST_H */
|