2019-05-19 13:51:31 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2013-11-13 00:51:23 +00:00
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/*
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* Hisilicon clock driver
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*
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* Copyright (c) 2012-2013 Hisilicon Limited.
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* Copyright (c) 2012-2013 Linaro Limited.
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*
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* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
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* Xin Li <li.xin@linaro.org>
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*/
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#include <linux/kernel.h>
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#include <linux/clkdev.h>
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2015-06-19 22:00:46 +00:00
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#include <linux/clk-provider.h>
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2013-11-13 00:51:23 +00:00
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include "clk.h"
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static DEFINE_SPINLOCK(hisi_clk_lock);
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2016-06-15 06:26:35 +00:00
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struct hisi_clock_data *hisi_clk_alloc(struct platform_device *pdev,
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int nr_clks)
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{
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struct hisi_clock_data *clk_data;
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struct resource *res;
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struct clk **clk_table;
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clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
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if (!clk_data)
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return NULL;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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clk: hisilicon: fix potential NULL dereference in hisi_clk_alloc()
platform_get_resource() may fail and return NULL, so we should
better check it's return value to avoid a NULL pointer dereference
a bit later in the code.
This is detected by Coccinelle semantic patch.
@@
expression pdev, res, n, t, e, e1, e2;
@@
res = platform_get_resource(pdev, t, n);
+ if (!res)
+ return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Fixes: 322269163a36 ("clk: hisilicon: add hisi_clk_alloc function.")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2018-03-20 14:19:34 +00:00
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if (!res)
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return NULL;
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2016-06-15 06:26:35 +00:00
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clk_data->base = devm_ioremap(&pdev->dev,
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res->start, resource_size(res));
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if (!clk_data->base)
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return NULL;
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2017-04-18 08:15:19 +00:00
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clk_table = devm_kmalloc_array(&pdev->dev, nr_clks,
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sizeof(*clk_table),
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GFP_KERNEL);
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2016-06-15 06:26:35 +00:00
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if (!clk_table)
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return NULL;
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clk_data->clk_data.clks = clk_table;
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clk_data->clk_data.clk_num = nr_clks;
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return clk_data;
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}
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EXPORT_SYMBOL_GPL(hisi_clk_alloc);
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2016-04-23 07:40:29 +00:00
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struct hisi_clock_data *hisi_clk_init(struct device_node *np,
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2013-12-24 13:38:26 +00:00
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int nr_clks)
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2013-11-13 00:51:23 +00:00
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{
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2013-12-24 13:38:26 +00:00
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struct hisi_clock_data *clk_data;
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struct clk **clk_table;
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void __iomem *base;
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2015-08-03 01:13:34 +00:00
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base = of_iomap(np, 0);
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if (!base) {
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pr_err("%s: failed to map clock registers\n", __func__);
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2013-12-24 13:38:26 +00:00
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goto err;
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}
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clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
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2017-04-18 08:12:32 +00:00
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if (!clk_data)
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2013-12-24 13:38:26 +00:00
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goto err;
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2017-04-18 08:12:32 +00:00
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2013-12-24 13:38:26 +00:00
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clk_data->base = base;
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2017-04-18 07:25:47 +00:00
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clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL);
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2017-04-18 08:12:32 +00:00
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if (!clk_table)
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2013-12-24 13:38:26 +00:00
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goto err_data;
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2017-04-18 08:12:32 +00:00
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2013-12-24 13:38:26 +00:00
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clk_data->clk_data.clks = clk_table;
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clk_data->clk_data.clk_num = nr_clks;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
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return clk_data;
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err_data:
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kfree(clk_data);
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err:
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return NULL;
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2013-11-13 00:51:23 +00:00
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}
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2016-04-23 07:40:29 +00:00
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EXPORT_SYMBOL_GPL(hisi_clk_init);
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2013-11-13 00:51:23 +00:00
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2016-06-15 06:26:36 +00:00
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int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *clks,
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2013-12-24 13:38:26 +00:00
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int nums, struct hisi_clock_data *data)
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2013-11-13 00:51:23 +00:00
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{
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struct clk *clk;
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int i;
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for (i = 0; i < nums; i++) {
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clk = clk_register_fixed_rate(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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clks[i].fixed_rate);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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2016-06-15 06:26:36 +00:00
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goto err;
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2013-11-13 00:51:23 +00:00
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}
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2013-12-24 13:38:26 +00:00
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data->clk_data.clks[clks[i].id] = clk;
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2013-11-13 00:51:23 +00:00
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}
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2016-06-15 06:26:36 +00:00
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return 0;
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err:
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while (i--)
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clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]);
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return PTR_ERR(clk);
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2013-11-13 00:51:23 +00:00
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}
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2016-04-23 07:40:29 +00:00
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EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_rate);
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2013-11-13 00:51:23 +00:00
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2016-06-15 06:26:36 +00:00
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int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *clks,
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2013-12-24 13:38:26 +00:00
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int nums,
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struct hisi_clock_data *data)
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2013-11-13 00:51:23 +00:00
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{
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struct clk *clk;
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int i;
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for (i = 0; i < nums; i++) {
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clk = clk_register_fixed_factor(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags, clks[i].mult,
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clks[i].div);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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2016-06-15 06:26:36 +00:00
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goto err;
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2013-11-13 00:51:23 +00:00
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}
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2013-12-24 13:38:26 +00:00
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data->clk_data.clks[clks[i].id] = clk;
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2013-11-13 00:51:23 +00:00
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}
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2016-06-15 06:26:36 +00:00
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return 0;
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err:
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while (i--)
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clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]);
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return PTR_ERR(clk);
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2013-11-13 00:51:23 +00:00
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}
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2016-04-23 07:40:29 +00:00
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EXPORT_SYMBOL_GPL(hisi_clk_register_fixed_factor);
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2013-11-13 00:51:23 +00:00
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2016-06-15 06:26:36 +00:00
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int hisi_clk_register_mux(const struct hisi_mux_clock *clks,
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2013-12-24 13:38:26 +00:00
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int nums, struct hisi_clock_data *data)
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2013-11-13 00:51:23 +00:00
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{
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struct clk *clk;
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2013-12-24 13:38:26 +00:00
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void __iomem *base = data->base;
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2013-11-13 00:51:23 +00:00
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int i;
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for (i = 0; i < nums; i++) {
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2014-04-21 03:35:21 +00:00
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u32 mask = BIT(clks[i].width) - 1;
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clk = clk_register_mux_table(NULL, clks[i].name,
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clks[i].parent_names,
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clks[i].num_parents, clks[i].flags,
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base + clks[i].offset, clks[i].shift,
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mask, clks[i].mux_flags,
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2021-03-23 11:29:33 +00:00
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(u32 *)clks[i].table, &hisi_clk_lock);
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2013-11-13 00:51:23 +00:00
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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2016-06-15 06:26:36 +00:00
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goto err;
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2013-11-13 00:51:23 +00:00
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}
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if (clks[i].alias)
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clk_register_clkdev(clk, clks[i].alias, NULL);
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2013-12-24 13:38:26 +00:00
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data->clk_data.clks[clks[i].id] = clk;
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2013-11-13 00:51:23 +00:00
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}
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2016-06-15 06:26:36 +00:00
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return 0;
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err:
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while (i--)
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clk_unregister_mux(data->clk_data.clks[clks[i].id]);
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return PTR_ERR(clk);
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2013-11-13 00:51:23 +00:00
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}
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2016-04-23 07:40:29 +00:00
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EXPORT_SYMBOL_GPL(hisi_clk_register_mux);
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2013-11-13 00:51:23 +00:00
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2018-03-05 07:01:31 +00:00
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int hisi_clk_register_phase(struct device *dev,
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const struct hisi_phase_clock *clks,
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int nums, struct hisi_clock_data *data)
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{
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void __iomem *base = data->base;
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struct clk *clk;
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int i;
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for (i = 0; i < nums; i++) {
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clk = clk_register_hisi_phase(dev, &clks[i], base,
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&hisi_clk_lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n", __func__,
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clks[i].name);
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return PTR_ERR(clk);
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}
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data->clk_data.clks[clks[i].id] = clk;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(hisi_clk_register_phase);
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2016-06-15 06:26:36 +00:00
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int hisi_clk_register_divider(const struct hisi_divider_clock *clks,
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2013-12-24 13:38:26 +00:00
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int nums, struct hisi_clock_data *data)
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2013-11-13 00:51:23 +00:00
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{
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struct clk *clk;
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2013-12-24 13:38:26 +00:00
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void __iomem *base = data->base;
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2013-11-13 00:51:23 +00:00
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int i;
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for (i = 0; i < nums; i++) {
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clk = clk_register_divider_table(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].shift, clks[i].width,
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clks[i].div_flags,
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clks[i].table,
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&hisi_clk_lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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2016-06-15 06:26:36 +00:00
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goto err;
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2013-11-13 00:51:23 +00:00
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}
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if (clks[i].alias)
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clk_register_clkdev(clk, clks[i].alias, NULL);
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2013-12-24 13:38:26 +00:00
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data->clk_data.clks[clks[i].id] = clk;
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2013-11-13 00:51:23 +00:00
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}
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2016-06-15 06:26:36 +00:00
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return 0;
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err:
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while (i--)
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clk_unregister_divider(data->clk_data.clks[clks[i].id]);
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return PTR_ERR(clk);
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2013-11-13 00:51:23 +00:00
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}
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2016-04-23 07:40:29 +00:00
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EXPORT_SYMBOL_GPL(hisi_clk_register_divider);
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2013-11-13 00:51:23 +00:00
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2016-06-15 06:26:36 +00:00
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int hisi_clk_register_gate(const struct hisi_gate_clock *clks,
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2014-04-22 07:42:47 +00:00
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int nums, struct hisi_clock_data *data)
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{
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struct clk *clk;
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void __iomem *base = data->base;
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int i;
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for (i = 0; i < nums; i++) {
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clk = clk_register_gate(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].bit_idx,
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clks[i].gate_flags,
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&hisi_clk_lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n",
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__func__, clks[i].name);
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2016-06-15 06:26:36 +00:00
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goto err;
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2014-04-22 07:42:47 +00:00
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}
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if (clks[i].alias)
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clk_register_clkdev(clk, clks[i].alias, NULL);
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data->clk_data.clks[clks[i].id] = clk;
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}
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2016-06-15 06:26:36 +00:00
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return 0;
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err:
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while (i--)
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clk_unregister_gate(data->clk_data.clks[clks[i].id]);
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return PTR_ERR(clk);
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2014-04-22 07:42:47 +00:00
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}
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2016-04-23 07:40:29 +00:00
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EXPORT_SYMBOL_GPL(hisi_clk_register_gate);
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2014-04-22 07:42:47 +00:00
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2016-04-23 07:40:29 +00:00
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void hisi_clk_register_gate_sep(const struct hisi_gate_clock *clks,
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2013-12-24 13:38:26 +00:00
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int nums, struct hisi_clock_data *data)
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2013-11-13 00:51:23 +00:00
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{
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struct clk *clk;
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2013-12-24 13:38:26 +00:00
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void __iomem *base = data->base;
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2013-11-13 00:51:23 +00:00
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int i;
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for (i = 0; i < nums; i++) {
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clk = hisi_register_clkgate_sep(NULL, clks[i].name,
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clks[i].parent_name,
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clks[i].flags,
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base + clks[i].offset,
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clks[i].bit_idx,
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clks[i].gate_flags,
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&hisi_clk_lock);
|
|
|
|
if (IS_ERR(clk)) {
|
|
|
|
pr_err("%s: failed to register clock %s\n",
|
|
|
|
__func__, clks[i].name);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (clks[i].alias)
|
|
|
|
clk_register_clkdev(clk, clks[i].alias, NULL);
|
|
|
|
|
2013-12-24 13:38:26 +00:00
|
|
|
data->clk_data.clks[clks[i].id] = clk;
|
2013-11-13 00:51:23 +00:00
|
|
|
}
|
|
|
|
}
|
2016-04-23 07:40:29 +00:00
|
|
|
EXPORT_SYMBOL_GPL(hisi_clk_register_gate_sep);
|
2015-05-29 02:08:38 +00:00
|
|
|
|
2016-04-23 07:40:29 +00:00
|
|
|
void __init hi6220_clk_register_divider(const struct hi6220_divider_clock *clks,
|
2015-05-29 02:08:38 +00:00
|
|
|
int nums, struct hisi_clock_data *data)
|
|
|
|
{
|
|
|
|
struct clk *clk;
|
|
|
|
void __iomem *base = data->base;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < nums; i++) {
|
|
|
|
clk = hi6220_register_clkdiv(NULL, clks[i].name,
|
|
|
|
clks[i].parent_name,
|
|
|
|
clks[i].flags,
|
|
|
|
base + clks[i].offset,
|
|
|
|
clks[i].shift,
|
|
|
|
clks[i].width,
|
|
|
|
clks[i].mask_bit,
|
|
|
|
&hisi_clk_lock);
|
|
|
|
if (IS_ERR(clk)) {
|
|
|
|
pr_err("%s: failed to register clock %s\n",
|
|
|
|
__func__, clks[i].name);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (clks[i].alias)
|
|
|
|
clk_register_clkdev(clk, clks[i].alias, NULL);
|
|
|
|
|
|
|
|
data->clk_data.clks[clks[i].id] = clk;
|
|
|
|
}
|
|
|
|
}
|