2009-05-28 17:56:16 +00:00
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/*
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* OMAP3 Power Management Routines
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*
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* Copyright (C) 2006-2008 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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* Jouni Hogander
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*
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2008-09-26 12:20:07 +00:00
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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2009-05-28 17:56:16 +00:00
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* Copyright (C) 2005 Texas Instruments, Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Based on pm.c for omap1
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/pm.h>
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#include <linux/suspend.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/list.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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2009-10-06 21:25:09 +00:00
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#include <linux/clk.h>
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2009-11-17 16:34:53 +00:00
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#include <linux/delay.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 08:04:11 +00:00
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#include <linux/slab.h>
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2009-05-28 17:56:16 +00:00
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2009-10-20 16:40:47 +00:00
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#include <plat/sram.h>
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#include <plat/clockdomain.h>
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#include <plat/powerdomain.h>
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#include <plat/control.h>
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#include <plat/serial.h>
|
2008-09-26 12:19:56 +00:00
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#include <plat/sdrc.h>
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2008-09-26 12:20:07 +00:00
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#include <plat/prcm.h>
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#include <plat/gpmc.h>
|
2008-08-28 13:13:31 +00:00
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#include <plat/dma.h>
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2009-10-06 21:30:23 +00:00
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#include <plat/dmtimer.h>
|
2009-05-28 17:56:16 +00:00
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2008-09-26 12:19:34 +00:00
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#include <asm/tlbflush.h>
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2009-05-28 17:56:16 +00:00
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#include "cm.h"
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#include "cm-regbits-34xx.h"
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#include "prm-regbits-34xx.h"
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#include "prm.h"
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#include "pm.h"
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2008-10-13 10:17:06 +00:00
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#include "sdrc.h"
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|
2008-09-26 12:20:07 +00:00
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/* Scratchpad offsets */
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#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
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#define OMAP343X_TABLE_VALUE_OFFSET 0x30
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#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
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|
2009-10-06 21:25:09 +00:00
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u32 enable_off_mode;
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u32 sleep_while_idle;
|
2009-10-06 21:30:23 +00:00
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u32 wakeup_timer_seconds;
|
2010-03-23 07:04:59 +00:00
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u32 wakeup_timer_milliseconds;
|
2009-10-06 21:25:09 +00:00
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2009-05-28 17:56:16 +00:00
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struct power_state {
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struct powerdomain *pwrdm;
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u32 next_state;
|
2009-06-24 18:39:18 +00:00
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#ifdef CONFIG_SUSPEND
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2009-05-28 17:56:16 +00:00
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u32 saved_state;
|
2009-06-24 18:39:18 +00:00
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#endif
|
2009-05-28 17:56:16 +00:00
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struct list_head node;
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};
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static LIST_HEAD(pwrst_list);
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static void (*_omap_sram_idle)(u32 *addr, int save_state);
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2008-10-13 10:15:00 +00:00
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static int (*_omap_save_secure_sram)(u32 *addr);
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2008-09-26 12:19:22 +00:00
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
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static struct powerdomain *core_pwrdm, *per_pwrdm;
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2008-12-11 14:46:57 +00:00
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static struct powerdomain *cam_pwrdm;
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2008-09-26 12:19:22 +00:00
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2008-09-26 12:20:07 +00:00
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static inline void omap3_per_save_context(void)
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{
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omap_gpio_save_context();
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}
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static inline void omap3_per_restore_context(void)
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{
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omap_gpio_restore_context();
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}
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2009-03-26 13:59:01 +00:00
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static void omap3_enable_io_chain(void)
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{
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int timeout = 0;
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if (omap_rev() >= OMAP3430_REV_ES3_1) {
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2010-05-19 00:47:24 +00:00
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prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKEN);
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2009-03-26 13:59:01 +00:00
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/* Do a readback to assure write has been done */
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prm_read_mod_reg(WKUP_MOD, PM_WKEN);
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while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
|
2010-05-19 00:47:24 +00:00
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OMAP3430_ST_IO_CHAIN_MASK)) {
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2009-03-26 13:59:01 +00:00
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timeout++;
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if (timeout > 1000) {
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printk(KERN_ERR "Wake up daisy chain "
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"activation failed.\n");
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return;
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}
|
2010-05-19 00:47:24 +00:00
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prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
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2009-03-26 13:59:01 +00:00
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WKUP_MOD, PM_WKST);
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}
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}
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}
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static void omap3_disable_io_chain(void)
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{
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if (omap_rev() >= OMAP3430_REV_ES3_1)
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2010-05-19 00:47:24 +00:00
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prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
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PM_WKEN);
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2009-03-26 13:59:01 +00:00
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}
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2008-09-26 12:20:07 +00:00
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static void omap3_core_save_context(void)
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{
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u32 control_padconf_off;
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/* Save the padconf registers */
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control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
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control_padconf_off |= START_PADCONF_SAVE;
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omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
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/* wait for the save to complete */
|
2010-01-08 18:29:07 +00:00
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while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
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& PADCONF_SAVE_DONE))
|
2009-11-17 16:34:53 +00:00
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udelay(1);
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/*
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* Force write last pad into memory, as this can fail in some
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* cases according to erratas 1.157, 1.185
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*/
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omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
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OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
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2008-09-26 12:20:07 +00:00
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/* Save the Interrupt controller context */
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omap_intc_save_context();
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/* Save the GPMC context */
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omap3_gpmc_save_context();
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/* Save the system control module context, padconf already save above*/
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omap3_control_save_context();
|
2008-08-28 13:13:31 +00:00
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omap_dma_global_context_save();
|
2008-09-26 12:20:07 +00:00
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}
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static void omap3_core_restore_context(void)
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{
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/* Restore the control module context, padconf restored by h/w */
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omap3_control_restore_context();
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/* Restore the GPMC context */
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omap3_gpmc_restore_context();
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/* Restore the interrupt controller context */
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omap_intc_restore_context();
|
2008-08-28 13:13:31 +00:00
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omap_dma_global_context_restore();
|
2008-09-26 12:20:07 +00:00
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}
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|
2008-12-12 09:20:05 +00:00
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/*
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* FIXME: This function should be called before entering off-mode after
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* OMAP3 secure services have been accessed. Currently it is only called
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* once during boot sequence, but this works as we are not using secure
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* services.
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*/
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2008-10-13 10:15:00 +00:00
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static void omap3_save_secure_ram_context(u32 target_mpu_state)
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{
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u32 ret;
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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/*
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* MPU next state must be set to POWER_ON temporarily,
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* otherwise the WFI executed inside the ROM code
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* will hang the system.
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*/
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pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
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ret = _omap_save_secure_sram((u32 *)
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__pa(omap3_secure_ram_storage));
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pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
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/* Following is for error tracking, it should not happen */
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if (ret) {
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printk(KERN_ERR "save_secure_sram() returns %08x\n",
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ret);
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while (1)
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;
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}
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}
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}
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|
2009-06-27 05:07:25 +00:00
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/*
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|
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* PRCM Interrupt Handler Helper Function
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*
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* The purpose of this function is to clear any wake-up events latched
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* in the PRCM PM_WKST_x registers. It is possible that a wake-up event
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* may occur whilst attempting to clear a PM_WKST_x register and thus
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* set another bit in this register. A while loop is used to ensure
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* that any peripheral wake-up events occurring while attempting to
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* clear the PM_WKST_x are detected and cleared.
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*/
|
2009-07-22 17:29:02 +00:00
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static int prcm_clear_mod_irqs(s16 module, u8 regs)
|
2009-05-28 17:56:16 +00:00
|
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{
|
2009-07-18 00:33:09 +00:00
|
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u32 wkst, fclk, iclk, clken;
|
2009-06-27 05:07:25 +00:00
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u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
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u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
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u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
|
2009-07-22 17:18:07 +00:00
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u16 grpsel_off = (regs == 3) ?
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OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
|
2009-07-22 17:29:02 +00:00
|
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int c = 0;
|
2009-05-28 17:56:16 +00:00
|
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|
2009-06-27 05:07:25 +00:00
|
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wkst = prm_read_mod_reg(module, wkst_off);
|
2009-07-22 17:18:07 +00:00
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|
wkst &= prm_read_mod_reg(module, grpsel_off);
|
2009-05-28 17:56:16 +00:00
|
|
|
if (wkst) {
|
2009-06-27 05:07:25 +00:00
|
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|
iclk = cm_read_mod_reg(module, iclk_off);
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fclk = cm_read_mod_reg(module, fclk_off);
|
|
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while (wkst) {
|
2009-07-18 00:33:09 +00:00
|
|
|
clken = wkst;
|
|
|
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cm_set_mod_reg_bits(clken, module, iclk_off);
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|
|
|
/*
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|
|
|
* For USBHOST, we don't know whether HOST1 or
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|
|
|
* HOST2 woke us up, so enable both f-clocks
|
|
|
|
*/
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|
if (module == OMAP3430ES2_USBHOST_MOD)
|
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|
|
clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
|
|
|
|
cm_set_mod_reg_bits(clken, module, fclk_off);
|
2009-06-27 05:07:25 +00:00
|
|
|
prm_write_mod_reg(wkst, module, wkst_off);
|
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|
|
wkst = prm_read_mod_reg(module, wkst_off);
|
2009-07-22 17:29:02 +00:00
|
|
|
c++;
|
2009-06-27 05:07:25 +00:00
|
|
|
}
|
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|
|
cm_write_mod_reg(iclk, module, iclk_off);
|
|
|
|
cm_write_mod_reg(fclk, module, fclk_off);
|
2009-05-28 17:56:16 +00:00
|
|
|
}
|
2009-07-22 17:29:02 +00:00
|
|
|
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|
|
|
return c;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int _prcm_int_handle_wakeup(void)
|
|
|
|
{
|
|
|
|
int c;
|
|
|
|
|
|
|
|
c = prcm_clear_mod_irqs(WKUP_MOD, 1);
|
|
|
|
c += prcm_clear_mod_irqs(CORE_MOD, 1);
|
|
|
|
c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
c += prcm_clear_mod_irqs(CORE_MOD, 3);
|
|
|
|
c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return c;
|
2009-06-27 05:07:25 +00:00
|
|
|
}
|
2009-05-28 17:56:16 +00:00
|
|
|
|
2009-06-27 05:07:25 +00:00
|
|
|
/*
|
|
|
|
* PRCM Interrupt Handler
|
|
|
|
*
|
|
|
|
* The PRM_IRQSTATUS_MPU register indicates if there are any pending
|
|
|
|
* interrupts from the PRCM for the MPU. These bits must be cleared in
|
|
|
|
* order to clear the PRCM interrupt. The PRCM interrupt handler is
|
|
|
|
* implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
|
|
|
|
* the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
|
|
|
|
* register indicates that a wake-up event is pending for the MPU and
|
|
|
|
* this bit can only be cleared if the all the wake-up events latched
|
|
|
|
* in the various PM_WKST_x registers have been cleared. The interrupt
|
|
|
|
* handler is implemented using a do-while loop so that if a wake-up
|
|
|
|
* event occurred during the processing of the prcm interrupt handler
|
|
|
|
* (setting a bit in the corresponding PM_WKST_x register and thus
|
|
|
|
* preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
|
|
|
|
* this would be handled.
|
|
|
|
*/
|
|
|
|
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
|
|
|
|
{
|
2010-04-26 21:59:09 +00:00
|
|
|
u32 irqenable_mpu, irqstatus_mpu;
|
2009-07-22 17:29:02 +00:00
|
|
|
int c = 0;
|
2009-06-27 05:07:25 +00:00
|
|
|
|
2010-04-26 21:59:09 +00:00
|
|
|
irqenable_mpu = prm_read_mod_reg(OCP_MOD,
|
|
|
|
OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
|
|
|
irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
|
|
|
|
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
irqstatus_mpu &= irqenable_mpu;
|
2009-07-22 17:29:02 +00:00
|
|
|
|
2010-04-26 21:59:09 +00:00
|
|
|
do {
|
2010-05-19 00:47:24 +00:00
|
|
|
if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
|
|
|
|
OMAP3430_IO_ST_MASK)) {
|
2009-07-22 17:29:02 +00:00
|
|
|
c = _prcm_int_handle_wakeup();
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Is the MPU PRCM interrupt handler racing with the
|
|
|
|
* IVA2 PRCM interrupt handler ?
|
|
|
|
*/
|
|
|
|
WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
|
|
|
|
"but no wakeup sources are marked\n");
|
|
|
|
} else {
|
|
|
|
/* XXX we need to expand our PRCM interrupt handler */
|
|
|
|
WARN(1, "prcm: WARNING: PRCM interrupt received, but "
|
|
|
|
"no code to handle it (%08x)\n", irqstatus_mpu);
|
|
|
|
}
|
|
|
|
|
2009-06-27 05:07:25 +00:00
|
|
|
prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
|
|
|
|
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
2009-05-28 17:56:16 +00:00
|
|
|
|
2010-04-26 21:59:09 +00:00
|
|
|
irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
|
|
|
|
OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
irqstatus_mpu &= irqenable_mpu;
|
|
|
|
|
|
|
|
} while (irqstatus_mpu);
|
2009-05-28 17:56:16 +00:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2008-09-26 12:19:34 +00:00
|
|
|
static void restore_control_register(u32 val)
|
|
|
|
{
|
|
|
|
__asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Function to restore the table entry that was modified for enabling MMU */
|
|
|
|
static void restore_table_entry(void)
|
|
|
|
{
|
|
|
|
u32 *scratchpad_address;
|
|
|
|
u32 previous_value, control_reg_value;
|
|
|
|
u32 *address;
|
|
|
|
|
|
|
|
scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
|
|
|
|
|
|
|
|
/* Get address of entry that was modified */
|
|
|
|
address = (u32 *)__raw_readl(scratchpad_address +
|
|
|
|
OMAP343X_TABLE_ADDRESS_OFFSET);
|
|
|
|
/* Get the previous value which needs to be restored */
|
|
|
|
previous_value = __raw_readl(scratchpad_address +
|
|
|
|
OMAP343X_TABLE_VALUE_OFFSET);
|
|
|
|
address = __va(address);
|
|
|
|
*address = previous_value;
|
|
|
|
flush_tlb_all();
|
|
|
|
control_reg_value = __raw_readl(scratchpad_address
|
|
|
|
+ OMAP343X_CONTROL_REG_VALUE_OFFSET);
|
|
|
|
/* This will enable caches and prediction */
|
|
|
|
restore_control_register(control_reg_value);
|
|
|
|
}
|
|
|
|
|
2008-10-08 12:00:58 +00:00
|
|
|
void omap_sram_idle(void)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
|
|
|
/* Variable to tell what needs to be saved and restored
|
|
|
|
* in omap_sram_idle*/
|
|
|
|
/* save_state = 0 => Nothing to save and restored */
|
|
|
|
/* save_state = 1 => Only L1 and logic lost */
|
|
|
|
/* save_state = 2 => Only L2 lost */
|
|
|
|
/* save_state = 3 => L1, L2 and logic lost */
|
2008-09-26 12:19:22 +00:00
|
|
|
int save_state = 0;
|
|
|
|
int mpu_next_state = PWRDM_POWER_ON;
|
|
|
|
int per_next_state = PWRDM_POWER_ON;
|
|
|
|
int core_next_state = PWRDM_POWER_ON;
|
2008-09-26 12:20:07 +00:00
|
|
|
int core_prev_state, per_prev_state;
|
2008-10-13 10:17:06 +00:00
|
|
|
u32 sdrc_pwr = 0;
|
2008-12-01 11:17:29 +00:00
|
|
|
int per_state_modified = 0;
|
2009-05-28 17:56:16 +00:00
|
|
|
|
|
|
|
if (!_omap_sram_idle)
|
|
|
|
return;
|
|
|
|
|
2008-09-26 12:19:22 +00:00
|
|
|
pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
|
|
|
|
pwrdm_clear_all_prev_pwrst(neon_pwrdm);
|
|
|
|
pwrdm_clear_all_prev_pwrst(core_pwrdm);
|
|
|
|
pwrdm_clear_all_prev_pwrst(per_pwrdm);
|
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
|
|
|
|
switch (mpu_next_state) {
|
2008-09-26 12:19:22 +00:00
|
|
|
case PWRDM_POWER_ON:
|
2009-05-28 17:56:16 +00:00
|
|
|
case PWRDM_POWER_RET:
|
|
|
|
/* No need to save context */
|
|
|
|
save_state = 0;
|
|
|
|
break;
|
2008-09-26 12:19:56 +00:00
|
|
|
case PWRDM_POWER_OFF:
|
|
|
|
save_state = 3;
|
|
|
|
break;
|
2009-05-28 17:56:16 +00:00
|
|
|
default:
|
|
|
|
/* Invalid state */
|
|
|
|
printk(KERN_ERR "Invalid mpu state in sram_idle\n");
|
|
|
|
return;
|
|
|
|
}
|
2008-10-15 14:48:44 +00:00
|
|
|
pwrdm_pre_transition();
|
|
|
|
|
2008-09-26 12:19:22 +00:00
|
|
|
/* NEON control */
|
|
|
|
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
|
2008-10-28 08:59:05 +00:00
|
|
|
pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
|
2008-09-26 12:19:22 +00:00
|
|
|
|
2010-05-03 23:04:06 +00:00
|
|
|
/* Enable IO-PAD and IO-CHAIN wakeups */
|
2008-11-05 04:50:52 +00:00
|
|
|
per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
|
2008-12-01 11:17:29 +00:00
|
|
|
core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
|
2010-05-03 23:04:06 +00:00
|
|
|
if (per_next_state < PWRDM_POWER_ON ||
|
|
|
|
core_next_state < PWRDM_POWER_ON) {
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
|
2010-05-03 23:04:06 +00:00
|
|
|
omap3_enable_io_chain();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* PER */
|
2008-11-05 04:50:52 +00:00
|
|
|
if (per_next_state < PWRDM_POWER_ON) {
|
|
|
|
omap_uart_prepare_idle(2);
|
2009-01-27 19:09:24 +00:00
|
|
|
omap2_gpio_prepare_for_idle(per_next_state);
|
2008-12-01 11:17:29 +00:00
|
|
|
if (per_next_state == PWRDM_POWER_OFF) {
|
|
|
|
if (core_next_state == PWRDM_POWER_ON) {
|
|
|
|
per_next_state = PWRDM_POWER_RET;
|
|
|
|
pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
|
|
|
|
per_state_modified = 1;
|
2009-01-27 19:09:24 +00:00
|
|
|
} else
|
2008-12-01 11:17:29 +00:00
|
|
|
omap3_per_save_context();
|
|
|
|
}
|
2008-11-05 04:50:52 +00:00
|
|
|
}
|
|
|
|
|
2008-12-11 14:46:57 +00:00
|
|
|
if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
|
|
|
|
omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
|
|
|
|
|
2008-11-05 04:50:52 +00:00
|
|
|
/* CORE */
|
2008-09-26 12:19:22 +00:00
|
|
|
if (core_next_state < PWRDM_POWER_ON) {
|
|
|
|
omap_uart_prepare_idle(0);
|
|
|
|
omap_uart_prepare_idle(1);
|
2008-09-26 12:20:07 +00:00
|
|
|
if (core_next_state == PWRDM_POWER_OFF) {
|
|
|
|
omap3_core_save_context();
|
|
|
|
omap3_prcm_save_context();
|
|
|
|
}
|
2008-09-26 12:19:22 +00:00
|
|
|
}
|
2010-05-03 23:04:06 +00:00
|
|
|
|
2009-10-23 16:03:50 +00:00
|
|
|
omap3_intc_prepare_idle();
|
2009-05-28 17:56:16 +00:00
|
|
|
|
2008-10-13 10:17:06 +00:00
|
|
|
/*
|
2009-06-09 17:00:41 +00:00
|
|
|
* On EMU/HS devices ROM code restores a SRDC value
|
|
|
|
* from scratchpad which has automatic self refresh on timeout
|
|
|
|
* of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
|
|
|
|
* Hence store/restore the SDRC_POWER register here.
|
|
|
|
*/
|
2008-10-13 10:17:06 +00:00
|
|
|
if (omap_rev() >= OMAP3430_REV_ES3_0 &&
|
|
|
|
omap_type() != OMAP2_DEVICE_TYPE_GP &&
|
2009-06-09 17:00:41 +00:00
|
|
|
core_next_state == PWRDM_POWER_OFF)
|
2008-10-13 10:17:06 +00:00
|
|
|
sdrc_pwr = sdrc_read_reg(SDRC_POWER);
|
|
|
|
|
2008-09-26 12:19:56 +00:00
|
|
|
/*
|
|
|
|
* omap3_arm_context is the location where ARM registers
|
|
|
|
* get saved. The restore path then reads from this
|
|
|
|
* location and restores them back.
|
|
|
|
*/
|
|
|
|
_omap_sram_idle(omap3_arm_context, save_state);
|
2009-05-28 17:56:16 +00:00
|
|
|
cpu_init();
|
|
|
|
|
2009-06-09 17:00:41 +00:00
|
|
|
/* Restore normal SDRC POWER settings */
|
2008-10-13 10:17:06 +00:00
|
|
|
if (omap_rev() >= OMAP3430_REV_ES3_0 &&
|
|
|
|
omap_type() != OMAP2_DEVICE_TYPE_GP &&
|
|
|
|
core_next_state == PWRDM_POWER_OFF)
|
|
|
|
sdrc_write_reg(sdrc_pwr, SDRC_POWER);
|
|
|
|
|
2008-09-26 12:19:34 +00:00
|
|
|
/* Restore table entry modified during MMU restoration */
|
|
|
|
if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
|
|
|
|
restore_table_entry();
|
|
|
|
|
2008-11-05 04:50:52 +00:00
|
|
|
/* CORE */
|
2008-09-26 12:19:22 +00:00
|
|
|
if (core_next_state < PWRDM_POWER_ON) {
|
2008-09-26 12:20:07 +00:00
|
|
|
core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
|
|
|
|
if (core_prev_state == PWRDM_POWER_OFF) {
|
|
|
|
omap3_core_restore_context();
|
|
|
|
omap3_prcm_restore_context();
|
|
|
|
omap3_sram_restore_context();
|
2009-05-13 10:32:11 +00:00
|
|
|
omap2_sms_restore_context();
|
2008-09-26 12:20:07 +00:00
|
|
|
}
|
2008-11-05 04:50:52 +00:00
|
|
|
omap_uart_resume_idle(0);
|
|
|
|
omap_uart_resume_idle(1);
|
|
|
|
if (core_next_state == PWRDM_POWER_OFF)
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
|
2008-11-05 04:50:52 +00:00
|
|
|
OMAP3430_GR_MOD,
|
|
|
|
OMAP3_PRM_VOLTCTRL_OFFSET);
|
|
|
|
}
|
2009-10-23 16:03:50 +00:00
|
|
|
omap3_intc_resume_idle();
|
2008-11-05 04:50:52 +00:00
|
|
|
|
|
|
|
/* PER */
|
|
|
|
if (per_next_state < PWRDM_POWER_ON) {
|
|
|
|
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
|
2009-01-27 19:09:24 +00:00
|
|
|
omap2_gpio_resume_after_idle();
|
|
|
|
if (per_prev_state == PWRDM_POWER_OFF)
|
2008-11-05 04:50:52 +00:00
|
|
|
omap3_per_restore_context();
|
2008-12-01 11:17:29 +00:00
|
|
|
omap_uart_resume_idle(2);
|
|
|
|
if (per_state_modified)
|
|
|
|
pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
|
2008-09-26 12:19:22 +00:00
|
|
|
}
|
2008-10-15 14:48:44 +00:00
|
|
|
|
2009-03-26 13:59:01 +00:00
|
|
|
/* Disable IO-PAD and IO-CHAIN wakeup */
|
2010-05-19 00:47:24 +00:00
|
|
|
if (core_next_state < PWRDM_POWER_ON) {
|
|
|
|
prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
|
2009-03-26 13:59:01 +00:00
|
|
|
omap3_disable_io_chain();
|
|
|
|
}
|
2008-11-05 04:50:52 +00:00
|
|
|
|
2008-10-15 14:48:44 +00:00
|
|
|
pwrdm_post_transition();
|
|
|
|
|
2008-12-11 14:46:57 +00:00
|
|
|
omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
|
2009-05-28 17:56:16 +00:00
|
|
|
}
|
|
|
|
|
2008-10-08 12:01:22 +00:00
|
|
|
int omap3_can_sleep(void)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
2009-10-06 21:25:09 +00:00
|
|
|
if (!sleep_while_idle)
|
|
|
|
return 0;
|
OMAP3: PM: UART: disable clocks when idle and off-mode support
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-02-04 18:51:40 +00:00
|
|
|
if (!omap_uart_can_sleep())
|
|
|
|
return 0;
|
2009-05-28 17:56:16 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This sets pwrdm state (other than mpu & core. Currently only ON &
|
|
|
|
* RET are supported. Function is assuming that clkdm doesn't have
|
|
|
|
* hw_sup mode enabled. */
|
2008-10-08 12:01:22 +00:00
|
|
|
int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
|
|
|
u32 cur_state;
|
|
|
|
int sleep_switch = 0;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
if (pwrdm == NULL || IS_ERR(pwrdm))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
while (!(pwrdm->pwrsts & (1 << state))) {
|
|
|
|
if (state == PWRDM_POWER_OFF)
|
|
|
|
return ret;
|
|
|
|
state--;
|
|
|
|
}
|
|
|
|
|
|
|
|
cur_state = pwrdm_read_next_pwrst(pwrdm);
|
|
|
|
if (cur_state == state)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
|
|
|
|
omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
|
|
|
|
sleep_switch = 1;
|
|
|
|
pwrdm_wait_transition(pwrdm);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = pwrdm_set_next_pwrst(pwrdm, state);
|
|
|
|
if (ret) {
|
|
|
|
printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
|
|
|
|
pwrdm->name);
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sleep_switch) {
|
|
|
|
omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
|
|
|
|
pwrdm_wait_transition(pwrdm);
|
2008-10-15 14:48:44 +00:00
|
|
|
pwrdm_state_switch(pwrdm);
|
2009-05-28 17:56:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
err:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_idle(void)
|
|
|
|
{
|
|
|
|
local_irq_disable();
|
|
|
|
local_fiq_disable();
|
|
|
|
|
|
|
|
if (!omap3_can_sleep())
|
|
|
|
goto out;
|
|
|
|
|
2009-03-20 13:21:02 +00:00
|
|
|
if (omap_irq_pending() || need_resched())
|
2009-05-28 17:56:16 +00:00
|
|
|
goto out;
|
|
|
|
|
|
|
|
omap_sram_idle();
|
|
|
|
|
|
|
|
out:
|
|
|
|
local_fiq_enable();
|
|
|
|
local_irq_enable();
|
|
|
|
}
|
|
|
|
|
2009-06-24 18:39:18 +00:00
|
|
|
#ifdef CONFIG_SUSPEND
|
2009-03-05 14:32:23 +00:00
|
|
|
static suspend_state_t suspend_state;
|
|
|
|
|
2010-03-23 07:04:59 +00:00
|
|
|
static void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
|
2009-10-06 21:30:23 +00:00
|
|
|
{
|
|
|
|
u32 tick_rate, cycles;
|
|
|
|
|
2010-03-23 07:04:59 +00:00
|
|
|
if (!seconds && !milliseconds)
|
2009-10-06 21:30:23 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
|
2010-03-23 07:04:59 +00:00
|
|
|
cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
|
2009-10-06 21:30:23 +00:00
|
|
|
omap_dm_timer_stop(gptimer_wakeup);
|
|
|
|
omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
|
|
|
|
|
2010-03-23 07:04:59 +00:00
|
|
|
pr_info("PM: Resume timer in %u.%03u secs"
|
|
|
|
" (%d ticks at %d ticks/sec.)\n",
|
|
|
|
seconds, milliseconds, cycles, tick_rate);
|
2009-10-06 21:30:23 +00:00
|
|
|
}
|
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
static int omap3_pm_prepare(void)
|
|
|
|
{
|
|
|
|
disable_hlt();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap3_pm_suspend(void)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
int state, ret = 0;
|
|
|
|
|
2010-03-23 07:04:59 +00:00
|
|
|
if (wakeup_timer_seconds || wakeup_timer_milliseconds)
|
|
|
|
omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
|
|
|
|
wakeup_timer_milliseconds);
|
2009-10-06 21:30:23 +00:00
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
/* Read current next_pwrsts */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node)
|
|
|
|
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
|
|
|
|
/* Set ones wanted by suspend */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
|
|
|
|
goto restore;
|
|
|
|
if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
|
|
|
|
goto restore;
|
|
|
|
}
|
|
|
|
|
OMAP3: PM: UART: disable clocks when idle and off-mode support
This patch allows the UART clocks to be disabled when the OMAP UARTs
are inactive, thus permitting the chip to hit retention in idle.
After the expiration of an activity timer, each UART is allowed to
disable its clocks so the system can enter retention. The activity
timer is (re)activated on any UART interrupt, UART wake event or any
IO pad wakeup. The actual disable of the UART clocks is done in the
'prepare_idle' hook called from the OMAP idle loop.
While the activity timer is active, the smart-idle mode of the UART is
also disabled. This is due to a "feature" of the UART module that
after a UART wakeup, the smart-idle mode may be entered before the
UART has communicated the interrupt, or upon TX, an idle mode may be
entered before the TX FIFOs are emptied.
Upon suspend, the 'prepare_suspend' hook cancels any pending activity
timers and allows the clocks to be disabled immediately.
In addition, upon disabling clocks the UART state is saved in case
of an off-mode transition while clocks are off.
Special thanks to Tero Kristo for the initial ideas and first versions
of UART idle support, and to Jouni Hogander for extra testing and
bugfixes.
Tested on OMAP3 (Beagle, RX51, SDP, EVM) and OMAP2 (n810)
Cc: Tero Kristo <tero.kristo@nokia.com>
Cc: Jouni Hogander <jouni.hogander@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-02-04 18:51:40 +00:00
|
|
|
omap_uart_prepare_suspend();
|
2009-10-23 16:03:48 +00:00
|
|
|
omap3_intc_suspend();
|
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
omap_sram_idle();
|
|
|
|
|
|
|
|
restore:
|
|
|
|
/* Restore next_pwrsts */
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
|
|
|
|
if (state > pwrst->next_state) {
|
|
|
|
printk(KERN_INFO "Powerdomain (%s) didn't enter "
|
|
|
|
"target state %d\n",
|
|
|
|
pwrst->pwrdm->name, pwrst->next_state);
|
|
|
|
ret = -1;
|
|
|
|
}
|
2008-10-29 10:06:04 +00:00
|
|
|
set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
|
2009-05-28 17:56:16 +00:00
|
|
|
}
|
|
|
|
if (ret)
|
|
|
|
printk(KERN_ERR "Could not enter target state in pm_suspend\n");
|
|
|
|
else
|
|
|
|
printk(KERN_INFO "Successfully put all powerdomains "
|
|
|
|
"to target state\n");
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2009-03-05 14:32:23 +00:00
|
|
|
static int omap3_pm_enter(suspend_state_t unused)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
|
|
|
int ret = 0;
|
|
|
|
|
2009-03-05 14:32:23 +00:00
|
|
|
switch (suspend_state) {
|
2009-05-28 17:56:16 +00:00
|
|
|
case PM_SUSPEND_STANDBY:
|
|
|
|
case PM_SUSPEND_MEM:
|
|
|
|
ret = omap3_pm_suspend();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_finish(void)
|
|
|
|
{
|
|
|
|
enable_hlt();
|
|
|
|
}
|
|
|
|
|
2009-03-05 14:32:23 +00:00
|
|
|
/* Hooks to enable / disable UART interrupts during suspend */
|
|
|
|
static int omap3_pm_begin(suspend_state_t state)
|
|
|
|
{
|
|
|
|
suspend_state = state;
|
|
|
|
omap_uart_enable_irqs(0);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void omap3_pm_end(void)
|
|
|
|
{
|
|
|
|
suspend_state = PM_SUSPEND_ON;
|
|
|
|
omap_uart_enable_irqs(1);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
static struct platform_suspend_ops omap_pm_ops = {
|
2009-03-05 14:32:23 +00:00
|
|
|
.begin = omap3_pm_begin,
|
|
|
|
.end = omap3_pm_end,
|
2009-05-28 17:56:16 +00:00
|
|
|
.prepare = omap3_pm_prepare,
|
|
|
|
.enter = omap3_pm_enter,
|
|
|
|
.finish = omap3_pm_finish,
|
|
|
|
.valid = suspend_valid_only_mem,
|
|
|
|
};
|
2009-06-24 18:39:18 +00:00
|
|
|
#endif /* CONFIG_SUSPEND */
|
2009-05-28 17:56:16 +00:00
|
|
|
|
2008-11-25 19:48:24 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* omap3_iva_idle(): ensure IVA is in idle so it can be put into
|
|
|
|
* retention
|
|
|
|
*
|
|
|
|
* In cases where IVA2 is activated by bootcode, it may prevent
|
|
|
|
* full-chip retention or off-mode because it is not idle. This
|
|
|
|
* function forces the IVA2 into idle state so it can go
|
|
|
|
* into retention/off and thus allow full-chip retention/off.
|
|
|
|
*
|
|
|
|
**/
|
|
|
|
static void __init omap3_iva_idle(void)
|
|
|
|
{
|
|
|
|
/* ensure IVA2 clock is disabled */
|
|
|
|
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* if no clock activity, nothing else to do */
|
|
|
|
if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
|
|
|
|
OMAP3430_CLKACTIVITY_IVA2_MASK))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* Reset IVA2 */
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
|
|
|
OMAP3430_RST2_IVA2_MASK |
|
|
|
|
OMAP3430_RST3_IVA2_MASK,
|
2010-01-27 03:12:51 +00:00
|
|
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
2008-11-25 19:48:24 +00:00
|
|
|
|
|
|
|
/* Enable IVA2 clock */
|
2010-02-24 19:05:48 +00:00
|
|
|
cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
|
2008-11-25 19:48:24 +00:00
|
|
|
OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* Set IVA2 boot mode to 'idle' */
|
|
|
|
omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
|
|
|
|
OMAP343X_CONTROL_IVA2_BOOTMOD);
|
|
|
|
|
|
|
|
/* Un-reset IVA2 */
|
2010-01-27 03:12:51 +00:00
|
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
2008-11-25 19:48:24 +00:00
|
|
|
|
|
|
|
/* Disable IVA2 clock */
|
|
|
|
cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
|
|
|
|
|
|
|
|
/* Reset IVA2 */
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
|
|
|
|
OMAP3430_RST2_IVA2_MASK |
|
|
|
|
OMAP3430_RST3_IVA2_MASK,
|
2010-01-27 03:12:51 +00:00
|
|
|
OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
|
2008-11-25 19:48:24 +00:00
|
|
|
}
|
|
|
|
|
2009-04-28 22:27:44 +00:00
|
|
|
static void __init omap3_d2d_idle(void)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
2009-04-28 22:27:44 +00:00
|
|
|
u16 mask, padconf;
|
|
|
|
|
|
|
|
/* In a stand alone OMAP3430 where there is not a stacked
|
|
|
|
* modem for the D2D Idle Ack and D2D MStandby must be pulled
|
|
|
|
* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
|
|
|
|
* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
|
|
|
|
mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
padconf |= mask;
|
|
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
|
|
|
|
|
|
|
|
padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
padconf |= mask;
|
|
|
|
omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
|
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
/* reset modem */
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
|
|
|
|
OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
|
2010-01-27 03:12:51 +00:00
|
|
|
CORE_MOD, OMAP2_RM_RSTCTRL);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
|
2009-04-28 22:27:44 +00:00
|
|
|
}
|
2009-05-28 17:56:16 +00:00
|
|
|
|
2009-04-28 22:27:44 +00:00
|
|
|
static void __init prcm_setup_regs(void)
|
|
|
|
{
|
2009-05-28 17:56:16 +00:00
|
|
|
/* XXX Reset all wkdeps. This should be done when initializing
|
|
|
|
* powerdomains */
|
|
|
|
prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
|
|
|
|
prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
|
|
|
} else
|
|
|
|
prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable interface clock autoidle for all modules.
|
|
|
|
* Note that in the long run this should be done by clockfw
|
|
|
|
*/
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_MODEM_MASK |
|
|
|
|
OMAP3430ES2_AUTO_MMC3_MASK |
|
|
|
|
OMAP3430ES2_AUTO_ICR_MASK |
|
|
|
|
OMAP3430_AUTO_AES2_MASK |
|
|
|
|
OMAP3430_AUTO_SHA12_MASK |
|
|
|
|
OMAP3430_AUTO_DES2_MASK |
|
|
|
|
OMAP3430_AUTO_MMC2_MASK |
|
|
|
|
OMAP3430_AUTO_MMC1_MASK |
|
|
|
|
OMAP3430_AUTO_MSPRO_MASK |
|
|
|
|
OMAP3430_AUTO_HDQ_MASK |
|
|
|
|
OMAP3430_AUTO_MCSPI4_MASK |
|
|
|
|
OMAP3430_AUTO_MCSPI3_MASK |
|
|
|
|
OMAP3430_AUTO_MCSPI2_MASK |
|
|
|
|
OMAP3430_AUTO_MCSPI1_MASK |
|
|
|
|
OMAP3430_AUTO_I2C3_MASK |
|
|
|
|
OMAP3430_AUTO_I2C2_MASK |
|
|
|
|
OMAP3430_AUTO_I2C1_MASK |
|
|
|
|
OMAP3430_AUTO_UART2_MASK |
|
|
|
|
OMAP3430_AUTO_UART1_MASK |
|
|
|
|
OMAP3430_AUTO_GPT11_MASK |
|
|
|
|
OMAP3430_AUTO_GPT10_MASK |
|
|
|
|
OMAP3430_AUTO_MCBSP5_MASK |
|
|
|
|
OMAP3430_AUTO_MCBSP1_MASK |
|
|
|
|
OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
|
|
|
|
OMAP3430_AUTO_MAILBOXES_MASK |
|
|
|
|
OMAP3430_AUTO_OMAPCTRL_MASK |
|
|
|
|
OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
|
|
|
|
OMAP3430_AUTO_HSOTGUSB_MASK |
|
|
|
|
OMAP3430_AUTO_SAD2D_MASK |
|
|
|
|
OMAP3430_AUTO_SSI_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
CORE_MOD, CM_AUTOIDLE1);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_PKA_MASK |
|
|
|
|
OMAP3430_AUTO_AES1_MASK |
|
|
|
|
OMAP3430_AUTO_RNG_MASK |
|
|
|
|
OMAP3430_AUTO_SHA11_MASK |
|
|
|
|
OMAP3430_AUTO_DES1_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
CORE_MOD, CM_AUTOIDLE2);
|
|
|
|
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_MAD2D_MASK |
|
|
|
|
OMAP3430ES2_AUTO_USBTLL_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
CORE_MOD, CM_AUTOIDLE3);
|
|
|
|
}
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_WDT2_MASK |
|
|
|
|
OMAP3430_AUTO_WDT1_MASK |
|
|
|
|
OMAP3430_AUTO_GPIO1_MASK |
|
|
|
|
OMAP3430_AUTO_32KSYNC_MASK |
|
|
|
|
OMAP3430_AUTO_GPT12_MASK |
|
|
|
|
OMAP3430_AUTO_GPT1_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
WKUP_MOD, CM_AUTOIDLE);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_DSS_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
OMAP3430_DSS_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_CAM_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
OMAP3430_CAM_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430_AUTO_GPIO6_MASK |
|
|
|
|
OMAP3430_AUTO_GPIO5_MASK |
|
|
|
|
OMAP3430_AUTO_GPIO4_MASK |
|
|
|
|
OMAP3430_AUTO_GPIO3_MASK |
|
|
|
|
OMAP3430_AUTO_GPIO2_MASK |
|
|
|
|
OMAP3430_AUTO_WDT3_MASK |
|
|
|
|
OMAP3430_AUTO_UART3_MASK |
|
|
|
|
OMAP3430_AUTO_GPT9_MASK |
|
|
|
|
OMAP3430_AUTO_GPT8_MASK |
|
|
|
|
OMAP3430_AUTO_GPT7_MASK |
|
|
|
|
OMAP3430_AUTO_GPT6_MASK |
|
|
|
|
OMAP3430_AUTO_GPT5_MASK |
|
|
|
|
OMAP3430_AUTO_GPT4_MASK |
|
|
|
|
OMAP3430_AUTO_GPT3_MASK |
|
|
|
|
OMAP3430_AUTO_GPT2_MASK |
|
|
|
|
OMAP3430_AUTO_MCBSP4_MASK |
|
|
|
|
OMAP3430_AUTO_MCBSP3_MASK |
|
|
|
|
OMAP3430_AUTO_MCBSP2_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
OMAP3430_PER_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
|
|
|
|
if (omap_rev() > OMAP3430_REV_ES1_0) {
|
|
|
|
cm_write_mod_reg(
|
2010-05-19 00:47:24 +00:00
|
|
|
OMAP3430ES2_AUTO_USBHOST_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
OMAP3430ES2_USBHOST_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
}
|
|
|
|
|
2010-05-19 00:40:23 +00:00
|
|
|
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
|
2009-10-23 16:03:49 +00:00
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
/*
|
|
|
|
* Set all plls to autoidle. This is needed until autoidle is
|
|
|
|
* enabled by clockfw
|
|
|
|
*/
|
|
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
|
|
|
|
OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
|
|
|
|
cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
|
|
|
|
MPU_MOD,
|
|
|
|
CM_AUTOIDLE2);
|
|
|
|
cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
|
|
|
|
(1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
|
|
|
|
PLL_MOD,
|
|
|
|
CM_AUTOIDLE);
|
|
|
|
cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
|
|
|
|
PLL_MOD,
|
|
|
|
CM_AUTOIDLE2);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable control of expternal oscillator through
|
|
|
|
* sys_clkreq. In the long run clock framework should
|
|
|
|
* take care of this.
|
|
|
|
*/
|
|
|
|
prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
|
|
|
|
1 << OMAP_AUTOEXTCLKMODE_SHIFT,
|
|
|
|
OMAP3430_GR_MOD,
|
|
|
|
OMAP3_PRM_CLKSRC_CTRL_OFFSET);
|
|
|
|
|
|
|
|
/* setup wakup source */
|
2010-05-19 00:40:23 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
|
|
|
|
OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
WKUP_MOD, PM_WKEN);
|
|
|
|
/* No need to write EN_IO, that is always enabled */
|
2010-05-19 00:40:23 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPT1_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPT12_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
/* For some reason IO doesn't generate wakeup event even if
|
|
|
|
* it is selected to mpu wakeup goup */
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
|
2009-05-28 17:56:16 +00:00
|
|
|
OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
|
2008-11-25 19:48:24 +00:00
|
|
|
|
2009-12-22 09:37:50 +00:00
|
|
|
/* Enable PM_WKEN to support DSS LPR */
|
2010-05-19 00:47:24 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
|
2009-12-22 09:37:50 +00:00
|
|
|
OMAP3430_DSS_MOD, PM_WKEN);
|
|
|
|
|
2009-10-22 21:48:13 +00:00
|
|
|
/* Enable wakeups in PER */
|
2010-05-19 00:40:23 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
|
|
|
|
OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
|
|
|
|
OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
|
|
|
|
OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
|
|
|
|
OMAP3430_EN_MCBSP4_MASK,
|
2009-10-22 21:48:13 +00:00
|
|
|
OMAP3430_PER_MOD, PM_WKEN);
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 15:53:08 +00:00
|
|
|
/* and allow them to wake up MPU */
|
2010-05-19 00:40:23 +00:00
|
|
|
prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO3_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO4_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO5_MASK |
|
|
|
|
OMAP3430_GRPSEL_GPIO6_MASK |
|
|
|
|
OMAP3430_GRPSEL_UART3_MASK |
|
|
|
|
OMAP3430_GRPSEL_MCBSP2_MASK |
|
|
|
|
OMAP3430_GRPSEL_MCBSP3_MASK |
|
|
|
|
OMAP3430_GRPSEL_MCBSP4_MASK,
|
OMAP3: PM: Enable GPIO module-level wakeups
Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups. This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.
In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.
NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.
This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off. When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.
To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:
# echo 3 > /debug/pm_debug/core_pwrdm/suspend
This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.
Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO (gpio 102, in PER)
Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_Management
Reported-by: Mike Chan <mikechan@google.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2009-09-10 15:53:08 +00:00
|
|
|
OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
|
|
|
2009-05-05 23:34:25 +00:00
|
|
|
/* Don't attach IVA interrupts */
|
|
|
|
prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
|
|
prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
|
|
prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
|
|
|
2009-04-27 23:14:54 +00:00
|
|
|
/* Clear any pending 'reset' flags */
|
2010-01-27 03:12:51 +00:00
|
|
|
prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
|
|
|
|
prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
|
2009-04-27 23:14:54 +00:00
|
|
|
|
2009-04-27 14:50:23 +00:00
|
|
|
/* Clear any pending PRCM interrupts */
|
|
|
|
prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
|
|
|
|
|
2008-11-25 19:48:24 +00:00
|
|
|
omap3_iva_idle();
|
2009-04-28 22:27:44 +00:00
|
|
|
omap3_d2d_idle();
|
2009-05-28 17:56:16 +00:00
|
|
|
}
|
|
|
|
|
2009-10-06 21:25:09 +00:00
|
|
|
void omap3_pm_off_mode_enable(int enable)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
u32 state;
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
state = PWRDM_POWER_OFF;
|
|
|
|
else
|
|
|
|
state = PWRDM_POWER_RET;
|
|
|
|
|
2010-01-28 17:46:43 +00:00
|
|
|
#ifdef CONFIG_CPU_IDLE
|
|
|
|
omap3_cpuidle_update_states();
|
|
|
|
#endif
|
|
|
|
|
2009-10-06 21:25:09 +00:00
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
pwrst->next_state = state;
|
|
|
|
set_pwrdm_state(pwrst->pwrdm, state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-11-26 10:26:24 +00:00
|
|
|
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (pwrst->pwrdm == pwrdm)
|
|
|
|
return pwrst->next_state;
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
|
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
list_for_each_entry(pwrst, &pwrst_list, node) {
|
|
|
|
if (pwrst->pwrdm == pwrdm) {
|
|
|
|
pwrst->next_state = state;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2008-10-15 15:13:47 +00:00
|
|
|
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
|
|
|
struct power_state *pwrst;
|
|
|
|
|
|
|
|
if (!pwrdm->pwrsts)
|
|
|
|
return 0;
|
|
|
|
|
2009-08-22 13:20:26 +00:00
|
|
|
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
|
2009-05-28 17:56:16 +00:00
|
|
|
if (!pwrst)
|
|
|
|
return -ENOMEM;
|
|
|
|
pwrst->pwrdm = pwrdm;
|
|
|
|
pwrst->next_state = PWRDM_POWER_RET;
|
|
|
|
list_add(&pwrst->node, &pwrst_list);
|
|
|
|
|
|
|
|
if (pwrdm_has_hdwr_sar(pwrdm))
|
|
|
|
pwrdm_enable_hdwr_sar(pwrdm);
|
|
|
|
|
|
|
|
return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable hw supervised mode for all clockdomains if it's
|
|
|
|
* supported. Initiate sleep transition for other clockdomains, if
|
|
|
|
* they are not used
|
|
|
|
*/
|
2008-10-15 15:13:47 +00:00
|
|
|
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
|
2009-05-28 17:56:16 +00:00
|
|
|
{
|
OMAP clockdomains: add usecounting for wakeup and sleep dependencies
Add usecounting for wakeup and sleep dependencies. In the current
situation, if several functions add dependencies on the same
clockdomains, when the first dependency removal function is called,
the dependency will be incorrectly removed from the hardware.
Add clkdm_clear_all_wkdeps() and clkdm_clear_all_sleepdeps(), which
provide a fast and usecounting-consistent way to clear all hardware
clockdomain dependencies, since accesses to these registers can be
quite slow. pm{2,3}4xx.c has been updated to use these new functions.
The original version of this patch did not touch these files, which
previously wrote directly to the wkdep registers, and thus confused
the usecounting code. This problem was found by Kevin Hilman
<khilman@deeprootsystems.com>.
N.B.: This patch introduces one significant functional difference over
the previous pm34xx.c code: sleepdeps are now cleared during
clockdomain initialization, whereas previously they were left
untouched. This has been tested by Kevin and confirmed to work.
The original version of this patch also did not take into
consideration that some clockdomains do not have sleep or wakeup
dependency sources, which caused NULL pointer dereferences. This
problem was debugged and fixed by Kevin Hilman
<khilman@deeprootsystems.com>.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Jouni Högander <jouni.hogander@nokia.com>
2010-01-27 03:13:01 +00:00
|
|
|
clkdm_clear_all_wkdeps(clkdm);
|
|
|
|
clkdm_clear_all_sleepdeps(clkdm);
|
|
|
|
|
2009-05-28 17:56:16 +00:00
|
|
|
if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
|
|
|
|
omap2_clkdm_allow_idle(clkdm);
|
|
|
|
else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
|
|
|
|
atomic_read(&clkdm->usecount) == 0)
|
|
|
|
omap2_clkdm_sleep(clkdm);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-09-26 12:19:14 +00:00
|
|
|
void omap_push_sram_idle(void)
|
|
|
|
{
|
|
|
|
_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
|
|
|
|
omap34xx_cpu_suspend_sz);
|
2008-10-13 10:15:00 +00:00
|
|
|
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
|
|
|
|
_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
|
|
|
|
save_secure_ram_context_sz);
|
2008-09-26 12:19:14 +00:00
|
|
|
}
|
|
|
|
|
2009-06-10 16:02:25 +00:00
|
|
|
static int __init omap3_pm_init(void)
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2009-05-28 17:56:16 +00:00
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{
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struct power_state *pwrst, *tmp;
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2010-01-27 03:12:59 +00:00
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struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
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2009-05-28 17:56:16 +00:00
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int ret;
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if (!cpu_is_omap34xx())
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return -ENODEV;
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printk(KERN_ERR "Power Management for TI OMAP3.\n");
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/* XXX prcm_setup_regs needs to be before enabling hw
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* supervised mode for powerdomains */
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prcm_setup_regs();
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ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
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(irq_handler_t)prcm_interrupt_handler,
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IRQF_DISABLED, "prcm", NULL);
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if (ret) {
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printk(KERN_ERR "request_irq failed to register for 0x%x\n",
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INT_34XX_PRCM_MPU_IRQ);
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goto err1;
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}
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2008-10-15 15:13:47 +00:00
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ret = pwrdm_for_each(pwrdms_setup, NULL);
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2009-05-28 17:56:16 +00:00
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if (ret) {
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printk(KERN_ERR "Failed to setup powerdomains\n");
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goto err2;
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}
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2008-10-15 15:13:47 +00:00
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(void) clkdm_for_each(clkdms_setup, NULL);
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2009-05-28 17:56:16 +00:00
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mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
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if (mpu_pwrdm == NULL) {
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printk(KERN_ERR "Failed to get mpu_pwrdm\n");
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goto err2;
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}
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2008-09-26 12:19:22 +00:00
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neon_pwrdm = pwrdm_lookup("neon_pwrdm");
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per_pwrdm = pwrdm_lookup("per_pwrdm");
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core_pwrdm = pwrdm_lookup("core_pwrdm");
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2008-12-11 14:46:57 +00:00
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cam_pwrdm = pwrdm_lookup("cam_pwrdm");
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2008-09-26 12:19:22 +00:00
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2010-01-27 03:12:59 +00:00
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neon_clkdm = clkdm_lookup("neon_clkdm");
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mpu_clkdm = clkdm_lookup("mpu_clkdm");
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per_clkdm = clkdm_lookup("per_clkdm");
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core_clkdm = clkdm_lookup("core_clkdm");
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2008-09-26 12:19:14 +00:00
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omap_push_sram_idle();
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2009-06-24 18:39:18 +00:00
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#ifdef CONFIG_SUSPEND
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2009-05-28 17:56:16 +00:00
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suspend_set_ops(&omap_pm_ops);
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2009-06-24 18:39:18 +00:00
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#endif /* CONFIG_SUSPEND */
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2009-05-28 17:56:16 +00:00
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pm_idle = omap3_pm_idle;
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2008-09-26 08:04:20 +00:00
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omap3_idle_init();
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2009-05-28 17:56:16 +00:00
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2010-01-27 03:12:59 +00:00
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clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
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2008-10-13 10:15:00 +00:00
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
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omap3_secure_ram_storage =
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kmalloc(0x803F, GFP_KERNEL);
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if (!omap3_secure_ram_storage)
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printk(KERN_ERR "Memory allocation failed when"
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"allocating for secure sram context\n");
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2008-12-12 09:20:05 +00:00
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local_irq_disable();
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local_fiq_disable();
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omap_dma_global_context_save();
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omap3_save_secure_ram_context(PWRDM_POWER_ON);
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omap_dma_global_context_restore();
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local_irq_enable();
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local_fiq_enable();
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2008-10-13 10:15:00 +00:00
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}
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2008-12-12 09:20:05 +00:00
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omap3_save_scratchpad_contents();
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2009-05-28 17:56:16 +00:00
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err1:
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return ret;
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err2:
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free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
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list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
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list_del(&pwrst->node);
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kfree(pwrst);
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}
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return ret;
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}
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late_initcall(omap3_pm_init);
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