2019-06-04 08:11:33 +00:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2013-01-18 09:42:18 +00:00
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/*
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2015-02-21 09:39:32 +00:00
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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2013-01-18 09:42:18 +00:00
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*/
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#ifndef __ASM_ARC_ENTRY_H
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#define __ASM_ARC_ENTRY_H
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#include <asm/unistd.h> /* For NR_syscalls defination */
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#include <asm/arcregs.h>
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#include <asm/ptrace.h>
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2013-02-11 14:22:57 +00:00
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#include <asm/processor.h> /* For VMALLOC_START */
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2013-07-26 22:29:40 +00:00
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#include <asm/mmu.h>
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2013-01-18 09:42:18 +00:00
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 13:00:41 +00:00
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#ifdef CONFIG_ISA_ARCOMPACT
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2015-02-21 09:39:32 +00:00
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#include <asm/entry-compact.h> /* ISA specific bits */
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ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
- SMP configurations of upto 4 cores with coherency
- Optional L2 Cache and IO-Coherency
- Revised Interrupt Architecture (multiple priorites, reg banks,
auto stack switch, auto regfile save/restore)
- MMUv4 (PIPT dcache, Huge Pages)
- Instructions for
* 64bit load/store: LDD, STD
* Hardware assisted divide/remainder: DIV, REM
* Function prologue/epilogue: ENTER_S, LEAVE_S
* IRQ enable/disable: CLRI, SETI
* pop count: FFS, FLS
* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-13 13:00:41 +00:00
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#else
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#include <asm/entry-arcv2.h>
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#endif
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2015-02-21 09:39:32 +00:00
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2013-01-18 09:42:18 +00:00
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/* Note on the LD/ST addr modes with addr reg wback
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*
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* LD.a same as LD.aw
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*
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* LD.a reg1, [reg2, x] => Pre Incr
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* Eff Addr for load = [reg2 + x]
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*
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* LD.ab reg1, [reg2, x] => Post Incr
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* Eff Addr for load = [reg2]
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*/
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2013-05-28 07:54:43 +00:00
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.macro PUSH reg
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st.a \reg, [sp, -4]
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.endm
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.macro PUSHAX aux
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lr r9, [\aux]
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PUSH r9
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.endm
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.macro POP reg
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ld.ab \reg, [sp, 4]
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.endm
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.macro POPAX aux
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POP r9
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sr r9, [\aux]
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.endm
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2013-01-18 09:42:18 +00:00
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/*--------------------------------------------------------------
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2013-05-28 07:54:43 +00:00
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* Helpers to save/restore Scratch Regs:
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* used by Interrupt/Exception Prologue/Epilogue
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2013-01-18 09:42:18 +00:00
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*-------------------------------------------------------------*/
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2013-05-28 07:54:43 +00:00
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.macro SAVE_R0_TO_R12
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PUSH r0
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PUSH r1
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PUSH r2
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PUSH r3
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PUSH r4
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PUSH r5
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PUSH r6
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PUSH r7
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PUSH r8
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PUSH r9
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PUSH r10
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PUSH r11
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PUSH r12
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.endm
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.macro RESTORE_R12_TO_R0
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POP r12
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POP r11
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POP r10
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POP r9
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POP r8
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POP r7
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POP r6
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POP r5
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POP r4
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POP r3
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POP r2
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POP r1
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POP r0
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ARC: pt_regs update #4: r25 saved/restored unconditionally
(This is a VERY IMP change for low level interrupt/exception handling)
-----------------------------------------------------------------------
WHAT
-----------------------------------------------------------------------
* User 25 now saved in pt_regs->user_r25 (vs. tsk->thread_info.user_r25)
* This allows Low level interrupt code to unconditionally save r25
(vs. the prev version which would only do it for U->K transition).
Ofcourse for nested interrupts, only the pt_regs->user_r25 of
bottom-most frame is useful.
* simplifies the interrupt prologue/epilogue
* Needed for ARCv2 ISA code and done here to keep design similar with
ARCompact event handling
-----------------------------------------------------------------------
WHY
-------------------------------------------------------------------------
With CONFIG_ARC_CURR_IN_REG, r25 is used to cache "current" task pointer
in kernel mode. So when entering kernel mode from User Mode
- user r25 is specially safe-kept (it being a callee reg is NOT part of
pt_regs which are saved by default on each interrupt/trap/exception)
- r25 loaded with current task pointer.
Further, if interrupt was taken in kernel mode, this is skipped since we
know that r25 already has valid "current" pointer.
With 2 level of interrupts in ARCompact ISA, detecting this is difficult
but still possible, since we could be in kernel mode but r25 not already saved
(in fact the stack itself might not have been switched).
A. User mode
B. L1 IRQ taken
C. L2 IRQ taken (while on 1st line of L1 ISR)
So in #C, although in kernel mode, r25 not saved (infact SP not
switched at all)
Given that ARcompact has manual stack switching, we could use a bit of
trickey - The low level code would make sure that SP is only set to kernel
mode value at the very end (after saving r25). So a non kernel mode SP,
even if in kernel mode, meant r25 was NOT saved.
The same paradigm won't work in ARCv2 ISA since SP is auto-switched so
it's setting can't be delayed/constrained.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2013-05-28 08:20:41 +00:00
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2013-01-18 09:42:18 +00:00
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.endm
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/*--------------------------------------------------------------
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2013-05-28 07:54:43 +00:00
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* Helpers to save/restore callee-saved regs:
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* used by several macros below
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2013-01-18 09:42:18 +00:00
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*-------------------------------------------------------------*/
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2013-05-28 07:54:43 +00:00
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.macro SAVE_R13_TO_R24
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PUSH r13
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PUSH r14
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PUSH r15
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PUSH r16
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PUSH r17
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PUSH r18
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PUSH r19
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PUSH r20
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PUSH r21
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PUSH r22
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PUSH r23
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PUSH r24
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.endm
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.macro RESTORE_R24_TO_R13
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POP r24
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POP r23
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POP r22
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POP r21
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POP r20
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POP r19
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POP r18
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POP r17
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POP r16
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POP r15
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POP r14
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POP r13
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2013-01-18 09:42:18 +00:00
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.endm
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/*--------------------------------------------------------------
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2013-05-28 07:54:43 +00:00
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* Collect User Mode callee regs as struct callee_regs - needed by
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* fork/do_signal/unaligned-access-emulation.
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* (By default only scratch regs are saved on entry to kernel)
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*
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* Special handling for r25 if used for caching Task Pointer.
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* It would have been saved in task->thread.user_r25 already, but to keep
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* the interface same it is copied into regular r25 placeholder in
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* struct callee_regs.
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2013-01-18 09:42:18 +00:00
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*-------------------------------------------------------------*/
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.macro SAVE_CALLEE_SAVED_USER
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2013-05-28 07:54:43 +00:00
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ARCv2: STAR 9000808988: signals involving Delay Slot
Reported by Anton as LTP:munmap01 failing with Illegal Instruction
Exception.
--------------------->8--------------------------------------
mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
munmap(0x200d2000, 24576) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
---
potentially unexpected fatal signal 4.
Path: /munmap01
CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
[ECR ]: 0x00020100 => Illegal Insn
[EFA ]: 0x0001354c
[BLINK ]: 0x200515d4
[ERET ]: 0x1354c
@off 0x1354c in [/munmap01]
VMA: 0x00010000 to 0x00018000
[STAT32]: 0x800802c0
...
--------------------->8--------------------------------------
The issue was
1. munmap01 accessed unmapped memory (on purpose) with signal handler
installed for SIGSEGV
2. The faulting instruction happened to be in Delay Slot
00011864 <main>:
11908: bl.d 13284 <tst_resm>
1190c: stb r16,[r2]
3. kernel sets up the reg file for signal handler and correctly clears
the DE bit in pt_regs->status32 placeholder
4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
and it over-writes the above with orig/stale value of status32
5. After RTIE, userspace signal handler executes a non branch
instruction with DE bit set, triggering Illegal Instruction Exception.
Reported-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-07 08:42:13 +00:00
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mov r12, sp ; save SP as ref to pt_regs
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2013-05-28 07:54:43 +00:00
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SAVE_R13_TO_R24
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2013-02-11 14:22:57 +00:00
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#ifdef CONFIG_ARC_CURR_IN_REG
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ARCv2: STAR 9000808988: signals involving Delay Slot
Reported by Anton as LTP:munmap01 failing with Illegal Instruction
Exception.
--------------------->8--------------------------------------
mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
munmap(0x200d2000, 24576) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
---
potentially unexpected fatal signal 4.
Path: /munmap01
CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
[ECR ]: 0x00020100 => Illegal Insn
[EFA ]: 0x0001354c
[BLINK ]: 0x200515d4
[ERET ]: 0x1354c
@off 0x1354c in [/munmap01]
VMA: 0x00010000 to 0x00018000
[STAT32]: 0x800802c0
...
--------------------->8--------------------------------------
The issue was
1. munmap01 accessed unmapped memory (on purpose) with signal handler
installed for SIGSEGV
2. The faulting instruction happened to be in Delay Slot
00011864 <main>:
11908: bl.d 13284 <tst_resm>
1190c: stb r16,[r2]
3. kernel sets up the reg file for signal handler and correctly clears
the DE bit in pt_regs->status32 placeholder
4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
and it over-writes the above with orig/stale value of status32
5. After RTIE, userspace signal handler executes a non branch
instruction with DE bit set, triggering Illegal Instruction Exception.
Reported-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-07 08:42:13 +00:00
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; Retrieve orig r25 and save it with rest of callee_regs
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2016-08-16 07:55:35 +00:00
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ld r12, [r12, PT_user_r25]
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ARCv2: STAR 9000808988: signals involving Delay Slot
Reported by Anton as LTP:munmap01 failing with Illegal Instruction
Exception.
--------------------->8--------------------------------------
mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
munmap(0x200d2000, 24576) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
---
potentially unexpected fatal signal 4.
Path: /munmap01
CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
[ECR ]: 0x00020100 => Illegal Insn
[EFA ]: 0x0001354c
[BLINK ]: 0x200515d4
[ERET ]: 0x1354c
@off 0x1354c in [/munmap01]
VMA: 0x00010000 to 0x00018000
[STAT32]: 0x800802c0
...
--------------------->8--------------------------------------
The issue was
1. munmap01 accessed unmapped memory (on purpose) with signal handler
installed for SIGSEGV
2. The faulting instruction happened to be in Delay Slot
00011864 <main>:
11908: bl.d 13284 <tst_resm>
1190c: stb r16,[r2]
3. kernel sets up the reg file for signal handler and correctly clears
the DE bit in pt_regs->status32 placeholder
4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
and it over-writes the above with orig/stale value of status32
5. After RTIE, userspace signal handler executes a non branch
instruction with DE bit set, triggering Illegal Instruction Exception.
Reported-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-07 08:42:13 +00:00
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PUSH r12
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2013-02-11 14:22:57 +00:00
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#else
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2013-05-28 07:54:43 +00:00
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PUSH r25
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2013-02-11 14:22:57 +00:00
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#endif
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2013-01-18 09:42:18 +00:00
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.endm
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/*--------------------------------------------------------------
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2013-05-28 07:54:43 +00:00
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* Save kernel Mode callee regs at the time of Contect Switch.
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*
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* Special handling for r25 if used for caching Task Pointer.
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* Kernel simply skips saving it since it will be loaded with
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* incoming task pointer anyways
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2013-01-18 09:42:18 +00:00
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*-------------------------------------------------------------*/
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.macro SAVE_CALLEE_SAVED_KERNEL
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2013-05-28 07:54:43 +00:00
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SAVE_R13_TO_R24
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2013-02-11 14:22:57 +00:00
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#ifdef CONFIG_ARC_CURR_IN_REG
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2013-05-27 16:13:41 +00:00
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sub sp, sp, 4
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2013-02-11 14:22:57 +00:00
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#else
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2013-05-28 07:54:43 +00:00
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PUSH r25
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2013-02-11 14:22:57 +00:00
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#endif
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2013-01-18 09:42:18 +00:00
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.endm
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/*--------------------------------------------------------------
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2013-05-28 07:54:43 +00:00
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* Opposite of SAVE_CALLEE_SAVED_KERNEL
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2013-01-18 09:42:18 +00:00
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*-------------------------------------------------------------*/
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.macro RESTORE_CALLEE_SAVED_KERNEL
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2013-02-11 14:22:57 +00:00
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#ifdef CONFIG_ARC_CURR_IN_REG
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2013-05-27 16:13:41 +00:00
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add sp, sp, 4 /* skip usual r25 placeholder */
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2013-02-11 14:22:57 +00:00
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#else
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2013-05-28 07:54:43 +00:00
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POP r25
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2013-02-11 14:22:57 +00:00
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#endif
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2013-05-28 07:54:43 +00:00
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RESTORE_R24_TO_R13
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2013-01-18 09:42:18 +00:00
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.endm
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2013-01-18 09:42:19 +00:00
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/*--------------------------------------------------------------
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2013-05-28 07:54:43 +00:00
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* Opposite of SAVE_CALLEE_SAVED_USER
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*
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* ptrace tracer or unaligned-access fixup might have changed a user mode
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* callee reg which is saved back to usual r25 storage location
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2013-01-18 09:42:19 +00:00
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*-------------------------------------------------------------*/
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.macro RESTORE_CALLEE_SAVED_USER
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#ifdef CONFIG_ARC_CURR_IN_REG
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ARCv2: STAR 9000808988: signals involving Delay Slot
Reported by Anton as LTP:munmap01 failing with Illegal Instruction
Exception.
--------------------->8--------------------------------------
mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
munmap(0x200d2000, 24576) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
---
potentially unexpected fatal signal 4.
Path: /munmap01
CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
[ECR ]: 0x00020100 => Illegal Insn
[EFA ]: 0x0001354c
[BLINK ]: 0x200515d4
[ERET ]: 0x1354c
@off 0x1354c in [/munmap01]
VMA: 0x00010000 to 0x00018000
[STAT32]: 0x800802c0
...
--------------------->8--------------------------------------
The issue was
1. munmap01 accessed unmapped memory (on purpose) with signal handler
installed for SIGSEGV
2. The faulting instruction happened to be in Delay Slot
00011864 <main>:
11908: bl.d 13284 <tst_resm>
1190c: stb r16,[r2]
3. kernel sets up the reg file for signal handler and correctly clears
the DE bit in pt_regs->status32 placeholder
4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
and it over-writes the above with orig/stale value of status32
5. After RTIE, userspace signal handler executes a non branch
instruction with DE bit set, triggering Illegal Instruction Exception.
Reported-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-07 08:42:13 +00:00
|
|
|
POP r12
|
2013-01-18 09:42:19 +00:00
|
|
|
#else
|
2013-05-28 07:54:43 +00:00
|
|
|
POP r25
|
2013-01-18 09:42:19 +00:00
|
|
|
#endif
|
2013-05-28 07:54:43 +00:00
|
|
|
RESTORE_R24_TO_R13
|
ARCv2: STAR 9000808988: signals involving Delay Slot
Reported by Anton as LTP:munmap01 failing with Illegal Instruction
Exception.
--------------------->8--------------------------------------
mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
munmap(0x200d2000, 24576) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
---
potentially unexpected fatal signal 4.
Path: /munmap01
CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
[ECR ]: 0x00020100 => Illegal Insn
[EFA ]: 0x0001354c
[BLINK ]: 0x200515d4
[ERET ]: 0x1354c
@off 0x1354c in [/munmap01]
VMA: 0x00010000 to 0x00018000
[STAT32]: 0x800802c0
...
--------------------->8--------------------------------------
The issue was
1. munmap01 accessed unmapped memory (on purpose) with signal handler
installed for SIGSEGV
2. The faulting instruction happened to be in Delay Slot
00011864 <main>:
11908: bl.d 13284 <tst_resm>
1190c: stb r16,[r2]
3. kernel sets up the reg file for signal handler and correctly clears
the DE bit in pt_regs->status32 placeholder
4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
and it over-writes the above with orig/stale value of status32
5. After RTIE, userspace signal handler executes a non branch
instruction with DE bit set, triggering Illegal Instruction Exception.
Reported-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-07 08:42:13 +00:00
|
|
|
|
|
|
|
|
; SP is back to start of pt_regs
|
|
|
|
|
#ifdef CONFIG_ARC_CURR_IN_REG
|
2016-08-16 07:55:35 +00:00
|
|
|
st r12, [sp, PT_user_r25]
|
ARCv2: STAR 9000808988: signals involving Delay Slot
Reported by Anton as LTP:munmap01 failing with Illegal Instruction
Exception.
--------------------->8--------------------------------------
mmap2(NULL, 24576, PROT_READ|PROT_WRITE, MAP_SHARED, 3, 0) = 0x200d2000
munmap(0x200d2000, 24576) = 0
--- SIGSEGV {si_signo=SIGSEGV, si_code=SEGV_MAPERR, si_addr=0x200d2000}
---
potentially unexpected fatal signal 4.
Path: /munmap01
CPU: 0 PID: 61 Comm: munmap01 Not tainted 3.13.0-g5d5c46d9a556 #8
task: 9f1a8000 ti: 9f154000 task.ti: 9f154000
[ECR ]: 0x00020100 => Illegal Insn
[EFA ]: 0x0001354c
[BLINK ]: 0x200515d4
[ERET ]: 0x1354c
@off 0x1354c in [/munmap01]
VMA: 0x00010000 to 0x00018000
[STAT32]: 0x800802c0
...
--------------------->8--------------------------------------
The issue was
1. munmap01 accessed unmapped memory (on purpose) with signal handler
installed for SIGSEGV
2. The faulting instruction happened to be in Delay Slot
00011864 <main>:
11908: bl.d 13284 <tst_resm>
1190c: stb r16,[r2]
3. kernel sets up the reg file for signal handler and correctly clears
the DE bit in pt_regs->status32 placeholder
4. However RESTORE_CALLEE_SAVED_USER macro is not adjusted for ARCv2,
and it over-writes the above with orig/stale value of status32
5. After RTIE, userspace signal handler executes a non branch
instruction with DE bit set, triggering Illegal Instruction Exception.
Reported-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2014-10-07 08:42:13 +00:00
|
|
|
#endif
|
2013-01-18 09:42:19 +00:00
|
|
|
.endm
|
|
|
|
|
|
2013-01-18 09:42:18 +00:00
|
|
|
/*--------------------------------------------------------------
|
|
|
|
|
* Super FAST Restore callee saved regs by simply re-adjusting SP
|
|
|
|
|
*-------------------------------------------------------------*/
|
|
|
|
|
.macro DISCARD_CALLEE_SAVED_USER
|
2013-05-27 16:13:41 +00:00
|
|
|
add sp, sp, SZ_CALLEE_REGS
|
2013-01-18 09:42:18 +00:00
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------
|
|
|
|
|
* given a tsk struct, get to the base of it's kernel mode stack
|
|
|
|
|
* tsk->thread_info is really a PAGE, whose bottom hoists stack
|
|
|
|
|
* which grows upwards towards thread_info
|
|
|
|
|
*------------------------------------------------------------*/
|
|
|
|
|
|
|
|
|
|
.macro GET_TSK_STACK_BASE tsk, out
|
|
|
|
|
|
|
|
|
|
/* Get task->thread_info (this is essentially start of a PAGE) */
|
|
|
|
|
ld \out, [\tsk, TASK_THREAD_INFO]
|
|
|
|
|
|
|
|
|
|
/* Go to end of page where stack begins (grows upwards) */
|
2013-05-28 04:04:45 +00:00
|
|
|
add2 \out, \out, (THREAD_SIZE)/4
|
2013-01-18 09:42:18 +00:00
|
|
|
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* @reg [OUT] thread_info->flags of "current"
|
|
|
|
|
*/
|
|
|
|
|
.macro GET_CURR_THR_INFO_FLAGS reg
|
|
|
|
|
GET_CURR_THR_INFO_FROM_SP \reg
|
|
|
|
|
ld \reg, [\reg, THREAD_INFO_FLAGS]
|
|
|
|
|
.endm
|
|
|
|
|
|
2013-01-18 09:42:23 +00:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
|
|
|
|
|
|
/*-------------------------------------------------
|
|
|
|
|
* Retrieve the current running task on this CPU
|
|
|
|
|
* 1. Determine curr CPU id.
|
|
|
|
|
* 2. Use it to index into _current_task[ ]
|
|
|
|
|
*/
|
|
|
|
|
.macro GET_CURR_TASK_ON_CPU reg
|
|
|
|
|
GET_CPU_ID \reg
|
|
|
|
|
ld.as \reg, [@_current_task, \reg]
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
/*-------------------------------------------------
|
|
|
|
|
* Save a new task as the "current" task on this CPU
|
|
|
|
|
* 1. Determine curr CPU id.
|
|
|
|
|
* 2. Use it to index into _current_task[ ]
|
|
|
|
|
*
|
|
|
|
|
* Coded differently than GET_CURR_TASK_ON_CPU (which uses LD.AS)
|
|
|
|
|
* because ST r0, [r1, offset] can ONLY have s9 @offset
|
|
|
|
|
* while LD can take s9 (4 byte insn) or LIMM (8 byte insn)
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
.macro SET_CURR_TASK_ON_CPU tsk, tmp
|
|
|
|
|
GET_CPU_ID \tmp
|
|
|
|
|
add2 \tmp, @_current_task, \tmp
|
|
|
|
|
st \tsk, [\tmp]
|
|
|
|
|
#ifdef CONFIG_ARC_CURR_IN_REG
|
|
|
|
|
mov r25, \tsk
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#else /* Uniprocessor implementation of macros */
|
|
|
|
|
|
2013-01-18 09:42:18 +00:00
|
|
|
.macro GET_CURR_TASK_ON_CPU reg
|
|
|
|
|
ld \reg, [@_current_task]
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
.macro SET_CURR_TASK_ON_CPU tsk, tmp
|
|
|
|
|
st \tsk, [@_current_task]
|
2013-02-11 14:22:57 +00:00
|
|
|
#ifdef CONFIG_ARC_CURR_IN_REG
|
|
|
|
|
mov r25, \tsk
|
|
|
|
|
#endif
|
2013-01-18 09:42:18 +00:00
|
|
|
.endm
|
|
|
|
|
|
2013-01-18 09:42:23 +00:00
|
|
|
#endif /* SMP / UNI */
|
|
|
|
|
|
2013-01-18 09:42:18 +00:00
|
|
|
/* ------------------------------------------------------------------
|
|
|
|
|
* Get the ptr to some field of Current Task at @off in task struct
|
2013-02-11 14:22:57 +00:00
|
|
|
* -Uses r25 for Current task ptr if that is enabled
|
2013-01-18 09:42:18 +00:00
|
|
|
*/
|
|
|
|
|
|
2013-02-11 14:22:57 +00:00
|
|
|
#ifdef CONFIG_ARC_CURR_IN_REG
|
|
|
|
|
|
|
|
|
|
.macro GET_CURR_TASK_FIELD_PTR off, reg
|
|
|
|
|
add \reg, r25, \off
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#else
|
|
|
|
|
|
2013-01-18 09:42:18 +00:00
|
|
|
.macro GET_CURR_TASK_FIELD_PTR off, reg
|
|
|
|
|
GET_CURR_TASK_ON_CPU \reg
|
|
|
|
|
add \reg, \reg, \off
|
|
|
|
|
.endm
|
|
|
|
|
|
2013-02-11 14:22:57 +00:00
|
|
|
#endif /* CONFIG_ARC_CURR_IN_REG */
|
|
|
|
|
|
2013-01-18 09:42:18 +00:00
|
|
|
#endif /* __ASM_ARC_ENTRY_H */
|