2022-05-16 08:25:01 +00:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas RZ/N1 Real Time Clock interface for Linux
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*
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* Copyright:
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* - 2014 Renesas Electronics Europe Limited
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* - 2022 Schneider Electric
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*
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* Authors:
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* - Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
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* - Miquel Raynal <miquel.raynal@bootlin.com>
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*/
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#include <linux/bcd.h>
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#include <linux/init.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/rtc.h>
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#define RZN1_RTC_CTL0 0x00
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#define RZN1_RTC_CTL0_SLSB_SUBU 0
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#define RZN1_RTC_CTL0_SLSB_SCMP BIT(4)
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#define RZN1_RTC_CTL0_AMPM BIT(5)
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#define RZN1_RTC_CTL0_CE BIT(7)
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#define RZN1_RTC_CTL1 0x04
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#define RZN1_RTC_CTL1_ALME BIT(4)
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#define RZN1_RTC_CTL2 0x08
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#define RZN1_RTC_CTL2_WAIT BIT(0)
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#define RZN1_RTC_CTL2_WST BIT(1)
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#define RZN1_RTC_CTL2_WUST BIT(5)
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#define RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST)
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#define RZN1_RTC_SEC 0x14
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#define RZN1_RTC_MIN 0x18
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#define RZN1_RTC_HOUR 0x1c
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#define RZN1_RTC_WEEK 0x20
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#define RZN1_RTC_DAY 0x24
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#define RZN1_RTC_MONTH 0x28
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#define RZN1_RTC_YEAR 0x2c
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#define RZN1_RTC_SUBU 0x38
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#define RZN1_RTC_SUBU_DEV BIT(7)
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#define RZN1_RTC_SUBU_DECR BIT(6)
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#define RZN1_RTC_ALM 0x40
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#define RZN1_RTC_ALH 0x44
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#define RZN1_RTC_ALW 0x48
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#define RZN1_RTC_SECC 0x4c
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#define RZN1_RTC_MINC 0x50
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#define RZN1_RTC_HOURC 0x54
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#define RZN1_RTC_WEEKC 0x58
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#define RZN1_RTC_DAYC 0x5c
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#define RZN1_RTC_MONTHC 0x60
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#define RZN1_RTC_YEARC 0x64
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struct rzn1_rtc {
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struct rtc_device *rtcdev;
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void __iomem *base;
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};
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static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm)
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{
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tm->tm_sec = readl(rtc->base + RZN1_RTC_SECC);
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tm->tm_min = readl(rtc->base + RZN1_RTC_MINC);
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tm->tm_hour = readl(rtc->base + RZN1_RTC_HOURC);
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tm->tm_wday = readl(rtc->base + RZN1_RTC_WEEKC);
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tm->tm_mday = readl(rtc->base + RZN1_RTC_DAYC);
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tm->tm_mon = readl(rtc->base + RZN1_RTC_MONTHC);
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tm->tm_year = readl(rtc->base + RZN1_RTC_YEARC);
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}
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static unsigned int rzn1_rtc_tm_to_wday(struct rtc_time *tm)
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{
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time64_t time;
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unsigned int days;
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u32 secs;
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time = rtc_tm_to_time64(tm);
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days = div_s64_rem(time, 86400, &secs);
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/* day of the week, 1970-01-01 was a Thursday */
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return (days + 4) % 7;
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}
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static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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u32 val, secs;
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/*
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* The RTC was not started or is stopped and thus does not carry the
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* proper time/date.
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*/
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val = readl(rtc->base + RZN1_RTC_CTL2);
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if (val & RZN1_RTC_CTL2_STOPPED)
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return -EINVAL;
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rzn1_rtc_get_time_snapshot(rtc, tm);
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secs = readl(rtc->base + RZN1_RTC_SECC);
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if (tm->tm_sec != secs)
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rzn1_rtc_get_time_snapshot(rtc, tm);
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tm->tm_sec = bcd2bin(tm->tm_sec);
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tm->tm_min = bcd2bin(tm->tm_min);
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tm->tm_hour = bcd2bin(tm->tm_hour);
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tm->tm_wday = bcd2bin(tm->tm_wday);
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tm->tm_mday = bcd2bin(tm->tm_mday);
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tm->tm_mon = bcd2bin(tm->tm_mon);
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tm->tm_year = bcd2bin(tm->tm_year);
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return 0;
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}
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static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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u32 val;
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int ret;
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tm->tm_sec = bin2bcd(tm->tm_sec);
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tm->tm_min = bin2bcd(tm->tm_min);
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tm->tm_hour = bin2bcd(tm->tm_hour);
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tm->tm_wday = bin2bcd(rzn1_rtc_tm_to_wday(tm));
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tm->tm_mday = bin2bcd(tm->tm_mday);
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tm->tm_mon = bin2bcd(tm->tm_mon);
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tm->tm_year = bin2bcd(tm->tm_year);
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val = readl(rtc->base + RZN1_RTC_CTL2);
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if (!(val & RZN1_RTC_CTL2_STOPPED)) {
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/* Hold the counter if it was counting up */
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writel(RZN1_RTC_CTL2_WAIT, rtc->base + RZN1_RTC_CTL2);
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/* Wait for the counter to stop: two 32k clock cycles */
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usleep_range(61, 100);
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ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val,
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val & RZN1_RTC_CTL2_WST, 0, 100);
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if (ret)
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return ret;
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}
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writel(tm->tm_sec, rtc->base + RZN1_RTC_SEC);
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writel(tm->tm_min, rtc->base + RZN1_RTC_MIN);
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writel(tm->tm_hour, rtc->base + RZN1_RTC_HOUR);
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writel(tm->tm_wday, rtc->base + RZN1_RTC_WEEK);
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writel(tm->tm_mday, rtc->base + RZN1_RTC_DAY);
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writel(tm->tm_mon, rtc->base + RZN1_RTC_MONTH);
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writel(tm->tm_year, rtc->base + RZN1_RTC_YEAR);
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writel(0, rtc->base + RZN1_RTC_CTL2);
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return 0;
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}
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2022-05-16 08:25:02 +00:00
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static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id)
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{
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struct rzn1_rtc *rtc = dev_id;
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rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF);
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return IRQ_HANDLED;
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}
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static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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u32 ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
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if (enable)
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ctl1 |= RZN1_RTC_CTL1_ALME;
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else
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ctl1 &= ~RZN1_RTC_CTL1_ALME;
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writel(ctl1, rtc->base + RZN1_RTC_CTL1);
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return 0;
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}
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static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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struct rtc_time *tm = &alrm->time;
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unsigned int min, hour, wday, delta_days;
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time64_t alarm;
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u32 ctl1;
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int ret;
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ret = rzn1_rtc_read_time(dev, tm);
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if (ret)
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return ret;
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min = readl(rtc->base + RZN1_RTC_ALM);
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hour = readl(rtc->base + RZN1_RTC_ALH);
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wday = readl(rtc->base + RZN1_RTC_ALW);
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tm->tm_sec = 0;
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tm->tm_min = bcd2bin(min);
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tm->tm_hour = bcd2bin(hour);
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delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7;
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tm->tm_wday = fls(wday) - 1;
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if (delta_days) {
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alarm = rtc_tm_to_time64(tm) + (delta_days * 86400);
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rtc_time64_to_tm(alarm, tm);
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}
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ctl1 = readl(rtc->base + RZN1_RTC_CTL1);
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alrm->enabled = !!(ctl1 & RZN1_RTC_CTL1_ALME);
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return 0;
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}
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static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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struct rtc_time *tm = &alrm->time, tm_now;
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unsigned long alarm, farest;
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unsigned int days_ahead, wday;
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int ret;
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ret = rzn1_rtc_read_time(dev, &tm_now);
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if (ret)
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return ret;
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/* We cannot set alarms more than one week ahead */
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farest = rtc_tm_to_time64(&tm_now) + (7 * 86400);
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alarm = rtc_tm_to_time64(tm);
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if (time_after(alarm, farest))
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return -ERANGE;
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/* Convert alarm day into week day */
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days_ahead = tm->tm_mday - tm_now.tm_mday;
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wday = (tm_now.tm_wday + days_ahead) % 7;
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writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM);
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writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH);
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writel(BIT(wday), rtc->base + RZN1_RTC_ALW);
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rzn1_rtc_alarm_irq_enable(dev, alrm->enabled);
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return 0;
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}
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2022-05-16 08:25:03 +00:00
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static int rzn1_rtc_read_offset(struct device *dev, long *offset)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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unsigned int ppb_per_step;
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bool subtract;
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u32 val;
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val = readl(rtc->base + RZN1_RTC_SUBU);
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ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051;
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subtract = val & RZN1_RTC_SUBU_DECR;
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val &= 0x3F;
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if (!val)
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*offset = 0;
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else if (subtract)
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*offset = -(((~val) & 0x3F) + 1) * ppb_per_step;
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else
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*offset = (val - 1) * ppb_per_step;
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return 0;
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}
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static int rzn1_rtc_set_offset(struct device *dev, long offset)
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{
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struct rzn1_rtc *rtc = dev_get_drvdata(dev);
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2022-05-20 08:25:00 +00:00
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int stepsh, stepsl, steps;
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2022-05-20 08:22:21 +00:00
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u32 subu = 0, ctl2;
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2022-05-16 08:25:03 +00:00
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int ret;
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/*
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* Check which resolution mode (every 20 or 60s) can be used.
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* Between 2 and 124 clock pulses can be added or substracted.
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*
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* In 20s mode, the minimum resolution is 2 / (32768 * 20) which is
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* close to 3051 ppb. In 60s mode, the resolution is closer to 1017.
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*/
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stepsh = DIV_ROUND_CLOSEST(offset, 1017);
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stepsl = DIV_ROUND_CLOSEST(offset, 3051);
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if (stepsh >= -0x3E && stepsh <= 0x3E) {
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/* 1017 ppb per step */
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steps = stepsh;
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2022-05-20 08:22:21 +00:00
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subu |= RZN1_RTC_SUBU_DEV;
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2022-05-16 08:25:03 +00:00
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} else if (stepsl >= -0x3E && stepsl <= 0x3E) {
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/* 3051 ppb per step */
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steps = stepsl;
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} else {
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return -ERANGE;
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}
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if (!steps)
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return 0;
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if (steps > 0) {
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2022-05-20 08:22:21 +00:00
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subu |= steps + 1;
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2022-05-16 08:25:03 +00:00
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} else {
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2022-05-20 08:22:21 +00:00
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subu |= RZN1_RTC_SUBU_DECR;
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subu |= (~(-steps - 1)) & 0x3F;
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2022-05-16 08:25:03 +00:00
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}
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2022-05-20 08:22:21 +00:00
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ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,
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!(ctl2 & RZN1_RTC_CTL2_WUST), 100, 2000000);
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2022-05-16 08:25:03 +00:00
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if (ret)
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return ret;
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2022-05-20 08:22:21 +00:00
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writel(subu, rtc->base + RZN1_RTC_SUBU);
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2022-05-16 08:25:03 +00:00
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return 0;
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}
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2022-05-16 08:25:01 +00:00
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static const struct rtc_class_ops rzn1_rtc_ops = {
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.read_time = rzn1_rtc_read_time,
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.set_time = rzn1_rtc_set_time,
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2022-05-16 08:25:02 +00:00
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.read_alarm = rzn1_rtc_read_alarm,
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.set_alarm = rzn1_rtc_set_alarm,
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.alarm_irq_enable = rzn1_rtc_alarm_irq_enable,
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2022-05-16 08:25:03 +00:00
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.read_offset = rzn1_rtc_read_offset,
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|
|
.set_offset = rzn1_rtc_set_offset,
|
2022-05-16 08:25:01 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int rzn1_rtc_probe(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct rzn1_rtc *rtc;
|
2022-05-16 08:25:02 +00:00
|
|
|
int alarm_irq;
|
2022-05-16 08:25:01 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
|
|
|
|
if (!rtc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, rtc);
|
|
|
|
|
|
|
|
rtc->base = devm_platform_ioremap_resource(pdev, 0);
|
|
|
|
if (IS_ERR(rtc->base))
|
|
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n");
|
|
|
|
|
2022-05-16 08:25:02 +00:00
|
|
|
alarm_irq = platform_get_irq(pdev, 0);
|
|
|
|
if (alarm_irq < 0)
|
|
|
|
return alarm_irq;
|
|
|
|
|
2022-05-16 08:25:01 +00:00
|
|
|
rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev);
|
|
|
|
if (IS_ERR(rtc->rtcdev))
|
2022-05-19 13:56:19 +00:00
|
|
|
return PTR_ERR(rtc->rtcdev);
|
2022-05-16 08:25:01 +00:00
|
|
|
|
|
|
|
rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000;
|
|
|
|
rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099;
|
|
|
|
rtc->rtcdev->ops = &rzn1_rtc_ops;
|
2022-05-16 08:25:02 +00:00
|
|
|
set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features);
|
2022-05-16 08:25:01 +00:00
|
|
|
clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features);
|
|
|
|
|
2022-11-07 09:25:44 +00:00
|
|
|
ret = devm_pm_runtime_enable(&pdev->dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2022-05-16 08:25:01 +00:00
|
|
|
ret = pm_runtime_resume_and_get(&pdev->dev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Ensure the clock counter is enabled.
|
|
|
|
* Set 24-hour mode and possible oscillator offset compensation in SUBU mode.
|
|
|
|
*/
|
|
|
|
writel(RZN1_RTC_CTL0_CE | RZN1_RTC_CTL0_AMPM | RZN1_RTC_CTL0_SLSB_SUBU,
|
|
|
|
rtc->base + RZN1_RTC_CTL0);
|
|
|
|
|
|
|
|
/* Disable all interrupts */
|
|
|
|
writel(0, rtc->base + RZN1_RTC_CTL1);
|
|
|
|
|
2022-05-16 08:25:02 +00:00
|
|
|
ret = devm_request_irq(&pdev->dev, alarm_irq, rzn1_rtc_alarm_irq, 0,
|
|
|
|
dev_name(&pdev->dev), rtc);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "RTC timer interrupt not available\n");
|
|
|
|
goto dis_runtime_pm;
|
|
|
|
}
|
|
|
|
|
2022-05-16 08:25:01 +00:00
|
|
|
ret = devm_rtc_register_device(rtc->rtcdev);
|
|
|
|
if (ret)
|
|
|
|
goto dis_runtime_pm;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dis_runtime_pm:
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rzn1_rtc_remove(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct of_device_id rzn1_rtc_of_match[] = {
|
|
|
|
{ .compatible = "renesas,rzn1-rtc" },
|
|
|
|
{},
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, rzn1_rtc_of_match);
|
|
|
|
|
|
|
|
static struct platform_driver rzn1_rtc_driver = {
|
|
|
|
.probe = rzn1_rtc_probe,
|
|
|
|
.remove = rzn1_rtc_remove,
|
|
|
|
.driver = {
|
|
|
|
.name = "rzn1-rtc",
|
|
|
|
.of_match_table = rzn1_rtc_of_match,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
module_platform_driver(rzn1_rtc_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Michel Pollet <Michel.Pollet@bp.renesas.com");
|
|
|
|
MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com");
|
|
|
|
MODULE_DESCRIPTION("RZ/N1 RTC driver");
|
|
|
|
MODULE_LICENSE("GPL");
|