A pile of clk driver updates with a small tracepoint patch to the clk core this
time around. The core framework is effectively unchanged, with the majority of
the diff going to the Qualcomm clk driver directory because they added two 3k
line files that are almost all clk data (Abel Vesa from Linaro tried to shrink
the number of lines down, but it doesn't seem to be possible without
sacrificing readability). The second big driver this time around is the
Rockchip rk3588 clk and reset unit, at _only_ 2.5k lines.
Ignoring the big clk drivers from the familiar SoC vendors, there's just a
bunch of little clk driver updates and fixes throughout here. It's the usual
set of clk data fixups to describe proper parents, or add frequencies to
frequency tables, or plug memory leaks when function calls fail. Also, some
drivers are converted to use modern clk_hw APIs, which is always nice to see.
And data is deduplicated, leading to a smaller kernel Image. Overall this batch
has a larger collection of cleanups than it typically does. Maybe that means
there are less new SoCs right now that need supporting, and the focus has
shifted to quality and reliability. I can dream.
New Drivers:
- Frequency hopping controller hardware on MediaTek MT8186
- Global clock controller for Qualcomm SM8550
- Display clock controller for Qualcomm SC8280XP
- RPMh clock controller for Qualcomm QDU1000 and QRU1000 SoCs
- CPU PLL on MStar/SigmaStar SoCs
- Support for the clock and reset unit of the Rockchip rk3588
Updates:
- Tracepoints for clk_rate_request structures
- Debugfs support for fractional divider clk
- Make MxL's CGU driver secure compatible
- Ingenic JZ4755 SoC clk support
- Support audio clks on X1000 SoCs
- Remove flags from univ/main/syspll child fixed factor clocks across
MediaTek platforms
- Fix clock dependency for ADC on MediaTek MT7986
- Fix parent for FlexSPI clock for i.MX93
- Add USB suspend clock on i.MX8MP
- Unmap anatop base on error for i.MX93 driver
- Change enet clock parent to wakeup_axi_root for i.MX93
- Drop LPIT1, LPIT2, TPM1 and TPM3 clocks for i.MX93
- Mark HSIO bus clock and SYS_CNT clock as critical on i.MX93
- Add 320MHz and 640MHz entries to PLL146x
- Add audio shared gate and SAI clocks for i.MX8MP
- Fix a possible memory leak in the error path of rockchip PLL creation
- Fix header guard for V3S clocks
- Add IR module clock for f1c100s
- Correct the parent clocks for the (High Speed) Serial Communication
Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
Switch clocks on Renesas R-Car S4-8
- Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on Renesas
R-Car V4H
- Two PLL driver fixups for the Amlogic clk driver
- Round SD clock rate to improve parent clock selection
- Add Ethernet Switch and internal SASYNCPER clocks on Renesas R-Car
S4-8
- Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX) serial
(SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI (RPC-IF) clocks
on Renesas R-Car V4H
- Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
Renesas RZ/G2L
- Fix endless loop on Renesas RZ/N1
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the Renesas R-Car V4H SoC
Note: HSCIF0 is used for the serial console on the White-Hawk
development board
- Various clk DT binding improvements and conversions to YAML
- Qualcomm SM8150/SM8250 display clock controller cleaned up
- Some missing clocks for Qualcomm SM8350 added
- Qualcomm MSM8974 Global and Multimedia clock controllers transitioned
to parent_data and parent_hws
- Use parent_data and add network resets for Qualcomm IPQ8074
- Qualcomm Krait clock controller modernized
- Fix pm_runtime usage in Qualcomm SC7180 and SC7280 LPASS clock
controllers
- Enable retention mode on Qualcomm SM8250 USB GDSCs
- Cleanup Qualcomm RPM and RPMh clock drivers to avoid duplicating
clocks which definition could be shared between platforms
- Various NULL pointer checks added for allocations
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk driver updates from Stephen Boyd:
"A pile of clk driver updates with a small tracepoint patch to the clk
core this time around.
The core framework is effectively unchanged, with the majority of the
diff going to the Qualcomm clk driver directory because they added two
3k line files that are almost all clk data (Abel Vesa from Linaro
tried to shrink the number of lines down, but it doesn't seem to be
possible without sacrificing readability).
The second big driver this time around is the Rockchip rk3588 clk and
reset unit, at _only_ 2.5k lines.
Ignoring the big clk drivers from the familiar SoC vendors, there's
just a bunch of little clk driver updates and fixes throughout here.
It's the usual set of clk data fixups to describe proper parents, or
add frequencies to frequency tables, or plug memory leaks when
function calls fail. Also, some drivers are converted to use modern
clk_hw APIs, which is always nice to see. And data is deduplicated,
leading to a smaller kernel Image.
Overall this batch has a larger collection of cleanups than it
typically does. Maybe that means there are less new SoCs right now
that need supporting, and the focus has shifted to quality and
reliability. I can dream.
New Drivers:
- Frequency hopping controller hardware on MediaTek MT8186
- Global clock controller for Qualcomm SM8550
- Display clock controller for Qualcomm SC8280XP
- RPMh clock controller for Qualcomm QDU1000 and QRU1000 SoCs
- CPU PLL on MStar/SigmaStar SoCs
- Support for the clock and reset unit of the Rockchip rk3588
Updates:
- Tracepoints for clk_rate_request structures
- Debugfs support for fractional divider clk
- Make MxL's CGU driver secure compatible
- Ingenic JZ4755 SoC clk support
- Support audio clks on X1000 SoCs
- Remove flags from univ/main/syspll child fixed factor clocks across
MediaTek platforms
- Fix clock dependency for ADC on MediaTek MT7986
- Fix parent for FlexSPI clock for i.MX93
- Add USB suspend clock on i.MX8MP
- Unmap anatop base on error for i.MX93 driver
- Change enet clock parent to wakeup_axi_root for i.MX93
- Drop LPIT1, LPIT2, TPM1 and TPM3 clocks for i.MX93
- Mark HSIO bus clock and SYS_CNT clock as critical on i.MX93
- Add 320MHz and 640MHz entries to PLL146x
- Add audio shared gate and SAI clocks for i.MX8MP
- Fix a possible memory leak in the error path of rockchip PLL
creation
- Fix header guard for V3S clocks
- Add IR module clock for f1c100s
- Correct the parent clocks for the (High Speed) Serial Communication
Interfaces with FIFO ((H)SCIF) modules and the mixed-up Ethernet
Switch clocks on Renesas R-Car S4-8
- Add timer (TMU, CMT) and Cortex-A76 CPU core (Z0) clocks on Renesas
R-Car V4H
- Two PLL driver fixups for the Amlogic clk driver
- Round SD clock rate to improve parent clock selection
- Add Ethernet Switch and internal SASYNCPER clocks on Renesas R-Car
S4-8
- Add DMA (SYS-DMAC), SPI (MSIOF), external interrupt (INTC-EX)
serial (SCIF), PWM (PWM and TPU), SDHI, and HyperFLASH/QSPI
(RPC-IF) clocks on Renesas R-Car V4H
- Add Multi-Function Timer Pulse Unit (MTU3a) clock and reset on
Renesas RZ/G2L
- Fix endless loop on Renesas RZ/N1
- Correct the parent clocks for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) modules on the Renesas R-Car V4H SoC
Note: HSCIF0 is used for the serial console on the White-Hawk
development board
- Various clk DT binding improvements and conversions to YAML
- Qualcomm SM8150/SM8250 display clock controller cleaned up
- Some missing clocks for Qualcomm SM8350 added
- Qualcomm MSM8974 Global and Multimedia clock controllers
transitioned to parent_data and parent_hws
- Use parent_data and add network resets for Qualcomm IPQ8074
- Qualcomm Krait clock controller modernized
- Fix pm_runtime usage in Qualcomm SC7180 and SC7280 LPASS clock
controllers
- Enable retention mode on Qualcomm SM8250 USB GDSCs
- Cleanup Qualcomm RPM and RPMh clock drivers to avoid duplicating
clocks which definition could be shared between platforms
- Various NULL pointer checks added for allocations"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (188 commits)
clk: nomadik: correct struct name kernel-doc warning
clk: lmk04832: fix kernel-doc warnings
clk: lmk04832: drop superfluous #include
clk: lmk04832: drop unnecessary semicolons
clk: lmk04832: declare variables as const when possible
clk: socfpga: Fix memory leak in socfpga_gate_init()
clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
clk: st: Fix memory leak in st_of_quadfs_setup()
clk: samsung: Fix memory leak in _samsung_clk_register_pll()
clk: Add trace events for rate requests
clk: Store clk_core for clk_rate_request
clk: qcom: rpmh: add support for SM6350 rpmh IPA clock
clk: qcom: mmcc-msm8974: use parent_hws/_data instead of parent_names
clk: qcom: mmcc-msm8974: move clock parent tables down
clk: qcom: mmcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
clk: qcom: gcc-msm8974: use parent_hws/_data instead of parent_names
clk: qcom: gcc-msm8974: move clock parent tables down
clk: qcom: gcc-msm8974: use ARRAY_SIZE instead of specifying num_parents
dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8974
dt-bindings: clock: split qcom,gcc-msm8974,-msm8226 to the separate file
...
This commit is contained in:
Linus Torvalds
commit
0015edd6f6
|
|
@ -22,6 +22,7 @@ select:
|
|||
enum:
|
||||
- ingenic,jz4740-cgu
|
||||
- ingenic,jz4725b-cgu
|
||||
- ingenic,jz4755-cgu
|
||||
- ingenic,jz4760-cgu
|
||||
- ingenic,jz4760b-cgu
|
||||
- ingenic,jz4770-cgu
|
||||
|
|
@ -51,6 +52,7 @@ properties:
|
|||
- enum:
|
||||
- ingenic,jz4740-cgu
|
||||
- ingenic,jz4725b-cgu
|
||||
- ingenic,jz4755-cgu
|
||||
- ingenic,jz4760-cgu
|
||||
- ingenic,jz4760b-cgu
|
||||
- ingenic,jz4770-cgu
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-fhctl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek frequency hopping and spread spectrum clocking control
|
||||
|
||||
maintainers:
|
||||
- Edward-JW Yang <edward-jw.yang@mediatek.com>
|
||||
|
||||
description: |
|
||||
Frequency hopping control (FHCTL) is a piece of hardware that control
|
||||
some PLLs to adopt "hopping" mechanism to adjust their frequency.
|
||||
Spread spectrum clocking (SSC) is another function provided by this hardware.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8186-fhctl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
description: Phandles of the PLL with FHCTL hardware capability.
|
||||
minItems: 1
|
||||
maxItems: 30
|
||||
|
||||
mediatek,hopping-ssc-percent:
|
||||
description: The percentage of spread spectrum clocking for one PLL.
|
||||
minItems: 1
|
||||
maxItems: 30
|
||||
items:
|
||||
default: 0
|
||||
minimum: 0
|
||||
maximum: 8
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
fhctl: fhctl@1000ce00 {
|
||||
compatible = "mediatek,mt8186-fhctl";
|
||||
reg = <0x1000ce00 0x200>;
|
||||
clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
|
||||
mediatek,hopping-ssc-percent = <3>;
|
||||
};
|
||||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,a53pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm A53 PLL Binding
|
||||
title: Qualcomm A53 PLL clock
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,a7pll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm A7 PLL Binding
|
||||
title: Qualcomm A7 PLL clock
|
||||
|
||||
maintainers:
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,aoncc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for LPASS Always ON Clock Controller on SM8250 SoCs
|
||||
title: LPASS Always ON Clock Controller on SM8250 SoCs
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
|
@ -17,7 +17,7 @@ description: |
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8250-lpass-aon
|
||||
const: qcom,sm8250-lpass-aoncc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -28,11 +28,13 @@ properties:
|
|||
clocks:
|
||||
items:
|
||||
- description: LPASS Core voting clock
|
||||
- description: LPASS Audio codec voting clock
|
||||
- description: Glitch Free Mux register clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: audio
|
||||
- const: bus
|
||||
|
||||
required:
|
||||
|
|
@ -50,9 +52,10 @@ examples:
|
|||
#include <dt-bindings/sound/qcom,q6afe.h>
|
||||
clock-controller@3800000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "qcom,sm8250-lpass-aon";
|
||||
compatible = "qcom,sm8250-lpass-aoncc";
|
||||
reg = <0x03380000 0x40000>;
|
||||
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "core", "audio", "bus";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,audiocc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Clock bindings for LPASS Audio Clock Controller on SM8250 SoCs
|
||||
title: LPASS Audio Clock Controller on SM8250 SoCs
|
||||
|
||||
maintainers:
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
|
@ -28,11 +28,13 @@ properties:
|
|||
clocks:
|
||||
items:
|
||||
- description: LPASS Core voting clock
|
||||
- description: LPASS Audio codec voting clock
|
||||
- description: Glitch Free Mux register clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: audio
|
||||
- const: bus
|
||||
|
||||
required:
|
||||
|
|
@ -53,6 +55,7 @@ examples:
|
|||
compatible = "qcom,sm8250-lpass-audiocc";
|
||||
reg = <0x03300000 0x30000>;
|
||||
clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "core", "bus";
|
||||
clock-names = "core", "audio", "bus";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM8250
|
||||
|
||||
maintainers:
|
||||
- Jonathan Marek <jonathan@marek.ca>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
Qualcomm camera clock control module provides the clocks, resets and
|
||||
power domains on SM8250.
|
||||
|
||||
See also dt-bindings/clock/qcom,camcc-sm8250.h
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,97 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC8280XP
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains for the two MDSS instances on SC8280XP.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,dispcc-sc8280xp.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,sc8280xp-dispcc0
|
||||
- qcom,sc8280xp-dispcc1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB interface clock,
|
||||
- description: SoC CXO clock
|
||||
- description: SoC sleep clock
|
||||
- description: DisplayPort 0 link clock
|
||||
- description: DisplayPort 0 VCO div clock
|
||||
- description: DisplayPort 1 link clock
|
||||
- description: DisplayPort 1 VCO div clock
|
||||
- description: DisplayPort 2 link clock
|
||||
- description: DisplayPort 2 VCO div clock
|
||||
- description: DisplayPort 3 link clock
|
||||
- description: DisplayPort 3 VCO div clock
|
||||
- description: DSI 0 PLL byte clock
|
||||
- description: DSI 0 PLL DSI clock
|
||||
- description: DSI 1 PLL byte clock
|
||||
- description: DSI 1 PLL DSI clock
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: MMCX power domain
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
- '#power-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/power/qcom-rpmpd.h>
|
||||
clock-controller@af00000 {
|
||||
compatible = "qcom,sc8280xp-dispcc0";
|
||||
reg = <0x0af00000 0x20000>;
|
||||
clocks = <&gcc GCC_DISP_AHB_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&sleep_clk>,
|
||||
<&mdss0_dp_phy0 0>,
|
||||
<&mdss0_dp_phy0 1>,
|
||||
<&mdss0_dp_phy1 0>,
|
||||
<&mdss0_dp_phy1 1>,
|
||||
<&mdss0_dp_phy2 0>,
|
||||
<&mdss0_dp_phy2 1>,
|
||||
<&mdss0_dp_phy3 0>,
|
||||
<&mdss0_dp_phy3 1>,
|
||||
<&mdss0_dsi0_phy 0>,
|
||||
<&mdss0_dsi0_phy 1>,
|
||||
<&mdss0_dsi1_phy 0>,
|
||||
<&mdss0_dsi1_phy 1>;
|
||||
power-domains = <&rpmhpd SC8280XP_MMCX>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6125.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock Controller Binding for SM6125
|
||||
title: Qualcomm Display Clock Controller on SM6125
|
||||
|
||||
maintainers:
|
||||
- Martin Botka <martin.botka@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks and
|
||||
power domains on SM6125.
|
||||
Qualcomm display clock control module provides the clocks and power domains
|
||||
on SM6125.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,dispcc-sm6125.h
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-sm6125.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SM6350
|
||||
title: Qualcomm Display Clock & Reset Controller on SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SM6350.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM6350.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sm6350.h.
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,19 +4,19 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
|
||||
title: Qualcomm Display Clock & Reset Controller on SM8150/SM8250/SM8350
|
||||
|
||||
maintainers:
|
||||
- Jonathan Marek <jonathan@marek.ca>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SM8150/SM8250/SM8350.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8150/SM8250/SM8350.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,dispcc-sm8150.h
|
||||
dt-bindings/clock/qcom,dispcc-sm8250.h
|
||||
dt-bindings/clock/qcom,dispcc-sm8350.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,dispcc-sm8150.h
|
||||
include/dt-bindings/clock/qcom,dispcc-sm8250.h
|
||||
include/dt-bindings/clock/qcom,dispcc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,22 +4,22 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
title: Qualcomm Global Clock & Reset Controller on APQ8064/MSM8960
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8064.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on APQ8064.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8960.h
|
||||
include/dt-bindings/reset/qcom,gcc-msm8960.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,19 +4,19 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for APQ8084
|
||||
title: Qualcomm Global Clock & Reset Controller on APQ8084
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on APQ8084.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on APQ8084.
|
||||
|
||||
See also::
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
include/dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
include/dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -4,21 +4,21 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ8064
|
||||
|
||||
maintainers:
|
||||
- Ansuel Smith <ansuelsmth@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on IPQ8064.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ8064.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
- dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -27,14 +27,18 @@ properties:
|
|||
- const: syscon
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: PXO source
|
||||
- description: CXO source
|
||||
- description: PLL4 from LCC
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: pxo
|
||||
- const: cxo
|
||||
- const: pll4
|
||||
|
||||
thermal-sensor:
|
||||
type: object
|
||||
|
|
@ -51,13 +55,14 @@ unevaluatedProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-ipq8064", "syscon";
|
||||
reg = <0x00900000 0x4000>;
|
||||
clocks = <&pxo_board>, <&cxo_board>;
|
||||
clock-names = "pxo", "cxo";
|
||||
clocks = <&pxo_board>, <&cxo_board>, <&lcc PLL4>;
|
||||
clock-names = "pxo", "cxo", "pll4";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -4,47 +4,39 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8074.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Bindingfor IPQ8074
|
||||
title: Qualcomm Global Clock & Reset Controller on IPQ8074
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on IPQ8074.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on IPQ8074.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-ipq8074.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,gcc-ipq8074
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
clocks:
|
||||
items:
|
||||
- description: board XO clock
|
||||
- description: sleep clock
|
||||
|
||||
'#power-domain-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
protected-clocks:
|
||||
description:
|
||||
Protected clock specifier list as per common clock binding.
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#power-domain-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
|
|
|
|||
|
|
@ -4,22 +4,22 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8660
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8660
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks and resets on
|
||||
Qualcomm global clock control module provides the clocks and resets on
|
||||
MSM8660
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8660.h
|
||||
include/dt-bindings/reset/qcom,gcc-msm8660.h
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,gcc.yaml#"
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8909
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8909
|
||||
|
||||
maintainers:
|
||||
- Stephan Gerhold <stephan@gerhold.net>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8909.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8909.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,21 +4,21 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8916.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8916 and MSM8939
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8916 and MSM8939
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8916 or MSM8939.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8916 or MSM8939.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8916.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8916.h
|
||||
- dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8916.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8939.h
|
||||
include/dt-bindings/reset/qcom,gcc-msm8916.h
|
||||
include/dt-bindings/reset/qcom,gcc-msm8939.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,61 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8974.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8974 (including Pro) and MSM8226
|
||||
Controller
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8974 (all variants) and MSM8226.
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
|
||||
$ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@fc400000 {
|
||||
compatible = "qcom,gcc-msm8974";
|
||||
reg = <0x00100000 0x94000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
clock-names = "xo", "sleep_clk";
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>;
|
||||
};
|
||||
...
|
||||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8976.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8976
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8976
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8976.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8976.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8976.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8976.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8994.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8994
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8994
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8994 and MSM8992.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8994 and MSM8992.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8994.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8994.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8996.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8996
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8996
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
Qualcomm global clock control module which provides the clocks, resets and
|
||||
power domains on MSM8996.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8996.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8996.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for MSM8998
|
||||
title: Qualcomm Global Clock & Reset Controller on MSM8998
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on MSM8998.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on MSM8998.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-msm8998.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,30 +4,27 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
title: Qualcomm Global Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
- dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
|
||||
- dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
- dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
include/dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
include/dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
include/dt-bindings/clock/qcom,gcc-msm8953.h
|
||||
include/dt-bindings/clock/qcom,gcc-mdm9607.h
|
||||
include/dt-bindings/clock/qcom,gcc-mdm9615.h
|
||||
include/dt-bindings/reset/qcom,gcc-mdm9615.h
|
||||
|
||||
allOf:
|
||||
- $ref: "qcom,gcc.yaml#"
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -35,14 +32,8 @@ properties:
|
|||
- qcom,gcc-ipq4019
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-mdm9607
|
||||
- qcom,gcc-msm8226
|
||||
- qcom,gcc-msm8953
|
||||
- qcom,gcc-msm8974
|
||||
- qcom,gcc-msm8974pro
|
||||
- qcom,gcc-msm8974pro-ac
|
||||
- qcom,gcc-mdm9615
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
@ -50,10 +41,9 @@ required:
|
|||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for MSM8974:
|
||||
- |
|
||||
clock-controller@900000 {
|
||||
compatible = "qcom,gcc-msm8974";
|
||||
compatible = "qcom,gcc-mdm9607";
|
||||
reg = <0x900000 0x4000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcm2290.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for QCM2290
|
||||
title: Qualcomm Global Clock & Reset Controller on QCM2290
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets
|
||||
and power domains on QCM2290.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on QCM2290.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-qcm2290.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-qcm2290.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-qcs404.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Bindingfor QCS404
|
||||
title: Qualcomm Global Clock & Reset Controller on QCS404
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on QCS404.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on QCS404.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-qcs404.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-qcs404.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7180.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC7180
|
||||
title: Qualcomm Global Clock & Reset Controller on SC7180
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc7180.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC7280
|
||||
title: Qualcomm Global Clock & Reset Controller on SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC7280.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc7280.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sc7280.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8180x.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8180x
|
||||
title: Qualcomm Global Clock & Reset Controller on SC8180x
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SC8180x.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SC8180x.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sc8180x.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sc8180x.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SC8280xp
|
||||
title: Qualcomm Global Clock & Reset Controller on SC8280xp
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
Qualcomm global clock control module provides the clocks, resets and
|
||||
power domains on SC8280xp.
|
||||
|
||||
See also:
|
||||
- include/dt-bindings/clock/qcom,gcc-sc8280xp.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,61 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDM660/SDM630/SDM636 Global Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <quic_tdas@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SDM630, SDM636 and SDM660
|
||||
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
|
||||
|
||||
$ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,gcc-sdm630
|
||||
- qcom,gcc-sdm660
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XO source
|
||||
- description: Sleep clock source
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: sleep_clk
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
# Example for GCC for SDM660:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,gcc-sdm660";
|
||||
reg = <0x00100000 0x94000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
|
||||
clock-names = "xo", "sleep_clk";
|
||||
clocks = <&xo_board>,
|
||||
<&sleep_clk>;
|
||||
};
|
||||
...
|
||||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdm845.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding
|
||||
title: Qualcomm Global Clock & Reset Controller on SDM670 and SDM845
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SDM845
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SDM670 and SDM845
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sdm845.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sdm845.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SDX55
|
||||
title: Qualcomm Global Clock & Reset Controller on SDX55
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
Qualcomm global clock control module provides the clocks, resets and
|
||||
power domains on SDX55
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sdx55.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sdx55.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx65.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SDX65
|
||||
title: Qualcomm Global Clock & Reset Controller on SDX65
|
||||
|
||||
maintainers:
|
||||
- Vamsi krishna Lanka <quic_vamslank@quicinc.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SDX65
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SDX65
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sdx65.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sdx65.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6115.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6115 and SM4250
|
||||
title: Qualcomm Global Clock & Reset Controller on SM6115 and SM4250
|
||||
|
||||
maintainers:
|
||||
- Iskren Chernev <iskren.chernev@gmail.com>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM4250/6115.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM4250/6115.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm6115.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm6115.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6125
|
||||
title: Qualcomm Global Clock & Reset Controller on SM6125
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM6125.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM6125.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm6125.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm6125.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6350
|
||||
title: Qualcomm Global Clock & Reset Controller on SM6350
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM6350.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM6350.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm6350.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm6350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8150.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8150
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8150
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8150.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8150.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8150.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm8150.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,17 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8250
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8250
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8250.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8250.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8250.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8350
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8350
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8350.
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8350.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8350.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM8450
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8450
|
||||
|
||||
maintainers:
|
||||
- Vinod Koul <vkoul@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM8450
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8450
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,gcc-sm8450.h
|
||||
See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,15 +4,15 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
|
||||
title: Qualcomm Global Clock & Reset Controller Common Bindings
|
||||
|
||||
maintainers:
|
||||
- Stephen Boyd <sboyd@kernel.org>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Common bindings for Qualcomm global clock control module which supports
|
||||
the clocks, resets and power domains.
|
||||
Common bindings for Qualcomm global clock control module providing the
|
||||
clocks, resets and power domains.
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
|
|
|
|||
|
|
@ -4,13 +4,13 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SDM630 and SDM660
|
||||
|
||||
maintainers:
|
||||
- AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
Qualcomm graphics clock control module provides the clocks, resets and
|
||||
power domains on SDM630 and SDM660.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-sdm660.h.
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding
|
||||
title: Qualcomm Graphics Clock & Reset Controller on SM8350
|
||||
|
||||
maintainers:
|
||||
- Robert Foss <robert.foss@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on Qualcomm SoCs.
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gpucc-sm8350.h
|
||||
See also:: include/dt-bindings/clock/qcom,gpucc-sm8350.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,23 +4,23 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding
|
||||
title: Qualcomm Graphics Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on Qualcomm SoCs.
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
dt-bindings/clock/qcom,gpucc-sc8280xp.h
|
||||
dt-bindings/clock/qcom,gpucc-sm6350.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,gpucc-sdm845.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc7180.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc7280.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm6350.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8150.h
|
||||
include/dt-bindings/clock/qcom,gpucc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -1,22 +0,0 @@
|
|||
Qualcomm LPASS Clock & Reset Controller Binding
|
||||
------------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain only one of the following:
|
||||
|
||||
"qcom,lcc-msm8960"
|
||||
"qcom,lcc-apq8064"
|
||||
"qcom,lcc-ipq8064"
|
||||
"qcom,lcc-mdm9615"
|
||||
|
||||
- reg : shall contain base register location and length
|
||||
- #clock-cells : shall contain 1
|
||||
- #reset-cells : shall contain 1
|
||||
|
||||
Example:
|
||||
clock-controller@28000000 {
|
||||
compatible = "qcom,lcc-ipq8064";
|
||||
reg = <0x28000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,lcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,lcc-apq8064
|
||||
- qcom,lcc-ipq8064
|
||||
- qcom,lcc-mdm9615
|
||||
- qcom,lcc-msm8960
|
||||
|
||||
clocks:
|
||||
maxItems: 8
|
||||
|
||||
clock-names:
|
||||
maxItems: 8
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,lcc-apq8064
|
||||
- qcom,lcc-msm8960
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board PXO source
|
||||
- description: PLL 4 Vote clock
|
||||
- description: MI2S codec clock
|
||||
- description: Mic I2S codec clock
|
||||
- description: Mic I2S spare clock
|
||||
- description: Speaker I2S codec clock
|
||||
- description: Speaker I2S spare clock
|
||||
- description: PCM codec clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: pxo
|
||||
- const: pll4_vote
|
||||
- const: mi2s_codec_clk
|
||||
- const: codec_i2s_mic_codec_clk
|
||||
- const: spare_i2s_mic_codec_clk
|
||||
- const: codec_i2s_spkr_codec_clk
|
||||
- const: spare_i2s_spkr_codec_clk
|
||||
- const: pcm_codec_clk
|
||||
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@28000000 {
|
||||
compatible = "qcom,lcc-ipq8064";
|
||||
reg = <0x28000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
Qualcomm LPASS Clock Controller Binding
|
||||
-----------------------------------------------
|
||||
|
||||
Required properties :
|
||||
- compatible : shall contain "qcom,sdm845-lpasscc"
|
||||
- #clock-cells : from common clock binding, shall contain 1.
|
||||
- reg : shall contain base register address and size,
|
||||
in the order
|
||||
Index-0 maps to LPASS_CC register region
|
||||
Index-1 maps to LPASS_QDSP6SS register region
|
||||
|
||||
Optional properties :
|
||||
- reg-names : register names of LPASS domain
|
||||
"cc", "qdsp6ss".
|
||||
|
||||
Example:
|
||||
|
||||
The below node has to be defined in the cases where the LPASS peripheral loader
|
||||
would bring the subsystem out of reset.
|
||||
|
||||
lpasscc: clock-controller@17014000 {
|
||||
compatible = "qcom,sdm845-lpasscc";
|
||||
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
|
||||
reg-names = "cc", "qdsp6ss";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -4,14 +4,14 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,mmcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Multimedia Clock & Reset Controller Binding
|
||||
title: Qualcomm Multimedia Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Jeffrey Hugo <quic_jhugo@quicinc.com>
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm multimedia clock control module which supports the clocks, resets and
|
||||
Qualcomm multimedia clock control module provides the clocks, resets and
|
||||
power domains.
|
||||
|
||||
properties:
|
||||
|
|
@ -99,6 +99,44 @@ allOf:
|
|||
- const: dsi2pllbyte
|
||||
- const: hdmipll
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,mmcc-msm8974
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: MMSS GPLL0 voted clock
|
||||
- description: GPLL0 voted clock
|
||||
- description: GPLL1 voted clock
|
||||
- description: GFX3D clock source
|
||||
- description: DSI phy instance 0 dsi clock
|
||||
- description: DSI phy instance 0 byte clock
|
||||
- description: DSI phy instance 1 dsi clock
|
||||
- description: DSI phy instance 1 byte clock
|
||||
- description: HDMI phy PLL clock
|
||||
- description: eDP phy PLL link clock
|
||||
- description: eDP phy PLL vco clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xo
|
||||
- const: mmss_gpll0_vote
|
||||
- const: gpll0_vote
|
||||
- const: gpll1_vote
|
||||
- const: gfx3d_clk_src
|
||||
- const: dsi0pll
|
||||
- const: dsi0pllbyte
|
||||
- const: dsi1pll
|
||||
- const: dsi1pllbyte
|
||||
- const: hdmipll
|
||||
- const: edp_link_clk
|
||||
- const: edp_vco_div
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,msm8998-gpucc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Graphics Clock & Reset Controller Binding for MSM8998
|
||||
title: Qualcomm Graphics Clock & Reset Controller on MSM8998
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm graphics clock control module which supports the clocks, resets and
|
||||
power domains on MSM8998.
|
||||
Qualcomm graphics clock control module provides the clocks, resets and power
|
||||
domains on MSM8998.
|
||||
|
||||
See also dt-bindings/clock/qcom,gpucc-msm8998.h.
|
||||
See also:: include/dt-bindings/clock/qcom,gpucc-msm8998.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: "qcom,qcs404-q6sstopcc"
|
||||
const: qcom,qcs404-q6sstopcc
|
||||
|
||||
reg:
|
||||
items:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,qcm2290-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for qcm2290
|
||||
title: Qualcomm Display Clock & Reset Controller on QCM2290
|
||||
|
||||
maintainers:
|
||||
- Loic Poulain <loic.poulain@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on qcm2290.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on qcm2290.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-qcm2290.h.
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-qcm2290.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ description: |
|
|||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qdu1000-rpmh-clk
|
||||
- qcom,sc7180-rpmh-clk
|
||||
- qcom,sc7280-rpmh-clk
|
||||
- qcom,sc8180x-rpmh-clk
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SC7180
|
||||
title: Qualcomm Camera Clock & Reset Controller on SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,camcc-sc7180.h
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC7180
|
||||
title: Qualcomm Display Clock & Reset Controller on SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SC7180.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SC7180.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sc7180.h.
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core Clock Controller Binding for SC7180
|
||||
title: Qualcomm LPASS Core Clock Controller on SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core clock control module which supports the clocks and
|
||||
power domains on SC7180.
|
||||
Qualcomm LPASS core clock control module provides the clocks and power
|
||||
domains on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7180.h
|
||||
See also:: include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,15 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7180-mss.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Modem Clock Controller Binding for SC7180
|
||||
title: Qualcomm Modem Clock Controller on SC7180
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm modem clock control module which supports the clocks on SC7180.
|
||||
Qualcomm modem clock control module provides the clocks on SC7180.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,mss-sc7180.h
|
||||
See also:: include/dt-bindings/clock/qcom,mss-sc7180.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SC7280
|
||||
title: Qualcomm Camera Clock & Reset Controller on SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
Qualcomm camera clock control module provides the clocks, resets and
|
||||
power domains on SC7280.
|
||||
|
||||
See also dt-bindings/clock/qcom,camcc-sc7280.h
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sc7280.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SC7280
|
||||
title: Qualcomm Display Clock & Reset Controller on SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SC7280.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SC7280.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sc7280.h.
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-sc7280.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core Clock Controller Binding for SC7280
|
||||
title: Qualcomm LPASS Core Clock Controller on SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core clock control module which supports the clocks and
|
||||
power domains on SC7280.
|
||||
Qualcomm LPASS core clock control module provides the clocks and power
|
||||
domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpass-sc7280.h
|
||||
See also:: include/dt-bindings/clock/qcom,lpass-sc7280.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,18 +4,18 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sc7280-lpasscorecc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller Binding for SC7280
|
||||
title: Qualcomm LPASS Core & Audio Clock Controller on SC7280
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm LPASS core and audio clock control module which supports the
|
||||
clocks and power domains on SC7280.
|
||||
Qualcomm LPASS core and audio clock control module provides the clocks and
|
||||
power domains on SC7280.
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,lpasscorecc-sc7280.h
|
||||
- dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
|
||||
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
|
||||
|
||||
properties:
|
||||
clocks: true
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SDM845
|
||||
title: Qualcomm Camera Clock & Reset Controller on SDM845
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,camcc-sm845.h
|
||||
See also:: include/dt-bindings/clock/qcom,camcc-sm845.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller Binding for SDM845
|
||||
title: Qualcomm Display Clock & Reset Controller on SDM845
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SDM845.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SDM845.
|
||||
|
||||
See also dt-bindings/clock/qcom,dispcc-sdm845.h.
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-sdm845.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,47 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sdm845-lpasscc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SDM845 LPASS Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm SDM845 LPASS (Low Power Audio SubSystem) Clock Controller.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,lpass-sdm845.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sdm845-lpasscc
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 2
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: cc
|
||||
- const: qdsp6ss
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- reg-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@17014000 {
|
||||
compatible = "qcom,sdm845-lpasscc";
|
||||
reg = <0x17014000 0x1f004>, <0x17300000 0x200>;
|
||||
reg-names = "cc", "qdsp6ss";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -10,11 +10,10 @@ maintainers:
|
|||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks and
|
||||
power domains on SM6115.
|
||||
Qualcomm display clock control module provides the clocks and power domains
|
||||
on SM6115.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,sm6115-dispcc.h
|
||||
See also:: include/dt-bindings/clock/qcom,sm6115-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,54 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm6375-dispcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Display Clock & Reset Controller on SM6375
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM6375.
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,dispcc-sm6375.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm6375-dispcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: GPLL0 source from GCC
|
||||
- description: Byte clock from DSI PHY
|
||||
- description: Pixel clock from DSI PHY
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
|
||||
clock-controller@5f00000 {
|
||||
compatible = "qcom,sm6375-dispcc";
|
||||
reg = <0x05f00000 0x20000>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
|
||||
<&dsi_phy 0>,
|
||||
<&dsi_phy 1>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
...
|
||||
|
|
@ -4,17 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller Binding for SM6375
|
||||
title: Qualcomm Global Clock & Reset Controller on SM6375
|
||||
|
||||
maintainers:
|
||||
- Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module which supports the clocks, resets and
|
||||
power domains on SM6375
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM6375
|
||||
|
||||
See also:
|
||||
- dt-bindings/clock/qcom,sm6375-gcc.h
|
||||
See also:: include/dt-bindings/clock/qcom,sm6375-gcc.h
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
|
|
|||
|
|
@ -4,16 +4,16 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
|
||||
title: Qualcomm Camera Clock & Reset Controller on SM8450
|
||||
|
||||
maintainers:
|
||||
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm camera clock control module which supports the clocks, resets and
|
||||
power domains on SM8450.
|
||||
Qualcomm camera clock control module provides the clocks, resets and power
|
||||
domains on SM8450.
|
||||
|
||||
See also include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
See also:: include/dt-bindings/clock/qcom,sm8450-camcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -10,11 +10,10 @@ maintainers:
|
|||
- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
||||
|
||||
description: |
|
||||
Qualcomm display clock control module which supports the clocks, resets and
|
||||
power domains on SM8450.
|
||||
Qualcomm display clock control module provides the clocks, resets and power
|
||||
domains on SM8450.
|
||||
|
||||
See also:
|
||||
include/dt-bindings/clock/qcom,sm8450-dispcc.h
|
||||
See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,62 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Global Clock & Reset Controller on SM8550
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Qualcomm global clock control module provides the clocks, resets and power
|
||||
domains on SM8550
|
||||
|
||||
See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8550-gcc
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Board XO source
|
||||
- description: Sleep clock source
|
||||
- description: PCIE 0 Pipe clock source
|
||||
- description: PCIE 1 Pipe clock source
|
||||
- description: PCIE 1 Phy Auxiliary clock source
|
||||
- description: UFS Phy Rx symbol 0 clock source
|
||||
- description: UFS Phy Rx symbol 1 clock source
|
||||
- description: UFS Phy Tx symbol 0 clock source
|
||||
- description: USB3 Phy wrapper pipe clock source
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
|
||||
allOf:
|
||||
- $ref: qcom,gcc.yaml#
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
clock-controller@100000 {
|
||||
compatible = "qcom,sm8550-gcc";
|
||||
reg = <0x00100000 0x001f4200>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
|
||||
<&pcie0_phy>,
|
||||
<&pcie1_phy>,
|
||||
<&pcie_1_phy_aux_clk>,
|
||||
<&ufs_mem_phy 0>,
|
||||
<&ufs_mem_phy 1>,
|
||||
<&ufs_mem_phy 2>,
|
||||
<&usb_1_qmpphy>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -4,21 +4,21 @@
|
|||
$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Video Clock & Reset Controller Binding
|
||||
title: Qualcomm Video Clock & Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Taniya Das <tdas@codeaurora.org>
|
||||
|
||||
description: |
|
||||
Qualcomm video clock control module which supports the clocks, resets and
|
||||
power domains on Qualcomm SoCs.
|
||||
Qualcomm video clock control module provides the clocks, resets and power
|
||||
domains on Qualcomm SoCs.
|
||||
|
||||
See also:
|
||||
dt-bindings/clock/qcom,videocc-sc7180.h
|
||||
dt-bindings/clock/qcom,videocc-sc7280.h
|
||||
dt-bindings/clock/qcom,videocc-sdm845.h
|
||||
dt-bindings/clock/qcom,videocc-sm8150.h
|
||||
dt-bindings/clock/qcom,videocc-sm8250.h
|
||||
See also::
|
||||
include/dt-bindings/clock/qcom,videocc-sc7180.h
|
||||
include/dt-bindings/clock/qcom,videocc-sc7280.h
|
||||
include/dt-bindings/clock/qcom,videocc-sdm845.h
|
||||
include/dt-bindings/clock/qcom,videocc-sm8150.h
|
||||
include/dt-bindings/clock/qcom,videocc-sm8250.h
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,71 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip rk3588 Family Clock and Reset Control Module
|
||||
|
||||
maintainers:
|
||||
- Elaine Zhang <zhangqing@rock-chips.com>
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
description: |
|
||||
The RK3588 clock controller generates the clock and also implements a reset
|
||||
controller for SoC peripherals. For example it provides SCLK_UART2 and
|
||||
PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
|
||||
module.
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clock and reset IDs
|
||||
are defined as preprocessor macros in dt-binding headers.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,rk3588-cru
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xin24m
|
||||
- const: xin32k
|
||||
|
||||
assigned-clocks: true
|
||||
|
||||
assigned-clock-rates: true
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: >
|
||||
phandle to the syscon managing the "general register files". It is used
|
||||
for GRF muxes, if missing any muxes present in the GRF will not be
|
||||
available.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- "#reset-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
cru: clock-controller@fd7c0000 {
|
||||
compatible = "rockchip,rk3588-cru";
|
||||
reg = <0xfd7c0000 0x5c000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
Binding for TI CDCE913/925/937/949 programmable I2C clock synthesizers.
|
||||
|
||||
Reference
|
||||
This binding uses the common clock binding[1].
|
||||
|
||||
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
[2] https://www.ti.com/product/cdce913
|
||||
[3] https://www.ti.com/product/cdce925
|
||||
[4] https://www.ti.com/product/cdce937
|
||||
[5] https://www.ti.com/product/cdce949
|
||||
|
||||
The driver provides clock sources for each output Y1 through Y5.
|
||||
|
||||
Required properties:
|
||||
- compatible: Shall be one of the following:
|
||||
- "ti,cdce913": 1-PLL, 3 Outputs
|
||||
- "ti,cdce925": 2-PLL, 5 Outputs
|
||||
- "ti,cdce937": 3-PLL, 7 Outputs
|
||||
- "ti,cdce949": 4-PLL, 9 Outputs
|
||||
- reg: I2C device address.
|
||||
- clocks: Points to a fixed parent clock that provides the input frequency.
|
||||
- #clock-cells: From common clock bindings: Shall be 1.
|
||||
|
||||
Optional properties:
|
||||
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
|
||||
board, or to compensate for external influences.
|
||||
- vdd-supply: A regulator node for Vdd
|
||||
- vddout-supply: A regulator node for Vddout
|
||||
|
||||
For all PLL1, PLL2, ... an optional child node can be used to specify spread
|
||||
spectrum clocking parameters for a board.
|
||||
- spread-spectrum: SSC mode as defined in the data sheet.
|
||||
- spread-spectrum-center: Use "centered" mode instead of "max" mode. When
|
||||
present, the clock runs at the requested frequency on average. Otherwise
|
||||
the requested frequency is the maximum value of the SCC range.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
clockgen: cdce925pw@64 {
|
||||
compatible = "cdce925";
|
||||
reg = <0x64>;
|
||||
clocks = <&xtal_27Mhz>;
|
||||
#clock-cells = <1>;
|
||||
xtal-load-pf = <5>;
|
||||
vdd-supply = <&1v8-reg>;
|
||||
vddout-supply = <&3v3-reg>;
|
||||
/* PLL options to get SSC 1% centered */
|
||||
PLL2 {
|
||||
spread-spectrum = <4>;
|
||||
spread-spectrum-center;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/ti,cdce925.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI CDCE913/925/937/949 programmable I2C clock synthesizers
|
||||
|
||||
maintainers:
|
||||
- Alexander Stein <alexander.stein@ew.tq-group.com>
|
||||
|
||||
description: |
|
||||
Flexible Low Power LVCMOS Clock Generator with SSC Support for EMI Reduction
|
||||
|
||||
- CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
|
||||
- CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
|
||||
- CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
|
||||
- CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- ti,cdce913
|
||||
- ti,cdce925
|
||||
- ti,cdce937
|
||||
- ti,cdce949
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: fixed parent clock
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
vdd-supply:
|
||||
description: Regulator that provides 1.8V Vdd power supply
|
||||
|
||||
vddout-supply:
|
||||
description: |
|
||||
Regulator that provides Vddout power supply.
|
||||
non-L variant: 2.5V or 3.3V for
|
||||
L variant: 1.8V for
|
||||
|
||||
xtal-load-pf:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Crystal load-capacitor value to fine-tune performance on a
|
||||
board, or to compensate for external influences.
|
||||
|
||||
patternProperties:
|
||||
"^PLL[1-4]$":
|
||||
type: object
|
||||
description: |
|
||||
optional child node can be used to specify spread
|
||||
spectrum clocking parameters for a board
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
spread-spectrum:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: SSC mode as defined in the data sheet
|
||||
|
||||
spread-spectrum-center:
|
||||
type: boolean
|
||||
description: |
|
||||
Use "centered" mode instead of "max" mode. When
|
||||
present, the clock runs at the requested frequency on average.
|
||||
Otherwise the requested frequency is the maximum value of the
|
||||
SCC range.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cdce925: clock-controller@64 {
|
||||
compatible = "ti,cdce925";
|
||||
reg = <0x64>;
|
||||
clocks = <&xtal_27Mhz>;
|
||||
#clock-cells = <1>;
|
||||
xtal-load-pf = <5>;
|
||||
vdd-supply = <®_1v8>;
|
||||
vddout-supply = <®_3v3>;
|
||||
/* PLL options to get SSC 1% centered */
|
||||
PLL2 {
|
||||
spread-spectrum = <4>;
|
||||
spread-spectrum-center;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -96,9 +96,9 @@ static int __clk_bulk_get(struct device *dev, int num_clks,
|
|||
if (ret == -ENOENT && optional)
|
||||
continue;
|
||||
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "Failed to get clk '%s': %d\n",
|
||||
clks[i].id, ret);
|
||||
dev_err_probe(dev, ret,
|
||||
"Failed to get clk '%s'\n",
|
||||
clks[i].id);
|
||||
goto err;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -603,28 +603,15 @@ of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
|
|||
return &data->clk[idx].hw;
|
||||
}
|
||||
|
||||
static void cdce925_regulator_disable(void *regulator)
|
||||
{
|
||||
regulator_disable(regulator);
|
||||
}
|
||||
|
||||
static int cdce925_regulator_enable(struct device *dev, const char *name)
|
||||
{
|
||||
struct regulator *regulator;
|
||||
int err;
|
||||
|
||||
regulator = devm_regulator_get(dev, name);
|
||||
if (IS_ERR(regulator))
|
||||
return PTR_ERR(regulator);
|
||||
err = devm_regulator_get_enable(dev, name);
|
||||
if (err)
|
||||
dev_err_probe(dev, err, "Failed to enable %s:\n", name);
|
||||
|
||||
err = regulator_enable(regulator);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed to enable %s: %d\n", name, err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return devm_add_action_or_reset(dev, cdce925_regulator_disable,
|
||||
regulator);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* The CDCE925 uses a funky way to read/write registers. Bulk mode is
|
||||
|
|
|
|||
|
|
@ -38,12 +38,15 @@
|
|||
* saturated values.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/math.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/rational.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
#include "clk-fractional-divider.h"
|
||||
|
||||
|
|
@ -63,14 +66,12 @@ static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
|
|||
writel(val, fd->reg);
|
||||
}
|
||||
|
||||
static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
static void clk_fd_get_div(struct clk_hw *hw, struct u32_fract *fract)
|
||||
{
|
||||
struct clk_fractional_divider *fd = to_clk_fd(hw);
|
||||
unsigned long flags = 0;
|
||||
unsigned long m, n;
|
||||
u32 val;
|
||||
u64 ret;
|
||||
|
||||
if (fd->lock)
|
||||
spin_lock_irqsave(fd->lock, flags);
|
||||
|
|
@ -92,11 +93,22 @@ static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
|
|||
n++;
|
||||
}
|
||||
|
||||
if (!n || !m)
|
||||
fract->numerator = m;
|
||||
fract->denominator = n;
|
||||
}
|
||||
|
||||
static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct u32_fract fract;
|
||||
u64 ret;
|
||||
|
||||
clk_fd_get_div(hw, &fract);
|
||||
|
||||
if (!fract.numerator || !fract.denominator)
|
||||
return parent_rate;
|
||||
|
||||
ret = (u64)parent_rate * m;
|
||||
do_div(ret, n);
|
||||
ret = (u64)parent_rate * fract.numerator;
|
||||
do_div(ret, fract.denominator);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -183,10 +195,45 @@ static int clk_fd_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
static int clk_fd_numerator_get(void *hw, u64 *val)
|
||||
{
|
||||
struct u32_fract fract;
|
||||
|
||||
clk_fd_get_div(hw, &fract);
|
||||
|
||||
*val = fract.numerator;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(clk_fd_numerator_fops, clk_fd_numerator_get, NULL, "%llu\n");
|
||||
|
||||
static int clk_fd_denominator_get(void *hw, u64 *val)
|
||||
{
|
||||
struct u32_fract fract;
|
||||
|
||||
clk_fd_get_div(hw, &fract);
|
||||
|
||||
*val = fract.denominator;
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_DEBUGFS_ATTRIBUTE(clk_fd_denominator_fops, clk_fd_denominator_get, NULL, "%llu\n");
|
||||
|
||||
static void clk_fd_debug_init(struct clk_hw *hw, struct dentry *dentry)
|
||||
{
|
||||
debugfs_create_file("numerator", 0444, dentry, hw, &clk_fd_numerator_fops);
|
||||
debugfs_create_file("denominator", 0444, dentry, hw, &clk_fd_denominator_fops);
|
||||
}
|
||||
#endif
|
||||
|
||||
const struct clk_ops clk_fractional_divider_ops = {
|
||||
.recalc_rate = clk_fd_recalc_rate,
|
||||
.round_rate = clk_fd_round_rate,
|
||||
.set_rate = clk_fd_set_rate,
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
.debug_init = clk_fd_debug_init,
|
||||
#endif
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_fractional_divider_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,12 +12,10 @@
|
|||
#include <linux/bitfield.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/gcd.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/uaccess.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/spi/spi.h>
|
||||
|
||||
|
|
@ -177,14 +175,14 @@ enum lmk04832_device_types {
|
|||
};
|
||||
|
||||
/**
|
||||
* lmk04832_device_info - Holds static device information that is specific to
|
||||
* the chip revision
|
||||
* struct lmk04832_device_info - Holds static device information that is
|
||||
* specific to the chip revision
|
||||
*
|
||||
* pid: Product Identifier
|
||||
* maskrev: IC version identifier
|
||||
* num_channels: Number of available output channels (clkout count)
|
||||
* vco0_range: {min, max} of the VCO0 operating range (in MHz)
|
||||
* vco1_range: {min, max} of the VCO1 operating range (in MHz)
|
||||
* @pid: Product Identifier
|
||||
* @maskrev: IC version identifier
|
||||
* @num_channels: Number of available output channels (clkout count)
|
||||
* @vco0_range: {min, max} of the VCO0 operating range (in MHz)
|
||||
* @vco1_range: {min, max} of the VCO1 operating range (in MHz)
|
||||
*/
|
||||
struct lmk04832_device_info {
|
||||
u16 pid;
|
||||
|
|
@ -282,7 +280,7 @@ static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
|
|||
default:
|
||||
return false;
|
||||
};
|
||||
};
|
||||
}
|
||||
|
||||
static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
|
||||
{
|
||||
|
|
@ -305,7 +303,7 @@ static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
|
|||
default:
|
||||
return false;
|
||||
};
|
||||
};
|
||||
}
|
||||
|
||||
static const struct regmap_config regmap_config = {
|
||||
.name = "lmk04832",
|
||||
|
|
@ -371,7 +369,7 @@ static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
|
|||
unsigned long prate)
|
||||
{
|
||||
struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
|
||||
unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
|
||||
const unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
|
||||
unsigned int pll2_n, p, pll2_r;
|
||||
unsigned int pll2_misc;
|
||||
unsigned long vco_rate;
|
||||
|
|
@ -403,7 +401,7 @@ static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
|
|||
pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
|
||||
|
||||
return vco_rate;
|
||||
};
|
||||
}
|
||||
|
||||
/**
|
||||
* lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
|
||||
|
|
@ -414,7 +412,7 @@ static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
|
|||
* The LMK04832 has 2 internal VCO, each with independent operating ranges.
|
||||
* Use the device_info structure to determine which VCO to use based on rate.
|
||||
*
|
||||
* Returns VCO_MUX value or negative errno.
|
||||
* Returns: VCO_MUX value or negative errno.
|
||||
*/
|
||||
static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
|
||||
{
|
||||
|
|
@ -451,7 +449,7 @@ static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
|
|||
*
|
||||
* VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
|
||||
*
|
||||
* Returns vco rate or negative errno.
|
||||
* Returns: vco rate or negative errno.
|
||||
*/
|
||||
static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
|
||||
unsigned int *n, unsigned int *p,
|
||||
|
|
@ -509,7 +507,7 @@ static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return -EINVAL;
|
||||
|
||||
return vco_rate;
|
||||
};
|
||||
}
|
||||
|
||||
static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate)
|
||||
|
|
@ -568,7 +566,7 @@ static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
|
||||
FIELD_GET(0x0000ff, n));
|
||||
};
|
||||
}
|
||||
|
||||
static const struct clk_ops lmk04832_vco_ops = {
|
||||
.is_enabled = lmk04832_vco_is_enabled,
|
||||
|
|
@ -633,7 +631,7 @@ static int lmk04832_register_vco(struct lmk04832 *lmk)
|
|||
|
||||
static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
|
||||
{
|
||||
int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
|
||||
const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
|
||||
unsigned int sclkx_y_ddly = 10;
|
||||
unsigned int dclkx_y_ddly;
|
||||
unsigned int dclkx_y_div;
|
||||
|
|
@ -1063,7 +1061,7 @@ static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
|
|||
rate = DIV_ROUND_CLOSEST(prate, dclk_div);
|
||||
|
||||
return rate;
|
||||
};
|
||||
}
|
||||
|
||||
static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
|
|
@ -1085,7 +1083,7 @@ static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return -EINVAL;
|
||||
|
||||
return dclk_rate;
|
||||
};
|
||||
}
|
||||
|
||||
static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate)
|
||||
|
|
@ -1147,7 +1145,7 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
dev_err(lmk->dev, "SYNC sequence failed\n");
|
||||
|
||||
return ret;
|
||||
};
|
||||
}
|
||||
|
||||
static const struct clk_ops lmk04832_dclk_ops = {
|
||||
.is_enabled = lmk04832_dclk_is_enabled,
|
||||
|
|
@ -1551,6 +1549,7 @@ static void lmk04832_remove(struct spi_device *spi)
|
|||
clk_disable_unprepare(lmk->oscin);
|
||||
of_clk_del_provider(spi->dev.of_node);
|
||||
}
|
||||
|
||||
static const struct spi_device_id lmk04832_id[] = {
|
||||
{ "lmk04832", LMK04832 },
|
||||
{}
|
||||
|
|
|
|||
|
|
@ -138,7 +138,7 @@ out_put:
|
|||
}
|
||||
|
||||
/**
|
||||
* struct clk_pll1 - Nomadik PLL1 clock
|
||||
* struct clk_pll - Nomadik PLL clock
|
||||
* @hw: corresponding clock hardware entry
|
||||
* @id: PLL instance: 1 or 2
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -155,7 +155,7 @@ static const char * const eth_src[] = {
|
|||
"pll4_p", "pll3_q"
|
||||
};
|
||||
|
||||
const struct clk_parent_data ethrx_src[] = {
|
||||
static const struct clk_parent_data ethrx_src[] = {
|
||||
{ .name = "ethck_k", .fw_name = "ETH_RX_CLK/ETH_REF_CLK" },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -20,7 +20,6 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/rational.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -603,10 +603,15 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
|
|||
}
|
||||
|
||||
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
|
||||
|
||||
trace_clk_rate_request_start(&parent_req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(parent, &parent_req);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
trace_clk_rate_request_done(&parent_req);
|
||||
|
||||
best = parent_req.rate;
|
||||
} else if (parent) {
|
||||
best = clk_core_get_rate_nolock(parent);
|
||||
|
|
@ -630,10 +635,15 @@ int clk_mux_determine_rate_flags(struct clk_hw *hw,
|
|||
struct clk_rate_request parent_req;
|
||||
|
||||
clk_core_forward_rate_req(core, req, parent, &parent_req, req->rate);
|
||||
|
||||
trace_clk_rate_request_start(&parent_req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(parent, &parent_req);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
trace_clk_rate_request_done(&parent_req);
|
||||
|
||||
parent_rate = parent_req.rate;
|
||||
} else {
|
||||
parent_rate = clk_core_get_rate_nolock(parent);
|
||||
|
|
@ -1468,6 +1478,7 @@ static void clk_core_init_rate_req(struct clk_core * const core,
|
|||
if (!core)
|
||||
return;
|
||||
|
||||
req->core = core;
|
||||
req->rate = rate;
|
||||
clk_core_get_boundaries(core, &req->min_rate, &req->max_rate);
|
||||
|
||||
|
|
@ -1550,10 +1561,15 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
|
|||
struct clk_rate_request parent_req;
|
||||
|
||||
clk_core_forward_rate_req(core, req, core->parent, &parent_req, req->rate);
|
||||
|
||||
trace_clk_rate_request_start(&parent_req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(core->parent, &parent_req);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
trace_clk_rate_request_done(&parent_req);
|
||||
|
||||
req->best_parent_rate = parent_req.rate;
|
||||
req->rate = parent_req.rate;
|
||||
|
||||
|
|
@ -1604,10 +1620,14 @@ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate)
|
|||
|
||||
clk_core_init_rate_req(hw->core, &req, rate);
|
||||
|
||||
trace_clk_rate_request_start(&req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(hw->core, &req);
|
||||
if (ret)
|
||||
return 0;
|
||||
|
||||
trace_clk_rate_request_done(&req);
|
||||
|
||||
return req.rate;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_hw_round_rate);
|
||||
|
|
@ -1636,8 +1656,12 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
|
|||
|
||||
clk_core_init_rate_req(clk->core, &req, rate);
|
||||
|
||||
trace_clk_rate_request_start(&req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(clk->core, &req);
|
||||
|
||||
trace_clk_rate_request_done(&req);
|
||||
|
||||
if (clk->exclusive_count)
|
||||
clk_core_rate_protect(clk->core);
|
||||
|
||||
|
|
@ -2129,10 +2153,14 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
|
|||
|
||||
clk_core_init_rate_req(core, &req, rate);
|
||||
|
||||
trace_clk_rate_request_start(&req);
|
||||
|
||||
ret = clk_core_determine_round_nolock(core, &req);
|
||||
if (ret < 0)
|
||||
return NULL;
|
||||
|
||||
trace_clk_rate_request_done(&req);
|
||||
|
||||
best_parent_rate = req.best_parent_rate;
|
||||
new_rate = req.rate;
|
||||
parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
|
||||
|
|
@ -2328,8 +2356,12 @@ static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
|
|||
|
||||
clk_core_init_rate_req(core, &req, req_rate);
|
||||
|
||||
trace_clk_rate_request_start(&req);
|
||||
|
||||
ret = clk_core_round_rate_nolock(core, &req);
|
||||
|
||||
trace_clk_rate_request_done(&req);
|
||||
|
||||
/* restore the protection */
|
||||
clk_core_rate_restore_protect(core, cnt);
|
||||
|
||||
|
|
|
|||
|
|
@ -91,12 +91,12 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
hws[IMX6SLL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
|
||||
hws[IMX6SLL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
|
||||
hws[IMX6SLL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
|
||||
hws[IMX6SLL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
|
||||
hws[IMX6SLL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");
|
||||
|
||||
/* ipp_di clock is external input */
|
||||
hws[IMX6SLL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
|
||||
hws[IMX6SLL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
|
||||
hws[IMX6SLL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");
|
||||
hws[IMX6SLL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sll-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -132,16 +132,16 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
hws[IMX6SX_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
|
||||
hws[IMX6SX_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
|
||||
hws[IMX6SX_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
|
||||
hws[IMX6SX_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
|
||||
hws[IMX6SX_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");
|
||||
|
||||
/* ipp_di clock is external input */
|
||||
hws[IMX6SX_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
|
||||
hws[IMX6SX_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
|
||||
hws[IMX6SX_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");
|
||||
hws[IMX6SX_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");
|
||||
|
||||
/* Clock source from external clock via CLK1/2 PAD */
|
||||
hws[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk1");
|
||||
hws[IMX6SX_CLK_ANACLK2] = imx_obtain_fixed_clk_hw(ccm_node, "anaclk2");
|
||||
hws[IMX6SX_CLK_ANACLK1] = imx_get_clk_hw_by_name(ccm_node, "anaclk1");
|
||||
hws[IMX6SX_CLK_ANACLK2] = imx_get_clk_hw_by_name(ccm_node, "anaclk2");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -126,12 +126,12 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
|
|||
|
||||
hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
|
||||
hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
|
||||
hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
|
||||
hws[IMX6UL_CLK_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
|
||||
hws[IMX6UL_CLK_OSC] = imx_get_clk_hw_by_name(ccm_node, "osc");
|
||||
|
||||
/* ipp_di clock is external input */
|
||||
hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
|
||||
hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
|
||||
hws[IMX6UL_CLK_IPP_DI0] = imx_get_clk_hw_by_name(ccm_node, "ipp_di0");
|
||||
hws[IMX6UL_CLK_IPP_DI1] = imx_get_clk_hw_by_name(ccm_node, "ipp_di1");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -391,8 +391,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
hws = clk_hw_data->hws;
|
||||
|
||||
hws[IMX7D_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
hws[IMX7D_OSC_24M_CLK] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
|
||||
hws[IMX7D_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
|
||||
hws[IMX7D_OSC_24M_CLK] = imx_get_clk_hw_by_name(ccm_node, "osc");
|
||||
hws[IMX7D_CKIL] = imx_get_clk_hw_by_name(ccm_node, "ckil");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -59,11 +59,11 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np)
|
|||
|
||||
hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
|
||||
hws[IMX7ULP_CLK_ROSC] = imx_obtain_fixed_clk_hw(np, "rosc");
|
||||
hws[IMX7ULP_CLK_SOSC] = imx_obtain_fixed_clk_hw(np, "sosc");
|
||||
hws[IMX7ULP_CLK_SIRC] = imx_obtain_fixed_clk_hw(np, "sirc");
|
||||
hws[IMX7ULP_CLK_FIRC] = imx_obtain_fixed_clk_hw(np, "firc");
|
||||
hws[IMX7ULP_CLK_UPLL] = imx_obtain_fixed_clk_hw(np, "upll");
|
||||
hws[IMX7ULP_CLK_ROSC] = imx_get_clk_hw_by_name(np, "rosc");
|
||||
hws[IMX7ULP_CLK_SOSC] = imx_get_clk_hw_by_name(np, "sosc");
|
||||
hws[IMX7ULP_CLK_SIRC] = imx_get_clk_hw_by_name(np, "sirc");
|
||||
hws[IMX7ULP_CLK_FIRC] = imx_get_clk_hw_by_name(np, "firc");
|
||||
hws[IMX7ULP_CLK_UPLL] = imx_get_clk_hw_by_name(np, "upll");
|
||||
|
||||
/* SCG1 */
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -312,12 +312,12 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws = clk_hw_data->hws;
|
||||
|
||||
hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
hws[IMX8MM_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
|
||||
hws[IMX8MM_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
|
||||
hws[IMX8MM_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
|
||||
hws[IMX8MM_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
|
||||
hws[IMX8MM_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
|
||||
hws[IMX8MM_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
|
||||
hws[IMX8MM_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
|
||||
hws[IMX8MM_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
|
||||
hws[IMX8MM_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
|
||||
hws[IMX8MM_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
|
||||
hws[IMX8MM_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
|
||||
hws[IMX8MM_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -27,10 +27,10 @@ static u32 share_count_nand;
|
|||
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", };
|
||||
static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", };
|
||||
static const char * const video_pll_bypass_sels[] = {"video_pll", "video_pll_ref_sel", };
|
||||
static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
|
||||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
static const char * const m7_alt_pll_bypass_sels[] = {"m7_alt_pll", "m7_alt_pll_ref_sel", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
|
||||
|
||||
|
|
@ -40,24 +40,24 @@ static const char * const imx8mn_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pl
|
|||
|
||||
static const char * const imx8mn_a53_core_sels[] = {"arm_a53_div", "arm_pll_out", };
|
||||
|
||||
static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "vpu_pll_out",
|
||||
"sys_pll1_800m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
|
||||
static const char * const imx8mn_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", "m7_alt_pll_out",
|
||||
"sys_pll1_800m", "audio_pll1_out", "video_pll_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
"video_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
"video_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll1_100m",};
|
||||
"video_pll_out", "sys_pll1_100m",};
|
||||
|
||||
static const char * const imx8mn_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out",
|
||||
"video_pll1_out", "sys_pll3_out", };
|
||||
"video_pll_out", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mn_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m",
|
||||
"sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out",
|
||||
|
|
@ -77,23 +77,23 @@ static const char * const imx8mn_usb_bus_sels[] = {"osc_24m", "sys_pll2_500m", "
|
|||
|
||||
static const char * const imx8mn_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
"video_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
"video_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"video_pll1_out", "audio_pll2_out", };
|
||||
"video_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m",
|
||||
"sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
"audio_pll1_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m",
|
||||
"sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out",
|
||||
"audio_pll1_out", "video_pll1_out", };
|
||||
"audio_pll1_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m",
|
||||
"sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
|
|
@ -103,49 +103,49 @@ static const char * const imx8mn_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m",
|
|||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
|
||||
static const char * const imx8mn_disp_pixel_sels[] = {"osc_24m", "video_pll_out", "audio_pll2_out",
|
||||
"audio_pll1_out", "sys_pll1_800m", "sys_pll2_1000m",
|
||||
"sys_pll3_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
"video_pll_out", "sys_pll1_133m", "dummy",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"video_pll_out", "sys_pll1_133m", "dummy",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"video_pll_out", "sys_pll1_133m", "dummy",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"video_pll_out", "sys_pll1_133m", "dummy",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"video_pll_out", "sys_pll1_133m", "dummy",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_spdif1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out",
|
||||
"video_pll1_out", "sys_pll1_133m", "osc_hdmi",
|
||||
"video_pll_out", "sys_pll1_133m", "dummy",
|
||||
"clk_ext2", "clk_ext3", };
|
||||
|
||||
static const char * const imx8mn_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m",
|
||||
"sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out",
|
||||
"video_pll1_out", "clk_ext4", };
|
||||
"video_pll_out", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mn_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "video_pll1_out", };
|
||||
"clk_ext4", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_enet_phy_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m",
|
||||
"sys_pll2_200m", "sys_pll2_500m", "video_pll1_out",
|
||||
"audio_pll2_out", };
|
||||
"sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"video_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mn_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out",
|
||||
"sys_pll1_400m", "audio_pll2_out", "sys_pll3_out",
|
||||
"sys_pll2_250m", "video_pll1_out", };
|
||||
"sys_pll2_250m", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m",
|
||||
"sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m",
|
||||
|
|
@ -160,19 +160,19 @@ static const char * const imx8mn_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "s
|
|||
"audio_pll2_out", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll1_out",
|
||||
"sys_pll3_out", "audio_pll1_out", "video_pll_out",
|
||||
"audio_pll2_out", "sys_pll1_133m", };
|
||||
|
||||
static const char * const imx8mn_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m",
|
||||
|
|
@ -213,63 +213,63 @@ static const char * const imx8mn_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "s
|
|||
|
||||
static const char * const imx8mn_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
"sys_pll1_80m", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext1",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
"sys_pll1_80m", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
"sys_pll1_80m", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m",
|
||||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
"sys_pll1_80m", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"sys_pll1_40m", "video_pll_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
|
||||
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
|
||||
"m7_alt_pll_out", "sys_pll2_125m", "sys_pll3_out",
|
||||
"sys_pll1_80m", "sys_pll2_166m", };
|
||||
|
||||
static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out",
|
||||
static const char * const imx8mn_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "m7_alt_pll_out",
|
||||
"sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m",
|
||||
"sys_pll2_500m", "sys_pll1_100m", };
|
||||
|
||||
static const char * const imx8mn_dsi_core_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
"audio_pll2_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_phy_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
"audio_pll2_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_dsi_dbi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
"audio_pll2_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m",
|
||||
"sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m",
|
||||
|
|
@ -277,15 +277,15 @@ static const char * const imx8mn_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "s
|
|||
|
||||
static const char * const imx8mn_camera_pixel_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
"audio_pll2_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_csi1_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
"audio_pll2_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_phy_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "clk_ext2",
|
||||
"audio_pll2_out", "video_pll1_out", };
|
||||
"audio_pll2_out", "video_pll_out", };
|
||||
|
||||
static const char * const imx8mn_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m",
|
||||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
|
|
@ -306,9 +306,9 @@ static const char * const imx8mn_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "du
|
|||
"dummy", "sys_pll1_80m", };
|
||||
static const char * const imx8mn_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m",
|
||||
"sys_pll2_166m", "sys_pll3_out", "audio_pll1_out",
|
||||
"video_pll1_out", "osc_32k", };
|
||||
"video_pll_out", "osc_32k", };
|
||||
|
||||
static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
|
||||
static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll_out",
|
||||
"dummy", "dummy", "gpu_pll_out", "dummy",
|
||||
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
|
||||
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
|
||||
|
|
@ -332,12 +332,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws = clk_hw_data->hws;
|
||||
|
||||
hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
hws[IMX8MN_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
|
||||
hws[IMX8MN_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
|
||||
hws[IMX8MN_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
|
||||
hws[IMX8MN_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
|
||||
hws[IMX8MN_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
|
||||
hws[IMX8MN_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
|
||||
hws[IMX8MN_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
|
||||
hws[IMX8MN_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
|
||||
hws[IMX8MN_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
|
||||
hws[IMX8MN_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
|
||||
hws[IMX8MN_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
|
||||
hws[IMX8MN_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mn-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
@ -349,19 +349,19 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
||||
hws[IMX8MN_AUDIO_PLL1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", base, &imx_1443x_pll);
|
||||
hws[IMX8MN_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);
|
||||
hws[IMX8MN_VIDEO_PLL1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", base + 0x28, &imx_1443x_pll);
|
||||
hws[IMX8MN_VIDEO_PLL] = imx_clk_hw_pll14xx("video_pll", "video_pll_ref_sel", base + 0x28, &imx_1443x_pll);
|
||||
hws[IMX8MN_DRAM_PLL] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50, &imx_1443x_dram_pll);
|
||||
hws[IMX8MN_GPU_PLL] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", base + 0x64, &imx_1416x_pll);
|
||||
hws[IMX8MN_VPU_PLL] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", base + 0x74, &imx_1416x_pll);
|
||||
hws[IMX8MN_M7_ALT_PLL] = imx_clk_hw_pll14xx("m7_alt_pll", "m7_alt_pll_ref_sel", base + 0x74, &imx_1416x_pll);
|
||||
hws[IMX8MN_ARM_PLL] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84, &imx_1416x_pll);
|
||||
hws[IMX8MN_SYS_PLL1] = imx_clk_hw_fixed("sys_pll1", 800000000);
|
||||
hws[IMX8MN_SYS_PLL2] = imx_clk_hw_fixed("sys_pll2", 1000000000);
|
||||
|
|
@ -370,20 +370,20 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
/* PLL bypass out */
|
||||
hws[IMX8MN_AUDIO_PLL1_BYPASS] = imx_clk_hw_mux_flags("audio_pll1_bypass", base, 16, 1, audio_pll1_bypass_sels, ARRAY_SIZE(audio_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_AUDIO_PLL2_BYPASS] = imx_clk_hw_mux_flags("audio_pll2_bypass", base + 0x14, 16, 1, audio_pll2_bypass_sels, ARRAY_SIZE(audio_pll2_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_VIDEO_PLL1_BYPASS] = imx_clk_hw_mux_flags("video_pll1_bypass", base + 0x28, 16, 1, video_pll1_bypass_sels, ARRAY_SIZE(video_pll1_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_VIDEO_PLL_BYPASS] = imx_clk_hw_mux_flags("video_pll_bypass", base + 0x28, 16, 1, video_pll_bypass_sels, ARRAY_SIZE(video_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_DRAM_PLL_BYPASS] = imx_clk_hw_mux_flags("dram_pll_bypass", base + 0x50, 16, 1, dram_pll_bypass_sels, ARRAY_SIZE(dram_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_GPU_PLL_BYPASS] = imx_clk_hw_mux_flags("gpu_pll_bypass", base + 0x64, 28, 1, gpu_pll_bypass_sels, ARRAY_SIZE(gpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_VPU_PLL_BYPASS] = imx_clk_hw_mux_flags("vpu_pll_bypass", base + 0x74, 28, 1, vpu_pll_bypass_sels, ARRAY_SIZE(vpu_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_M7_ALT_PLL_BYPASS] = imx_clk_hw_mux_flags("m7_alt_pll_bypass", base + 0x74, 28, 1, m7_alt_pll_bypass_sels, ARRAY_SIZE(m7_alt_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_ARM_PLL_BYPASS] = imx_clk_hw_mux_flags("arm_pll_bypass", base + 0x84, 28, 1, arm_pll_bypass_sels, ARRAY_SIZE(arm_pll_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
hws[IMX8MN_SYS_PLL3_BYPASS] = imx_clk_hw_mux_flags("sys_pll3_bypass", base + 0x114, 28, 1, sys_pll3_bypass_sels, ARRAY_SIZE(sys_pll3_bypass_sels), CLK_SET_RATE_PARENT);
|
||||
|
||||
/* PLL out gate */
|
||||
hws[IMX8MN_AUDIO_PLL1_OUT] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", base, 13);
|
||||
hws[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
|
||||
hws[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
|
||||
hws[IMX8MN_VIDEO_PLL_OUT] = imx_clk_hw_gate("video_pll_out", "video_pll_bypass", base + 0x28, 13);
|
||||
hws[IMX8MN_DRAM_PLL_OUT] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
|
||||
hws[IMX8MN_GPU_PLL_OUT] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
|
||||
hws[IMX8MN_VPU_PLL_OUT] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
|
||||
hws[IMX8MN_M7_ALT_PLL_OUT] = imx_clk_hw_gate("m7_alt_pll_out", "m7_alt_pll_bypass", base + 0x74, 11);
|
||||
hws[IMX8MN_ARM_PLL_OUT] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
|
||||
hws[IMX8MN_SYS_PLL3_OUT] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
|
||||
static u32 share_count_nand;
|
||||
static u32 share_count_media;
|
||||
static u32 share_count_usb;
|
||||
static u32 share_count_audio;
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
|
||||
static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
|
||||
|
|
@ -436,12 +438,12 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws = clk_hw_data->hws;
|
||||
|
||||
hws[IMX8MP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
hws[IMX8MP_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
|
||||
hws[IMX8MP_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
|
||||
hws[IMX8MP_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
|
||||
hws[IMX8MP_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
|
||||
hws[IMX8MP_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
|
||||
hws[IMX8MP_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
|
||||
hws[IMX8MP_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
|
||||
hws[IMX8MP_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
|
||||
hws[IMX8MP_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
|
||||
hws[IMX8MP_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
|
||||
hws[IMX8MP_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
|
||||
hws[IMX8MP_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
|
||||
|
||||
hws[IMX8MP_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
hws[IMX8MP_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
|
||||
|
|
@ -673,7 +675,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
|
||||
hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
|
||||
hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
|
||||
hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0);
|
||||
hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb);
|
||||
hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0, &share_count_usb);
|
||||
hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
|
||||
hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
|
||||
hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);
|
||||
|
|
@ -699,7 +702,16 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
|
||||
hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0);
|
||||
hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
|
||||
hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0);
|
||||
|
||||
hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio);
|
||||
|
||||
hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
hws[IMX8MP_CLK_A53_CORE]->clk,
|
||||
|
|
|
|||
|
|
@ -297,13 +297,13 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws = clk_hw_data->hws;
|
||||
|
||||
hws[IMX8MQ_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
hws[IMX8MQ_CLK_32K] = imx_obtain_fixed_clk_hw(np, "ckil");
|
||||
hws[IMX8MQ_CLK_25M] = imx_obtain_fixed_clk_hw(np, "osc_25m");
|
||||
hws[IMX8MQ_CLK_27M] = imx_obtain_fixed_clk_hw(np, "osc_27m");
|
||||
hws[IMX8MQ_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
|
||||
hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
|
||||
hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
|
||||
hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
|
||||
hws[IMX8MQ_CLK_32K] = imx_get_clk_hw_by_name(np, "ckil");
|
||||
hws[IMX8MQ_CLK_25M] = imx_get_clk_hw_by_name(np, "osc_25m");
|
||||
hws[IMX8MQ_CLK_27M] = imx_get_clk_hw_by_name(np, "osc_27m");
|
||||
hws[IMX8MQ_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
|
||||
hws[IMX8MQ_CLK_EXT2] = imx_get_clk_hw_by_name(np, "clk_ext2");
|
||||
hws[IMX8MQ_CLK_EXT3] = imx_get_clk_hw_by_name(np, "clk_ext3");
|
||||
hws[IMX8MQ_CLK_EXT4] = imx_get_clk_hw_by_name(np, "clk_ext4");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
|
|
|
|||
|
|
@ -64,13 +64,9 @@ static const struct imx93_clk_root {
|
|||
{ IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_FLEXIO2, "flexio2_root", 0x0580, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_LPIT1, "lpit1_root", 0x0600, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_LPIT2, "lpit2_root", 0x0680, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_LPTMR1, "lptmr1_root", 0x0700, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_LPTMR2, "lptmr2_root", 0x0780, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_TPM1, "tpm1_root", 0x0800, TPM_SEL, },
|
||||
{ IMX93_CLK_TPM2, "tpm2_root", 0x0880, TPM_SEL, },
|
||||
{ IMX93_CLK_TPM3, "tpm3_root", 0x0900, TPM_SEL, },
|
||||
{ IMX93_CLK_TPM4, "tpm4_root", 0x0980, TPM_SEL, },
|
||||
{ IMX93_CLK_TPM5, "tpm5_root", 0x0a00, TPM_SEL, },
|
||||
{ IMX93_CLK_TPM6, "tpm6_root", 0x0a80, TPM_SEL, },
|
||||
|
|
@ -113,7 +109,11 @@ static const struct imx93_clk_root {
|
|||
{ IMX93_CLK_CCM_CKO2, "ccm_cko2_root", 0x1d00, CKO2_SEL, },
|
||||
{ IMX93_CLK_CCM_CKO3, "ccm_cko3_root", 0x1d80, CKO1_SEL, },
|
||||
{ IMX93_CLK_CCM_CKO4, "ccm_cko4_root", 0x1e00, CKO2_SEL, },
|
||||
{ IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, },
|
||||
/*
|
||||
* Critical because clk is used for handshake between HSIOMIX and NICMIX when
|
||||
* NICMIX power down/on during system suspend/resume
|
||||
*/
|
||||
{ IMX93_CLK_HSIO, "hsio_root", 0x1e80, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL},
|
||||
{ IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, },
|
||||
{ IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, },
|
||||
|
|
@ -170,20 +170,20 @@ static const struct imx93_clk_ccgr {
|
|||
{ IMX93_CLK_MU2_B_GATE, "mu2_b", "bus_wakeup_root", 0x8500, 0, &share_count_mub },
|
||||
{ IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, },
|
||||
{ IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, },
|
||||
{ IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, },
|
||||
{ IMX93_CLK_FLEXSPI1_GATE, "flexspi1", "flexspi1_root", 0x8640, },
|
||||
{ IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, },
|
||||
{ IMX93_CLK_GPIO2_GATE, "gpio2", "bus_wakeup_root", 0x88c0, },
|
||||
{ IMX93_CLK_GPIO3_GATE, "gpio3", "bus_wakeup_root", 0x8900, },
|
||||
{ IMX93_CLK_GPIO4_GATE, "gpio4", "bus_wakeup_root", 0x8940, },
|
||||
{ IMX93_CLK_FLEXIO1_GATE, "flexio1", "flexio1_root", 0x8980, },
|
||||
{ IMX93_CLK_FLEXIO2_GATE, "flexio2", "flexio2_root", 0x89c0, },
|
||||
{ IMX93_CLK_LPIT1_GATE, "lpit1", "lpit1_root", 0x8a00, },
|
||||
{ IMX93_CLK_LPIT2_GATE, "lpit2", "lpit2_root", 0x8a40, },
|
||||
{ IMX93_CLK_LPIT1_GATE, "lpit1", "bus_aon_root", 0x8a00, },
|
||||
{ IMX93_CLK_LPIT2_GATE, "lpit2", "bus_wakeup_root", 0x8a40, },
|
||||
{ IMX93_CLK_LPTMR1_GATE, "lptmr1", "lptmr1_root", 0x8a80, },
|
||||
{ IMX93_CLK_LPTMR2_GATE, "lptmr2", "lptmr2_root", 0x8ac0, },
|
||||
{ IMX93_CLK_TPM1_GATE, "tpm1", "tpm1_root", 0x8b00, },
|
||||
{ IMX93_CLK_TPM1_GATE, "tpm1", "bus_aon_root", 0x8b00, },
|
||||
{ IMX93_CLK_TPM2_GATE, "tpm2", "tpm2_root", 0x8b40, },
|
||||
{ IMX93_CLK_TPM3_GATE, "tpm3", "tpm3_root", 0x8b80, },
|
||||
{ IMX93_CLK_TPM3_GATE, "tpm3", "bus_wakeup_root", 0x8b80, },
|
||||
{ IMX93_CLK_TPM4_GATE, "tpm4", "tpm4_root", 0x8bc0, },
|
||||
{ IMX93_CLK_TPM5_GATE, "tpm5", "tpm5_root", 0x8c00, },
|
||||
{ IMX93_CLK_TPM6_GATE, "tpm6", "tpm6_root", 0x8c40, },
|
||||
|
|
@ -240,9 +240,10 @@ static const struct imx93_clk_ccgr {
|
|||
{ IMX93_CLK_AUD_XCVR_GATE, "aud_xcvr", "audio_xcvr_root", 0x9b80, },
|
||||
{ IMX93_CLK_SPDIF_GATE, "spdif", "spdif_root", 0x9c00, },
|
||||
{ IMX93_CLK_HSIO_32K_GATE, "hsio_32k", "osc_32k", 0x9dc0, },
|
||||
{ IMX93_CLK_ENET1_GATE, "enet1", "enet_root", 0x9e00, },
|
||||
{ IMX93_CLK_ENET1_GATE, "enet1", "wakeup_axi_root", 0x9e00, },
|
||||
{ IMX93_CLK_ENET_QOS_GATE, "enet_qos", "wakeup_axi_root", 0x9e40, },
|
||||
{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, },
|
||||
/* Critical because clk accessed during CPU idle */
|
||||
{ IMX93_CLK_SYS_CNT_GATE, "sys_cnt", "osc_24m", 0x9e80, CLK_IS_CRITICAL},
|
||||
{ IMX93_CLK_TSTMR1_GATE, "tstmr1", "bus_aon_root", 0x9ec0, },
|
||||
{ IMX93_CLK_TSTMR2_GATE, "tstmr2", "bus_wakeup_root", 0x9f00, },
|
||||
{ IMX93_CLK_TMC_GATE, "tmc", "osc_24m", 0x9f40, },
|
||||
|
|
@ -258,7 +259,7 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
struct device_node *np = dev->of_node;
|
||||
const struct imx93_clk_root *root;
|
||||
const struct imx93_clk_ccgr *ccgr;
|
||||
void __iomem *base = NULL;
|
||||
void __iomem *base, *anatop_base;
|
||||
int i, ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
|
|
@ -270,9 +271,9 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
clks = clk_hw_data->hws;
|
||||
|
||||
clks[IMX93_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
|
||||
clks[IMX93_CLK_24M] = imx_obtain_fixed_clk_hw(np, "osc_24m");
|
||||
clks[IMX93_CLK_32K] = imx_obtain_fixed_clk_hw(np, "osc_32k");
|
||||
clks[IMX93_CLK_EXT1] = imx_obtain_fixed_clk_hw(np, "clk_ext1");
|
||||
clks[IMX93_CLK_24M] = imx_get_clk_hw_by_name(np, "osc_24m");
|
||||
clks[IMX93_CLK_32K] = imx_get_clk_hw_by_name(np, "osc_32k");
|
||||
clks[IMX93_CLK_EXT1] = imx_get_clk_hw_by_name(np, "clk_ext1");
|
||||
|
||||
clks[IMX93_CLK_SYS_PLL_PFD0] = imx_clk_hw_fixed("sys_pll_pfd0", 1000000000);
|
||||
clks[IMX93_CLK_SYS_PLL_PFD0_DIV2] = imx_clk_hw_fixed_factor("sys_pll_pfd0_div2",
|
||||
|
|
@ -285,20 +286,22 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
"sys_pll_pfd2", 1, 2);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx93-anatop");
|
||||
base = of_iomap(np, 0);
|
||||
anatop_base = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
if (WARN_ON(!base))
|
||||
if (WARN_ON(!anatop_base))
|
||||
return -ENOMEM;
|
||||
|
||||
clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", base + 0x1200,
|
||||
clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200,
|
||||
&imx_fracn_gppll);
|
||||
clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", base + 0x1400,
|
||||
clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400,
|
||||
&imx_fracn_gppll);
|
||||
|
||||
np = dev->of_node;
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (WARN_ON(IS_ERR(base)))
|
||||
if (WARN_ON(IS_ERR(base))) {
|
||||
iounmap(anatop_base);
|
||||
return PTR_ERR(base);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(root_array); i++) {
|
||||
root = &root_array[i];
|
||||
|
|
@ -327,6 +330,7 @@ static int imx93_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
unregister_hws:
|
||||
imx_unregister_hw_clocks(clks, IMX93_CLK_END);
|
||||
iounmap(anatop_base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
|
|||
clk_hw_data->num = IMXRT1050_CLK_END;
|
||||
hws = clk_hw_data->hws;
|
||||
|
||||
hws[IMXRT1050_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc");
|
||||
hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc");
|
||||
|
||||
anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
|
||||
pll_base = of_iomap(anp, 0);
|
||||
|
|
@ -140,7 +140,8 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2);
|
||||
hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4);
|
||||
hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24);
|
||||
hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10);
|
||||
hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28);
|
||||
hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif", ccm_base + 0x74, 10);
|
||||
hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6);
|
||||
hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7);
|
||||
imx_check_clk_hws(hws, IMXRT1050_CLK_END);
|
||||
|
|
|
|||
|
|
@ -54,7 +54,9 @@ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
|
|||
PLL_1416X_RATE(800000000U, 200, 3, 1),
|
||||
PLL_1416X_RATE(750000000U, 250, 2, 2),
|
||||
PLL_1416X_RATE(700000000U, 350, 3, 2),
|
||||
PLL_1416X_RATE(640000000U, 320, 3, 2),
|
||||
PLL_1416X_RATE(600000000U, 300, 3, 2),
|
||||
PLL_1416X_RATE(320000000U, 160, 3, 2),
|
||||
};
|
||||
|
||||
static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
|
||||
|
|
|
|||
|
|
@ -110,8 +110,7 @@ struct clk_hw *imx_obtain_fixed_clock_hw(
|
|||
return __clk_get_hw(clk);
|
||||
}
|
||||
|
||||
struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np,
|
||||
const char *name)
|
||||
struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
|
|
@ -121,7 +120,7 @@ struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np,
|
|||
|
||||
return __clk_get_hw(clk);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw);
|
||||
EXPORT_SYMBOL_GPL(imx_get_clk_hw_by_name);
|
||||
|
||||
/*
|
||||
* This fixups the register CCM_CSCMR1 write value.
|
||||
|
|
|
|||
|
|
@ -288,8 +288,7 @@ struct clk * imx_obtain_fixed_clock(
|
|||
struct clk_hw *imx_obtain_fixed_clock_hw(
|
||||
const char *name, unsigned long rate);
|
||||
|
||||
struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
|
||||
const char *name);
|
||||
struct clk_hw *imx_get_clk_hw_by_name(struct device_node *np, const char *name);
|
||||
|
||||
struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
|
||||
void __iomem *reg, u8 shift, u32 exclusive_mask);
|
||||
|
|
|
|||
|
|
@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740
|
|||
|
||||
If building for a JZ4740 SoC, you want to say Y here.
|
||||
|
||||
config INGENIC_CGU_JZ4755
|
||||
bool "Ingenic JZ4755 CGU driver"
|
||||
default MACH_JZ4755
|
||||
select INGENIC_CGU_COMMON
|
||||
help
|
||||
Support the clocks provided by the CGU hardware on Ingenic JZ4755
|
||||
and compatible SoCs.
|
||||
|
||||
If building for a JZ4755 SoC, you want to say Y here.
|
||||
|
||||
config INGENIC_CGU_JZ4725B
|
||||
bool "Ingenic JZ4725B CGU driver"
|
||||
default MACH_JZ4725B
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
|
||||
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
|
||||
struct ingenic_cgu *cgu = ingenic_clk->cgu;
|
||||
const struct ingenic_cgu_pll_info *pll_info;
|
||||
unsigned m, n, od_enc, od;
|
||||
unsigned m, n, od, od_enc = 0;
|
||||
bool bypass;
|
||||
u32 ctl;
|
||||
|
||||
|
|
@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
m += pll_info->m_offset;
|
||||
n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
|
||||
n += pll_info->n_offset;
|
||||
od_enc = ctl >> pll_info->od_shift;
|
||||
od_enc &= GENMASK(pll_info->od_bits - 1, 0);
|
||||
|
||||
if (pll_info->od_bits > 0) {
|
||||
od_enc = ctl >> pll_info->od_shift;
|
||||
od_enc &= GENMASK(pll_info->od_bits - 1, 0);
|
||||
}
|
||||
|
||||
if (pll_info->bypass_bit >= 0) {
|
||||
ctl = readl(cgu->base + pll_info->bypass_reg);
|
||||
|
|
@ -108,11 +111,15 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
return parent_rate;
|
||||
}
|
||||
|
||||
for (od = 0; od < pll_info->od_max; od++) {
|
||||
for (od = 0; od < pll_info->od_max; od++)
|
||||
if (pll_info->od_encoding[od] == od_enc)
|
||||
break;
|
||||
}
|
||||
BUG_ON(od == pll_info->od_max);
|
||||
|
||||
/* if od_max = 0, od_bits should be 0 and od is fixed to 1. */
|
||||
if (pll_info->od_max == 0)
|
||||
BUG_ON(pll_info->od_bits != 0);
|
||||
else
|
||||
BUG_ON(od == pll_info->od_max);
|
||||
od++;
|
||||
|
||||
return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
|
||||
|
|
@ -182,6 +189,9 @@ static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu,
|
|||
{
|
||||
u32 ctl;
|
||||
|
||||
if (pll_info->stable_bit < 0)
|
||||
return 0;
|
||||
|
||||
return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
|
||||
ctl & BIT(pll_info->stable_bit),
|
||||
0, 100 * USEC_PER_MSEC);
|
||||
|
|
@ -215,13 +225,18 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
|
|||
ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
|
||||
ctl |= (n - pll_info->n_offset) << pll_info->n_shift;
|
||||
|
||||
ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
|
||||
ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
|
||||
if (pll_info->od_bits > 0) {
|
||||
ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
|
||||
ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
|
||||
}
|
||||
|
||||
writel(ctl, cgu->base + pll_info->reg);
|
||||
|
||||
if (pll_info->set_rate_hook)
|
||||
pll_info->set_rate_hook(pll_info, rate, parent_rate);
|
||||
|
||||
/* If the PLL is enabled, verify that it's stable */
|
||||
if (ctl & BIT(pll_info->enable_bit))
|
||||
if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit)))
|
||||
ret = ingenic_pll_check_stable(cgu, pll_info);
|
||||
|
||||
spin_unlock_irqrestore(&cgu->lock, flags);
|
||||
|
|
@ -239,6 +254,9 @@ static int ingenic_pll_enable(struct clk_hw *hw)
|
|||
int ret;
|
||||
u32 ctl;
|
||||
|
||||
if (pll_info->enable_bit < 0)
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&cgu->lock, flags);
|
||||
if (pll_info->bypass_bit >= 0) {
|
||||
ctl = readl(cgu->base + pll_info->bypass_reg);
|
||||
|
|
@ -269,6 +287,9 @@ static void ingenic_pll_disable(struct clk_hw *hw)
|
|||
unsigned long flags;
|
||||
u32 ctl;
|
||||
|
||||
if (pll_info->enable_bit < 0)
|
||||
return;
|
||||
|
||||
spin_lock_irqsave(&cgu->lock, flags);
|
||||
ctl = readl(cgu->base + pll_info->reg);
|
||||
|
||||
|
|
@ -286,6 +307,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw)
|
|||
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
|
||||
u32 ctl;
|
||||
|
||||
if (pll_info->enable_bit < 0)
|
||||
return true;
|
||||
|
||||
ctl = readl(cgu->base + pll_info->reg);
|
||||
|
||||
return !!(ctl & BIT(pll_info->enable_bit));
|
||||
|
|
|
|||
|
|
@ -33,7 +33,8 @@
|
|||
* @od_shift: the number of bits to shift the post-VCO divider value by (ie.
|
||||
* the index of the lowest bit of the post-VCO divider value in
|
||||
* the PLL's control register)
|
||||
* @od_bits: the size of the post-VCO divider field in bits
|
||||
* @od_bits: the size of the post-VCO divider field in bits, or 0 if no
|
||||
* OD field exists (then the OD is fixed to 1)
|
||||
* @od_max: the maximum post-VCO divider value
|
||||
* @od_encoding: a pointer to an array mapping post-VCO divider values to
|
||||
* their encoded values in the PLL control register, or -1 for
|
||||
|
|
@ -41,8 +42,12 @@
|
|||
* @bypass_reg: the offset of the bypass control register within the CGU
|
||||
* @bypass_bit: the index of the bypass bit in the PLL control register, or
|
||||
* -1 if there is no bypass bit
|
||||
* @enable_bit: the index of the enable bit in the PLL control register
|
||||
* @stable_bit: the index of the stable bit in the PLL control register
|
||||
* @enable_bit: the index of the enable bit in the PLL control register, or
|
||||
* -1 if there is no enable bit (ie, the PLL is always on)
|
||||
* @stable_bit: the index of the stable bit in the PLL control register, or
|
||||
* -1 if there is no stable bit
|
||||
* @set_rate_hook: hook called immediately after updating the CGU register,
|
||||
* before releasing the spinlock
|
||||
*/
|
||||
struct ingenic_cgu_pll_info {
|
||||
unsigned reg;
|
||||
|
|
@ -53,11 +58,13 @@ struct ingenic_cgu_pll_info {
|
|||
u8 od_shift, od_bits, od_max;
|
||||
unsigned bypass_reg;
|
||||
s8 bypass_bit;
|
||||
u8 enable_bit;
|
||||
u8 stable_bit;
|
||||
s8 enable_bit;
|
||||
s8 stable_bit;
|
||||
void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
|
||||
unsigned long rate, unsigned long parent_rate,
|
||||
unsigned int *m, unsigned int *n, unsigned int *od);
|
||||
void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,
|
||||
unsigned long rate, unsigned long parent_rate);
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
|
|||
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Reference in New Issue