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arm64: dts: qcom: sc8180x: Add QUPs
This patch adds qup instances and i2c, spi, serial ports Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230530162454.51708-10-vkoul@kernel.org
This commit is contained in:
Vinod Koul
Bjorn Andersson
parent
d1d3ca0355
commit
0018761d15
1 changed files with 859 additions and 0 deletions
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@ -780,6 +780,865 @@ gcc: clock-controller@100000 {
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"sleep_clk";
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};
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qupv3_id_0: geniqup@8c0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0 0x008c0000 0 0x6000>;
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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clock-names = "m-ahb", "s-ahb";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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iommus = <&apps_smmu 0x4c3 0>;
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status = "disabled";
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i2c0: i2c@880000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00880000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@880000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00880000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart0: serial@880000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x00880000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c1: i2c@884000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00884000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@884000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00884000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart1: serial@884000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x00884000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c2: i2c@888000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00888000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@888000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00888000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart2: serial@888000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x00888000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c3: i2c@88c000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x0088c000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi3: spi@88c000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x0088c000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart3: serial@88c000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x0088c000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c4: i2c@890000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00890000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi4: spi@890000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00890000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart4: serial@890000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x00890000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c5: i2c@894000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00894000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi5: spi@894000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00894000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart5: serial@894000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x00894000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c6: i2c@898000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x00898000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi6: spi@898000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x00898000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart6: serial@898000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x00898000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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i2c7: i2c@89c000 {
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compatible = "qcom,geni-i2c";
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reg = <0 0x0089c000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi7: spi@89c000 {
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compatible = "qcom,geni-spi";
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reg = <0 0x0089c000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart7: serial@89c000 {
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compatible = "qcom,geni-uart";
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reg = <0 0x0089c000 0 0x4000>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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clock-names = "se";
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interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
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interconnect-names = "qup-core", "qup-config";
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status = "disabled";
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};
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};
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||||
|
||||
qupv3_id_1: geniqup@ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x00ac0000 0x0 0x6000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
iommus = <&apps_smmu 0x603 0>;
|
||||
status = "disabled";
|
||||
|
||||
i2c8: i2c@a80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a80000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi8: spi@a80000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a80000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart8: serial@a80000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00a80000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c9: i2c@a84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi9: spi@a84000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart9: serial@a84000 {
|
||||
compatible = "qcom,geni-debug-uart";
|
||||
reg = <0 0x00a84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c10: i2c@a88000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a88000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi10: spi@a88000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a88000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart10: serial@a88000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00a88000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c11: i2c@a8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi11: spi@a8c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart11: serial@a8c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00a8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c12: i2c@a90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a90000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi12: spi@a90000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a90000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart12: serial@a90000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00a90000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c16: i2c@a94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00a94000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
|
||||
<&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi16: spi@a94000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00a94000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart16: serial@a94000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00a94000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_2: geniqup@cc0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
reg = <0x0 0x00cc0000 0x0 0x6000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
|
||||
clock-names = "m-ahb", "s-ahb";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
iommus = <&apps_smmu 0x7a3 0>;
|
||||
status = "disabled";
|
||||
|
||||
i2c17: i2c@c80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c80000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi17: spi@c80000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00c80000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart17: serial@c80000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c80000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c18: i2c@c84000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi18: spi@c84000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00c84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart18: serial@c84000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c84000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c19: i2c@c88000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c88000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi19: spi@c88000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00c88000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart19: serial@c88000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c88000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c13: i2c@c8c000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi13: spi@c8c000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00c8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart13: serial@c8c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c8c000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c14: i2c@c90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c90000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi14: spi@c90000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00c90000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart14: serial@c90000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c90000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c15: i2c@c94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0 0x00c94000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
|
||||
<&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi15: spi@c94000 {
|
||||
compatible = "qcom,geni-spi";
|
||||
reg = <0 0x00c94000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart15: serial@c94000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0 0x00c94000 0 0x4000>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
|
||||
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
|
||||
interconnect-names = "qup-core", "qup-config";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
config_noc: interconnect@1500000 {
|
||||
compatible = "qcom,sc8180x-config-noc";
|
||||
reg = <0 0x01500000 0 0x7400>;
|
||||
|
|
|
|||
Loading…
Reference in a new issue