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PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT

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Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF
DT parser.

[bhelgaas: changelog]
Tested-by: James Morse <james.morse@arm.com>
Tested-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Tested-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
This commit is contained in:
Zhou Wang 2015-10-29 19:57:06 -05:00 committed by Bjorn Helgaas
parent 9cdce1cdc0
commit 0021d22b73
3 changed files with 53 additions and 60 deletions
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2
drivers/pci/host/pci-keystone-dw.c
View file

@ -322,7 +322,7 @@ static void ks_dw_pcie_clear_dbi_mode(void __iomem *reg_virt)
void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie)
{ {
struct pcie_port *pp = &ks_pcie->pp; struct pcie_port *pp = &ks_pcie->pp;
u32 start = pp->mem.start, end = pp->mem.end; u32 start = pp->mem->start, end = pp->mem->end;
int i, tr_size; int i, tr_size;
/* Disable BARs for inbound access */ /* Disable BARs for inbound access */

99
drivers/pci/host/pcie-designware.c
View file

@ -414,11 +414,11 @@ int dw_pcie_host_init(struct pcie_port *pp)
{ {
struct device_node *np = pp->dev->of_node; struct device_node *np = pp->dev->of_node;
struct platform_device *pdev = to_platform_device(pp->dev); struct platform_device *pdev = to_platform_device(pp->dev);
struct of_pci_range range;
struct of_pci_range_parser parser;
struct resource *cfg_res; struct resource *cfg_res;
u32 val; u32 val;
int i, ret; int i, ret;
LIST_HEAD(res);
struct resource_entry *win;
cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
if (cfg_res) { if (cfg_res) {
@ -430,65 +430,58 @@ int dw_pcie_host_init(struct pcie_port *pp)
dev_err(pp->dev, "missing *config* reg space\n"); dev_err(pp->dev, "missing *config* reg space\n");
} }
if (of_pci_range_parser_init(&parser, np)) { ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
dev_err(pp->dev, "missing ranges property\n"); if (ret)
return -EINVAL; return ret;
}
/* Get the I/O and memory ranges from DT */ /* Get the I/O and memory ranges from DT */
for_each_of_pci_range(&parser, &range) { resource_list_for_each_entry(win, &res) {
unsigned long restype = range.flags & IORESOURCE_TYPE_BITS; switch (resource_type(win->res)) {
case IORESOURCE_IO:
if (restype == IORESOURCE_IO) { pp->io = win->res;
of_pci_range_to_resource(&range, np, &pp->io); pp->io->name = "I/O";
pp->io.name = "I/O"; pp->io_size = resource_size(pp->io);
pp->io.start = max_t(resource_size_t, pp->io_bus_addr = pp->io->start - win->offset;
PCIBIOS_MIN_IO, pp->io->start = max_t(resource_size_t, PCIBIOS_MIN_IO,
range.pci_addr + global_io_offset); pp->io_bus_addr +
pp->io.end = min_t(resource_size_t, global_io_offset);
IO_SPACE_LIMIT, pp->io->end = min_t(resource_size_t, IO_SPACE_LIMIT,
range.pci_addr + range.size pp->io_bus_addr + pp->io_size +
+ global_io_offset - 1); global_io_offset - 1);
pp->io_size = resource_size(&pp->io); pp->io_base = pp->io->start;
pp->io_bus_addr = range.pci_addr; pp->io_base_tmp = pp->io->start;
pp->io_base = range.cpu_addr; break;
pp->io_base_tmp = range.cpu_addr; case IORESOURCE_MEM:
pp->mem = win->res;
pp->mem->name = "MEM";
pp->mem_size = resource_size(pp->mem);
pp->mem_bus_addr = pp->mem->start - win->offset;
break;
case 0:
pp->cfg = win->res;
pp->cfg0_size = resource_size(pp->cfg)/2;
pp->cfg1_size = resource_size(pp->cfg)/2;
pp->cfg0_base = pp->cfg->start;
pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
break;
case IORESOURCE_BUS:
pp->busn = win->res;
break;
default:
continue;
} }
if (restype == IORESOURCE_MEM) {
of_pci_range_to_resource(&range, np, &pp->mem);
pp->mem.name = "MEM";
pp->mem_size = resource_size(&pp->mem);
pp->mem_bus_addr = range.pci_addr;
}
if (restype == 0) {
of_pci_range_to_resource(&range, np, &pp->cfg);
pp->cfg0_size = resource_size(&pp->cfg)/2;
pp->cfg1_size = resource_size(&pp->cfg)/2;
pp->cfg0_base = pp->cfg.start;
pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
}
}
ret = of_pci_parse_bus_range(np, &pp->busn);
if (ret < 0) {
pp->busn.name = np->name;
pp->busn.start = 0;
pp->busn.end = 0xff;
pp->busn.flags = IORESOURCE_BUS;
dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
ret, &pp->busn);
} }
if (!pp->dbi_base) { if (!pp->dbi_base) {
pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start, pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start,
resource_size(&pp->cfg)); resource_size(pp->cfg));
if (!pp->dbi_base) { if (!pp->dbi_base) {
dev_err(pp->dev, "error with ioremap\n"); dev_err(pp->dev, "error with ioremap\n");
return -ENOMEM; return -ENOMEM;
} }
} }
pp->mem_base = pp->mem.start; pp->mem_base = pp->mem->start;
if (!pp->va_cfg0_base) { if (!pp->va_cfg0_base) {
pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@ -712,13 +705,13 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
sys->io_offset = global_io_offset - pp->io_bus_addr; sys->io_offset = global_io_offset - pp->io_bus_addr;
pci_ioremap_io(global_io_offset, pp->io_base_tmp); pci_ioremap_io(global_io_offset, pp->io_base_tmp);
global_io_offset += SZ_64K; global_io_offset += SZ_64K;
pci_add_resource_offset(&sys->resources, &pp->io, pci_add_resource_offset(&sys->resources, pp->io,
sys->io_offset); sys->io_offset);
} }
sys->mem_offset = pp->mem.start - pp->mem_bus_addr; sys->mem_offset = pp->mem->start - pp->mem_bus_addr;
pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, pp->mem, sys->mem_offset);
pci_add_resource(&sys->resources, &pp->busn); pci_add_resource(&sys->resources, pp->busn);
return 1; return 1;
} }

12
drivers/pci/host/pcie-designware.h
View file

@ -32,17 +32,17 @@ struct pcie_port {
u64 cfg1_base; u64 cfg1_base;
void __iomem *va_cfg1_base; void __iomem *va_cfg1_base;
u32 cfg1_size; u32 cfg1_size;
u64 io_base; resource_size_t io_base;
u64 io_base_tmp; resource_size_t io_base_tmp;
phys_addr_t io_bus_addr; phys_addr_t io_bus_addr;
u32 io_size; u32 io_size;
u64 mem_base; u64 mem_base;
phys_addr_t mem_bus_addr; phys_addr_t mem_bus_addr;
u32 mem_size; u32 mem_size;
struct resource cfg; struct resource *cfg;
struct resource io; struct resource *io;
struct resource mem; struct resource *mem;
struct resource busn; struct resource *busn;
int irq; int irq;
u32 lanes; u32 lanes;
struct pcie_host_ops *ops; struct pcie_host_ops *ops;