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clk: meson: meson8b: add the fractional divider for vid_pll_dco
This "vid_pll_dco" (which should be named HDMI_PLL or - as the datasheet calls it - HPLL) has a 12-bit wide fractional parameter at HHI_VID_PLL_CNTL2[11:0]. Add this so we correctly calculate the rate of this PLL when u-boot is configured for a video mode which uses this fractional parameter. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20181202214220.7715-3-martin.blumenstingl@googlemail.com
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2 changed files with 6 additions and 0 deletions
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@ -137,6 +137,11 @@ static struct clk_regmap meson8b_vid_pll_dco = {
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.shift = 10,
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.shift = 10,
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.width = 5,
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.width = 5,
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},
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},
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.frac = {
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.reg_off = HHI_VID_PLL_CNTL2,
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.shift = 0,
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.width = 12,
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},
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.l = {
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.l = {
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.reg_off = HHI_VID_PLL_CNTL,
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.reg_off = HHI_VID_PLL_CNTL,
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.shift = 31,
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.shift = 31,
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@ -33,6 +33,7 @@
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
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/*
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/*
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* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
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* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
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