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iio: adc: ad7766: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Update the comment to reflect the fact DMA safety 'may' require
separate cachelines.
Fixes: aa16c6bd0e
("iio:adc: Add support for AD7766/AD7767")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-16-jic23@kernel.org
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1 changed files with 2 additions and 3 deletions
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@ -45,13 +45,12 @@ struct ad7766 {
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struct spi_message msg;
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struct spi_message msg;
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/*
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/*
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* DMA (thus cache coherency maintenance) requires the
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* DMA (thus cache coherency maintenance) may require the
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* transfer buffers to live in their own cache lines.
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* transfer buffers to live in their own cache lines.
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* Make the buffer large enough for one 24 bit sample and one 64 bit
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* Make the buffer large enough for one 24 bit sample and one 64 bit
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* aligned 64 bit timestamp.
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* aligned 64 bit timestamp.
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*/
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*/
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unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)]
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unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)] __aligned(IIO_DMA_MINALIGN);
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____cacheline_aligned;
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};
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};
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/*
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/*
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