Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2023-12-12 (igb, e1000e)

This series contains updates to igb and e1000e drivers.

Ilpo Järvinen does some cleanups to both drivers: utilizing FIELD_GET()
helpers and using standard kernel defines over driver created ones.

* '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  e1000e: Use pcie_capability_read_word() for reading LNKSTA
  e1000e: Use PCI_EXP_LNKSTA_NLW & FIELD_GET() instead of custom defines/code
  igb: Use FIELD_GET() to extract Link Width
====================

Link: https://lore.kernel.org/r/20231212204947.513563-1-anthony.l.nguyen@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2023-12-13 22:08:58 -08:00
commit 00b1b2296b
3 changed files with 11 additions and 16 deletions

View file

@ -678,11 +678,8 @@
/* PCI/PCI-X/PCI-EX Config space */
#define PCI_HEADER_TYPE_REGISTER 0x0E
#define PCIE_LINK_STATUS 0x12
#define PCI_HEADER_TYPE_MULTIFUNC 0x80
#define PCIE_LINK_WIDTH_MASK 0x3F0
#define PCIE_LINK_WIDTH_SHIFT 4
#define PHY_REVISION_MASK 0xFFFFFFF0
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */

View file

@ -1,6 +1,8 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 1999 - 2018 Intel Corporation. */
#include <linux/bitfield.h>
#include "e1000.h"
/**
@ -13,21 +15,17 @@
**/
s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw)
{
struct pci_dev *pdev = hw->adapter->pdev;
struct e1000_mac_info *mac = &hw->mac;
struct e1000_bus_info *bus = &hw->bus;
struct e1000_adapter *adapter = hw->adapter;
u16 pcie_link_status, cap_offset;
u16 pcie_link_status;
cap_offset = adapter->pdev->pcie_cap;
if (!cap_offset) {
if (!pci_pcie_cap(pdev)) {
bus->width = e1000_bus_width_unknown;
} else {
pci_read_config_word(adapter->pdev,
cap_offset + PCIE_LINK_STATUS,
&pcie_link_status);
bus->width = (enum e1000_bus_width)((pcie_link_status &
PCIE_LINK_WIDTH_MASK) >>
PCIE_LINK_WIDTH_SHIFT);
pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &pcie_link_status);
bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW,
pcie_link_status);
}
mac->ops.set_lan_id(hw);

View file

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2007 - 2018 Intel Corporation. */
#include <linux/bitfield.h>
#include <linux/if_ether.h>
#include <linux/delay.h>
#include <linux/pci.h>
@ -50,9 +51,8 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
break;
}
bus->width = (enum e1000_bus_width)((pcie_link_status &
PCI_EXP_LNKSTA_NLW) >>
PCI_EXP_LNKSTA_NLW_SHIFT);
bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW,
pcie_link_status);
}
reg = rd32(E1000_STATUS);