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iio: dac: ad5504: Fix alignment for DMA safety 

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 0dbe59c7a7 ("iio:ad5504: Do not store transfer buffers on the stack")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-48-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:27 +01:00
parent 678d536bb4
commit 00b9737caa
1 changed files with 1 additions and 1 deletions
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drivers/iio/dac/ad5504.c
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@ -54,7 +54,7 @@ struct ad5504_state {
unsigned pwr_down_mask;
unsigned pwr_down_mode;
__be16 data[2] ____cacheline_aligned;
__be16 data[2] __aligned(IIO_DMA_MINALIGN);
};
/*