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sata_mv rearrange mv_config_fbs
Rearrange mv_config_fbs() to more closely follow the (corrected) datasheet recommendations for NCQ and FIS-based switching (FBS). Also, maintain a port flag to let us know when FBS is enabled. We will make more use of that flag later in this patch series. Signed-off-by: Mark Lord <mlord@pobox.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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1 changed files with 39 additions and 21 deletions
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@ -366,6 +366,7 @@ enum {
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/* Port private flags (pp_flags) */
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MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
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MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
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MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
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};
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#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
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@ -1129,26 +1130,31 @@ static int mv_qc_defer(struct ata_queued_cmd *qc)
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return ATA_DEFER_PORT;
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}
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static void mv_config_fbs(void __iomem *port_mmio, int enable_fbs)
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static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
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{
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u32 old_fiscfg, new_fiscfg, old_ltmode, new_ltmode;
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/*
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* Various bit settings required for operation
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* in FIS-based switching (fbs) mode on GenIIe:
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*/
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old_fiscfg = readl(port_mmio + FISCFG_OFS);
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old_ltmode = readl(port_mmio + LTMODE_OFS);
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if (enable_fbs) {
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new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
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new_ltmode = old_ltmode | LTMODE_BIT8;
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} else { /* disable fbs */
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new_fiscfg = old_fiscfg & ~FISCFG_SINGLE_SYNC;
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new_ltmode = old_ltmode & ~LTMODE_BIT8;
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u32 new_fiscfg, old_fiscfg;
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u32 new_ltmode, old_ltmode;
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u32 new_haltcond, old_haltcond;
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old_fiscfg = readl(port_mmio + FISCFG_OFS);
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old_ltmode = readl(port_mmio + LTMODE_OFS);
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old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
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new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
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new_ltmode = old_ltmode & ~LTMODE_BIT8;
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new_haltcond = old_haltcond | EDMA_ERR_DEV;
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if (want_fbs) {
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new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
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new_ltmode = old_ltmode | LTMODE_BIT8;
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}
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if (new_fiscfg != old_fiscfg)
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writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
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if (new_ltmode != old_ltmode)
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writelfl(new_ltmode, port_mmio + LTMODE_OFS);
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if (new_haltcond != old_haltcond)
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writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
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}
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static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
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@ -1175,6 +1181,7 @@ static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
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/* set up non-NCQ EDMA configuration */
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cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
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pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
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if (IS_GEN_I(hpriv))
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cfg |= (1 << 8); /* enab config burst size mask */
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@ -1184,19 +1191,30 @@ static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
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mv_60x1_errata_sata25(ap, want_ncq);
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} else if (IS_GEN_IIE(hpriv)) {
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int want_fbs = sata_pmp_attached(ap);
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/*
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* Possible future enhancement:
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*
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* The chip can use FBS with non-NCQ, if we allow it,
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* But first we need to have the error handling in place
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* for this mode (datasheet section 7.3.15.4.2.3).
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* So disallow non-NCQ FBS for now.
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*/
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want_fbs &= want_ncq;
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mv_config_fbs(port_mmio, want_ncq, want_fbs);
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if (want_fbs) {
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pp->pp_flags |= MV_PP_FLAG_FBS_EN;
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cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
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}
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cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
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cfg |= (1 << 22); /* enab 4-entry host queue cache */
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if (HAS_PCI(ap->host))
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cfg |= (1 << 18); /* enab early completion */
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if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
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cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
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if (want_ncq && sata_pmp_attached(ap)) {
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cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
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mv_config_fbs(port_mmio, 1);
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} else {
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mv_config_fbs(port_mmio, 0);
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}
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}
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if (want_ncq) {
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