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ARM: mx5: use generic irq chip pm interface for pm functions on
Two problems exist in the current i.MX5 pm suspend/resume and idle functions. The first is the current i.MX5 suspend routine will call tzic_enable_wake(1) to set wake source, this will set all enabled irq as wake source rather than those wake capable. The second is i.MX5 idle will call mx5_cpu_lp_set() to prepare enter low power mode, but it forgets to call wfi instruction to enter this mode. To fix these two problems, using generic irq chip pm interface and modify function imx5_idle(). [Tested by Shawn Guo on imx51 babbage board. Tested by Hui Wang on imx51 pdk board.] Signed-off-by: Hui Wang <jason77.wang@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
parent
5f0a6e2d50
commit
010dc8af8f
4 changed files with 48 additions and 16 deletions
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@ -13,6 +13,7 @@
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <asm/mach/map.h>
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@ -21,10 +22,26 @@
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#include <mach/devices-common.h>
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#include <mach/iomux-v3.h>
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static struct clk *gpc_dvfs_clk;
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static void imx5_idle(void)
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{
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if (!need_resched())
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if (!need_resched()) {
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/* gpc clock is needed for SRPG */
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if (gpc_dvfs_clk == NULL) {
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gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
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if (IS_ERR(gpc_dvfs_clk))
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goto err0;
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}
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clk_enable(gpc_dvfs_clk);
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mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
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if (tzic_enable_wake())
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goto err1;
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cpu_do_idle();
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err1:
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clk_disable(gpc_dvfs_clk);
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}
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err0:
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local_irq_enable();
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}
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@ -55,9 +55,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
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stop_mode = 1;
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}
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arm_srpgcr |= MXC_SRPGCR_PCR;
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if (tzic_enable_wake(1) != 0)
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return;
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break;
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case STOP_POWER_ON:
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ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
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@ -168,7 +168,7 @@ struct cpu_op {
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u32 cpu_rate;
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};
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int tzic_enable_wake(int is_idle);
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int tzic_enable_wake(void);
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extern struct cpu_op *(*get_cpu_op)(int *op);
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#endif
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@ -73,7 +73,28 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
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#define tzic_set_irq_fiq NULL
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#endif
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static unsigned int *wakeup_intr[4];
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#ifdef CONFIG_PM
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static void tzic_irq_suspend(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int idx = gc->irq_base >> 5;
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__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
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}
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static void tzic_irq_resume(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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int idx = gc->irq_base >> 5;
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__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
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tzic_base + TZIC_WAKEUP0(idx));
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}
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#else
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#define tzic_irq_suspend NULL
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#define tzic_irq_resume NULL
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#endif
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static struct mxc_extra_irq tzic_extra_irq = {
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#ifdef CONFIG_FIQ
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@ -91,12 +112,13 @@ static __init void tzic_init_gc(unsigned int irq_start)
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handle_level_irq);
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gc->private = &tzic_extra_irq;
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gc->wake_enabled = IRQ_MSK(32);
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wakeup_intr[idx] = &gc->wake_active;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_disable_reg;
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ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
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ct->chip.irq_set_wake = irq_gc_set_wake;
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ct->chip.irq_suspend = tzic_irq_suspend;
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ct->chip.irq_resume = tzic_irq_resume;
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ct->regs.disable = TZIC_ENCLEAR0(idx);
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ct->regs.enable = TZIC_ENSET0(idx);
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@ -167,23 +189,19 @@ void __init tzic_init_irq(void __iomem *irqbase)
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/**
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* tzic_enable_wake() - enable wakeup interrupt
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*
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* @param is_idle 1 if called in idle loop (ENSET0 register);
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* 0 to be used when called from low power entry
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* @return 0 if successful; non-zero otherwise
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*/
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int tzic_enable_wake(int is_idle)
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int tzic_enable_wake(void)
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{
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unsigned int i, v;
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unsigned int i;
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__raw_writel(1, tzic_base + TZIC_DSMINT);
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if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
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return -EAGAIN;
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for (i = 0; i < 4; i++) {
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v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
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*wakeup_intr[i];
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__raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
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}
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for (i = 0; i < 4; i++)
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__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)),
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tzic_base + TZIC_WAKEUP0(i));
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return 0;
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}
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