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drm/amdgpu: support nbio_7_2_1 for yellow carp
This patch adds nbio_7_2_1 support yellow carp. Signed-off-by: Aaron Liu <aaron.liu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
bf9d4e88c2
commit
011b514fd8
1 changed files with 103 additions and 37 deletions
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@ -28,6 +28,25 @@
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#include "nbio/nbio_7_2_0_sh_mask.h"
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#include <uapi/linux/kfd_ioctl.h>
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#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC 0x0015
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#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC_BASE_IDX 2
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#define regBIF_BX0_BIF_FB_EN_YC 0x0100
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#define regBIF_BX0_BIF_FB_EN_YC_BASE_IDX 2
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#define regBIF1_PCIE_MST_CTRL_3 0x4601c6
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#define regBIF1_PCIE_MST_CTRL_3_BASE_IDX 5
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE__SHIFT \
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0x1b
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV__SHIFT \
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0x1c
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_MODE_MASK \
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0x08000000L
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#define BIF1_PCIE_MST_CTRL_3__CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV_MASK \
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0x30000000L
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#define regBIF1_PCIE_TX_POWER_CTRL_1 0x460187
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#define regBIF1_PCIE_TX_POWER_CTRL_1_BASE_IDX 5
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#define BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK 0x00000001L
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#define BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK 0x00000008L
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static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
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{
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WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
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@ -38,7 +57,12 @@ static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
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static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
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u32 tmp;
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if (adev->asic_type == CHIP_YELLOW_CARP)
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tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
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else
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tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
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tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
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tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
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@ -49,11 +73,19 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
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static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
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{
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if (enable)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
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BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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if (adev->asic_type == CHIP_YELLOW_CARP)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
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BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
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BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
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BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
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if (adev->asic_type == CHIP_YELLOW_CARP)
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
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else
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WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
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}
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static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
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@ -92,13 +124,13 @@ static void nbio_v7_2_vcn_doorbell_range(struct amdgpu_device *adev, bool use_do
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if (use_doorbell) {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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GDC0_BIF_VCN0_DOORBELL_RANGE, OFFSET,
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doorbell_index);
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
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GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 8);
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} else {
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doorbell_range = REG_SET_FIELD(doorbell_range,
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GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
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GDC0_BIF_VCN0_DOORBELL_RANGE, SIZE, 0);
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}
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WREG32_PCIE_PORT(reg, doorbell_range);
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@ -123,22 +155,22 @@ static void nbio_v7_2_enable_doorbell_selfring_aperture(struct amdgpu_device *ad
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if (enable) {
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tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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DOORBELL_SELFRING_GPA_APER_EN, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_MODE, 1) |
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REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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DOORBELL_SELFRING_GPA_APER_SIZE, 0);
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WREG32_SOC15(NBIO, 0,
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regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
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lower_32_bits(adev->doorbell.base));
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WREG32_SOC15(NBIO, 0,
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regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
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upper_32_bits(adev->doorbell.base));
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}
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WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
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tmp);
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tmp);
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}
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@ -218,19 +250,42 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
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{
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uint32_t def, data;
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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} else {
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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}
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if (adev->asic_type == CHIP_YELLOW_CARP) {
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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else
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data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
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data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
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def = data;
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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else
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data &= ~(BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
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BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
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data);
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} else {
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
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if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
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data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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else
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data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
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PCIE_CNTL2__MST_MEM_LS_EN_MASK |
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PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
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}
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}
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static void nbio_v7_2_get_clockgating_state(struct amdgpu_device *adev,
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@ -297,14 +352,25 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
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static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
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{
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uint32_t def, data;
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if (adev->asic_type == CHIP_YELLOW_CARP) {
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
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data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
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CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
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data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
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CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
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data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
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data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
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} else {
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def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
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data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
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CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
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data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
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CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL),
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data);
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if (def != data)
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WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
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}
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}
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const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
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