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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 09:19:51 +00:00
[PATCH] nvidiafb: Fixes for new G5
Recent X "nv" driver was fixed for various issues with modern 6xxx and 7xxx cards. This patch ports those fixes to nvidiafb. This makes it work fine on the 6600 bundled with the newest G5 macs. I've verified it still works on the 5200FX of the iMacG5. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: "Antonino A. Daplas" <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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parent
2308acca65
commit
0137ecfdc3
3 changed files with 75 additions and 18 deletions
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@ -848,7 +848,7 @@ void NVCalcStateExt(struct nvidia_par *par,
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int width,
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int hDisplaySize, int height, int dotClock, int flags)
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{
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int pixelDepth, VClk;
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int pixelDepth, VClk = 0;
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/*
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* Save mode parameters.
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*/
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@ -938,15 +938,24 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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if (par->Architecture == NV_ARCH_04) {
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NV_WR32(par->PFB, 0x0200, state->config);
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} else if ((par->Chipset & 0xfff0) == 0x0090) {
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for (i = 0; i < 15; i++) {
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NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
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NV_WR32(par->PFB, 0x0604 + (i * 0x10), par->FbMapSize - 1);
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}
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} else {
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} else if ((par->Architecture < NV_ARCH_40) ||
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(par->Chipset & 0xfff0) == 0x0040) {
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for (i = 0; i < 8; i++) {
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NV_WR32(par->PFB, 0x0240 + (i * 0x10), 0);
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NV_WR32(par->PFB, 0x0244 + (i * 0x10), par->FbMapSize - 1);
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NV_WR32(par->PFB, 0x0244 + (i * 0x10),
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par->FbMapSize - 1);
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}
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} else {
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int regions = 12;
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if (((par->Chipset & 0xfff0) == 0x0090) ||
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((par->Chipset & 0xfff0) == 0x01D0) ||
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((par->Chipset & 0xfff0) == 0x0290))
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regions = 15;
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for(i = 0; i < regions; i++) {
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NV_WR32(par->PFB, 0x0600 + (i * 0x10), 0);
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NV_WR32(par->PFB, 0x0604 + (i * 0x10),
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par->FbMapSize - 1);
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}
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}
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@ -1182,11 +1191,17 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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NV_WR32(par->PGRAPH, 0x0608, 0xFFFFFFFF);
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} else {
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if (par->Architecture >= NV_ARCH_40) {
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u32 tmp;
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NV_WR32(par->PGRAPH, 0x0084, 0x401287c0);
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NV_WR32(par->PGRAPH, 0x008C, 0x60de8051);
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NV_WR32(par->PGRAPH, 0x0090, 0x00008000);
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NV_WR32(par->PGRAPH, 0x0610, 0x00be3c5f);
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tmp = NV_RD32(par->REGS, 0x1540) & 0xff;
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for(i = 0; tmp && !(tmp & 1); tmp >>= 1, i++);
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NV_WR32(par->PGRAPH, 0x5000, i);
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if ((par->Chipset & 0xfff0) == 0x0040) {
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NV_WR32(par->PGRAPH, 0x09b0,
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0x83280fff);
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@ -1211,6 +1226,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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0xffff7fff);
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break;
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case 0x00C0:
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case 0x0120:
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NV_WR32(par->PGRAPH, 0x0828,
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0x007596ff);
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NV_WR32(par->PGRAPH, 0x082C,
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@ -1245,6 +1261,7 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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0x00100000);
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break;
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case 0x0090:
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case 0x0290:
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NV_WR32(par->PRAMDAC, 0x0608,
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NV_RD32(par->PRAMDAC, 0x0608) |
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0x00100000);
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@ -1310,14 +1327,44 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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}
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}
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if ((par->Chipset & 0xfff0) == 0x0090) {
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for (i = 0; i < 60; i++)
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NV_WR32(par->PGRAPH, 0x0D00 + i,
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NV_RD32(par->PFB, 0x0600 + i));
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if ((par->Architecture < NV_ARCH_40) ||
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((par->Chipset & 0xfff0) == 0x0040)) {
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for (i = 0; i < 32; i++) {
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NV_WR32(par->PGRAPH, 0x0900 + i*4,
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NV_RD32(par->PFB, 0x0240 +i*4));
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NV_WR32(par->PGRAPH, 0x6900 + i*4,
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NV_RD32(par->PFB, 0x0240 +i*4));
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}
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} else {
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for (i = 0; i < 32; i++)
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NV_WR32(par->PGRAPH, 0x0900 + i,
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NV_RD32(par->PFB, 0x0240 + i));
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if (((par->Chipset & 0xfff0) == 0x0090) ||
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((par->Chipset & 0xfff0) == 0x01D0) ||
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((par->Chipset & 0xfff0) == 0x0290)) {
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for (i = 0; i < 60; i++) {
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NV_WR32(par->PGRAPH,
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0x0D00 + i*4,
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NV_RD32(par->PFB,
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0x0600 + i*4));
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NV_WR32(par->PGRAPH,
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0x6900 + i*4,
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NV_RD32(par->PFB,
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0x0600 + i*4));
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}
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} else {
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for (i = 0; i < 48; i++) {
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NV_WR32(par->PGRAPH,
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0x0900 + i*4,
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NV_RD32(par->PFB,
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0x0600 + i*4));
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if(((par->Chipset & 0xfff0)
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!= 0x0160) &&
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((par->Chipset & 0xfff0)
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!= 0x0220))
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NV_WR32(par->PGRAPH,
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0x6900 + i*4,
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NV_RD32(par->PFB,
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0x0600 + i*4));
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}
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}
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}
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if (par->Architecture >= NV_ARCH_40) {
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@ -1338,7 +1385,9 @@ void NVLoadStateExt(struct nvidia_par *par, RIVA_HW_STATE * state)
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NV_WR32(par->PGRAPH, 0x0868,
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par->FbMapSize - 1);
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} else {
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if((par->Chipset & 0xfff0) == 0x0090) {
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if ((par->Chipset & 0xfff0) == 0x0090 ||
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(par->Chipset & 0xfff0) == 0x01D0 ||
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(par->Chipset & 0xfff0) == 0x0290) {
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NV_WR32(par->PGRAPH, 0x0DF0,
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NV_RD32(par->PFB, 0x0200));
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NV_WR32(par->PGRAPH, 0x0DF4,
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@ -285,7 +285,6 @@ static void nv10GetConfig(struct nvidia_par *par)
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par->CrystalFreqKHz = 27000;
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}
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par->CursorStart = (par->RamAmountKBytes - 96) * 1024;
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par->CURSOR = NULL; /* can't set this here */
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par->MinVClockFreqKHz = 12000;
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par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
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@ -382,6 +381,8 @@ void NVCommonSetup(struct fb_info *info)
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case 0x0146:
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case 0x0147:
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case 0x0148:
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case 0x0098:
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case 0x0099:
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mobile = 1;
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break;
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default:
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@ -1485,6 +1485,8 @@ static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
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case 0x0210:
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case 0x0220:
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case 0x0230:
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case 0x0290:
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case 0x0390:
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arch = NV_ARCH_40;
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break;
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case 0x0020: /* TNT, TNT2 */
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@ -1581,10 +1583,15 @@ static int __devinit nvidiafb_probe(struct pci_dev *pd,
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if (par->FbMapSize > 64 * 1024 * 1024)
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par->FbMapSize = 64 * 1024 * 1024;
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par->FbUsableSize = par->FbMapSize - (128 * 1024);
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if(par->Architecture >= NV_ARCH_40)
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par->FbUsableSize = par->FbMapSize - (560 * 1024);
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else
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par->FbUsableSize = par->FbMapSize - (128 * 1024);
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par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
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16 * 1024;
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par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
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par->CursorStart = par->FbUsableSize + (32 * 1024);
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info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
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info->screen_size = par->FbUsableSize;
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nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024;
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