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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Mediatek DRM Next for Linux 6.9
1. Add display driver for MT8188 VDOSYS1 2. DSI driver cleanups 3. Filter modes according to hardware capability 4. Fix a null pointer crash in mtk_drm_crtc_finish_page_flip -----BEGIN PGP SIGNATURE----- iQJMBAABCgA2FiEEACwLKSDmq+9RDv5P4cpzo8lZTiQFAmXgrhsYHGNodW5rdWFu Zy5odUBrZXJuZWwub3JnAAoJEOHKc6PJWU4kiR0P/1AqLdIf5HOpSRJSI45iiGc1 Y7LKpCshf7OQG5WlIAK417Fv6Rq0oLNrUZe0KLtIzRtTazdhJOyi8wdsRaGdpqop abPkHhBpEIX37raEXeZjjYtU06QPfK1do512nrXK30SdDqb33jiNEvbzaLQamMrQ +gUASajPf+RqRKuuUZIDOGQA1/tWS8sVWTxcriwBhFu5QPY+kfImF0E1ivsfOIiC l6LEGhXD1mMfwQ3Q6O80/Yeqxng4V6KOkTHvfNGvvCQVIvC5IxW0yrve2UvM56Hb rgZ0j4ztk/tnjNUHIUOq8Pb+9Hg7LrrLRcF8bMbN/l7Agna9FqW2LiTA5KVoAWjE ISqcuZ1y3aVNDMN0l+g3vKHW8qMxIHqb8+rCxh7nRxGjTRkkDkHruMi11p8F/2vG 7pL9x6sdgXG+Ea482UubpscjeymZiZzoJL+PpbqoRJUUknfXEbAHfyedH5YIi1QK bJk/1Ri/08hsfesXdKuH5Yk0JTb8eZKByt/CUHcLMBlmXtscTTgPiCY4rLsubr7a JLT2T04VqsD5JUbwn0PRVz2/ckjF1vNP+BgGUxy5tWuv5ecJGNU76L5gXgzPh3ke k0R2W9UUJlZodDBX6rGYkJJrYhdjQ9GE2TG6lkjyyTT7NdEY8ja53GVQ9289HPde Y1syVXkG7JeLq+07tRiM =gaet -----END PGP SIGNATURE----- Merge tag 'mediatek-drm-next-6.9' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next Mediatek DRM Next for Linux 6.9 1. Add display driver for MT8188 VDOSYS1 2. DSI driver cleanups 3. Filter modes according to hardware capability 4. Fix a null pointer crash in mtk_drm_crtc_finish_page_flip Signed-off-by: Dave Airlie <airlied@redhat.com> From: Chun-Kuang Hu <chunkuang.hu@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20240229162143.28957-1-chunkuang.hu@kernel.org
This commit is contained in:
Dave Airlie
commit
017da39e9c
8 changed files with 281 additions and 193 deletions
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@ -73,6 +73,8 @@ void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int
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struct cmdq_pkt *cmdq_pkt);
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void mtk_merge_start_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
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void mtk_merge_stop_cmdq(struct device *dev, struct cmdq_pkt *cmdq_pkt);
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enum drm_mode_status mtk_merge_mode_valid(struct device *dev,
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const struct drm_display_mode *mode);
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void mtk_ovl_bgclr_in_on(struct device *dev);
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void mtk_ovl_bgclr_in_off(struct device *dev);
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@ -131,6 +133,8 @@ unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);
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struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev);
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const u32 *mtk_ovl_adaptor_get_formats(struct device *dev);
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size_t mtk_ovl_adaptor_get_num_formats(struct device *dev);
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enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
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const struct drm_display_mode *mode);
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void mtk_rdma_bypass_shadow(struct device *dev);
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int mtk_rdma_clk_enable(struct device *dev);
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@ -222,6 +222,71 @@ void mtk_merge_clk_disable(struct device *dev)
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clk_disable_unprepare(priv->clk);
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}
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enum drm_mode_status mtk_merge_mode_valid(struct device *dev,
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const struct drm_display_mode *mode)
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{
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struct mtk_disp_merge *priv = dev_get_drvdata(dev);
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unsigned long rate;
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rate = clk_get_rate(priv->clk);
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/* Convert to KHz and round the number */
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rate = (rate + 500) / 1000;
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if (rate && mode->clock > rate) {
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dev_dbg(dev, "invalid clock: %d (>%lu)\n", mode->clock, rate);
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return MODE_CLOCK_HIGH;
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}
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/*
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* Measure the bandwidth requirement of hardware prefetch (per frame)
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*
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* let N = prefetch buffer size in lines
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* (ex. N=3, then prefetch buffer size = 3 lines)
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*
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* prefetch size = htotal * N (pixels)
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* time per line = 1 / fps / vtotal (seconds)
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* duration = vbp * time per line
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* = vbp / fps / vtotal
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*
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* data rate = prefetch size / duration
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* = htotal * N / (vbp / fps / vtotal)
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* = htotal * vtotal * fps * N / vbp
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* = clk * N / vbp (pixels per second)
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*
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* Say 4K60 (CEA-861) is the maximum mode supported by the SoC
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* data rate = 594000K * N / 72 = 8250 (standard)
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* (remove K * N due to the same unit)
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*
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* For 2560x1440@144 (clk=583600K, vbp=17):
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* data rate = 583600 / 17 ~= 34329 > 8250 (NG)
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*
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* For 2560x1440@120 (clk=497760K, vbp=77):
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* data rate = 497760 / 77 ~= 6464 < 8250 (OK)
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*
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* A non-standard 4K60 timing (clk=521280K, vbp=54)
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* data rate = 521280 / 54 ~= 9653 > 8250 (NG)
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*
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* Bandwidth requirement of hardware prefetch increases significantly
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* when the VBP decreases (more than 4x in this example).
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*
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* The proposed formula is only one way to estimate whether our SoC
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* supports the mode setting. The basic idea behind it is just to check
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* if the data rate requirement is too high (directly proportional to
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* pixel clock, inversely proportional to vbp). Please adjust the
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* function if it doesn't fit your situation in the future.
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*/
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rate = mode->clock / (mode->vtotal - mode->vsync_end);
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if (rate > 8250) {
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dev_dbg(dev, "invalid rate: %lu (>8250): " DRM_MODE_FMT "\n",
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rate, DRM_MODE_ARG(mode));
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return MODE_BAD;
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}
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return MODE_OK;
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}
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static int mtk_disp_merge_bind(struct device *dev, struct device *master,
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void *data)
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{
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@ -30,6 +30,7 @@ enum mtk_ovl_adaptor_comp_type {
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OVL_ADAPTOR_TYPE_ETHDR,
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OVL_ADAPTOR_TYPE_MDP_RDMA,
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OVL_ADAPTOR_TYPE_MERGE,
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OVL_ADAPTOR_TYPE_PADDING,
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OVL_ADAPTOR_TYPE_NUM,
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};
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@ -47,6 +48,14 @@ enum mtk_ovl_adaptor_comp_id {
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OVL_ADAPTOR_MERGE1,
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OVL_ADAPTOR_MERGE2,
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OVL_ADAPTOR_MERGE3,
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OVL_ADAPTOR_PADDING0,
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OVL_ADAPTOR_PADDING1,
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OVL_ADAPTOR_PADDING2,
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OVL_ADAPTOR_PADDING3,
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OVL_ADAPTOR_PADDING4,
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OVL_ADAPTOR_PADDING5,
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OVL_ADAPTOR_PADDING6,
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OVL_ADAPTOR_PADDING7,
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OVL_ADAPTOR_ID_MAX
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};
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@ -67,6 +76,7 @@ static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {
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[OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
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[OVL_ADAPTOR_TYPE_MDP_RDMA] = "vdo1-rdma",
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[OVL_ADAPTOR_TYPE_MERGE] = "merge",
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[OVL_ADAPTOR_TYPE_PADDING] = "padding",
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};
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static const struct mtk_ddp_comp_funcs ethdr = {
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@ -79,6 +89,14 @@ static const struct mtk_ddp_comp_funcs ethdr = {
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static const struct mtk_ddp_comp_funcs merge = {
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.clk_enable = mtk_merge_clk_enable,
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.clk_disable = mtk_merge_clk_disable,
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.mode_valid = mtk_merge_mode_valid,
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};
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static const struct mtk_ddp_comp_funcs padding = {
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.clk_enable = mtk_padding_clk_enable,
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.clk_disable = mtk_padding_clk_disable,
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.start = mtk_padding_start,
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.stop = mtk_padding_stop,
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};
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static const struct mtk_ddp_comp_funcs rdma = {
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@ -102,6 +120,14 @@ static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
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[OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &merge },
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[OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &merge },
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[OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &merge },
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[OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0, &padding },
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[OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1, &padding },
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[OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2, &padding },
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[OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3, &padding },
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[OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4, &padding },
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[OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5, &padding },
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[OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6, &padding },
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[OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7, &padding },
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};
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void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
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@ -317,6 +343,22 @@ void mtk_ovl_adaptor_clk_disable(struct device *dev)
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}
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}
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enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct device *dev,
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const struct drm_display_mode *mode)
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{
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int i;
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struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
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for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
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dev = ovl_adaptor->ovl_adaptor_comp[i];
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if (!dev || !comp_matches[i].funcs->mode_valid)
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continue;
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return comp_matches[i].funcs->mode_valid(dev, mode);
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}
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return MODE_OK;
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}
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unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev)
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{
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return MTK_OVL_ADAPTOR_LAYER_NUM;
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@ -437,6 +479,7 @@ static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
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}
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static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {
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{ .compatible = "mediatek,mt8188-disp-padding", .data = (void *)OVL_ADAPTOR_TYPE_PADDING },
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{ .compatible = "mediatek,mt8195-disp-ethdr", .data = (void *)OVL_ADAPTOR_TYPE_ETHDR },
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{ .compatible = "mediatek,mt8195-disp-merge", .data = (void *)OVL_ADAPTOR_TYPE_MERGE },
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{ .compatible = "mediatek,mt8195-vdo1-rdma", .data = (void *)OVL_ADAPTOR_TYPE_MDP_RDMA },
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@ -95,11 +95,13 @@ static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
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struct drm_crtc *crtc = &mtk_crtc->base;
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unsigned long flags;
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
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drm_crtc_vblank_put(crtc);
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mtk_crtc->event = NULL;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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if (mtk_crtc->event) {
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spin_lock_irqsave(&crtc->dev->event_lock, flags);
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drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
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drm_crtc_vblank_put(crtc);
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mtk_crtc->event = NULL;
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spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
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}
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}
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static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
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@ -213,6 +215,22 @@ static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc,
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kfree(to_mtk_crtc_state(state));
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}
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static enum drm_mode_status
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mtk_drm_crtc_mode_valid(struct drm_crtc *crtc,
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const struct drm_display_mode *mode)
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{
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struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
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enum drm_mode_status status = MODE_OK;
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int i;
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for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
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status = mtk_ddp_comp_mode_valid(mtk_crtc->ddp_comp[i], mode);
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if (status != MODE_OK)
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break;
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}
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return status;
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}
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static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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@ -831,6 +849,7 @@ static const struct drm_crtc_funcs mtk_crtc_funcs = {
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static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
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.mode_fixup = mtk_drm_crtc_mode_fixup,
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.mode_set_nofb = mtk_drm_crtc_mode_set_nofb,
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.mode_valid = mtk_drm_crtc_mode_valid,
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.atomic_begin = mtk_drm_crtc_atomic_begin,
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.atomic_flush = mtk_drm_crtc_atomic_flush,
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.atomic_enable = mtk_drm_crtc_atomic_enable,
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@ -418,6 +418,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = {
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.remove = mtk_ovl_adaptor_remove_comp,
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.get_formats = mtk_ovl_adaptor_get_formats,
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.get_num_formats = mtk_ovl_adaptor_get_num_formats,
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.mode_valid = mtk_ovl_adaptor_mode_valid,
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};
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static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
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@ -12,6 +12,8 @@
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#include <linux/soc/mediatek/mtk-mmsys.h>
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#include <linux/soc/mediatek/mtk-mutex.h>
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#include <drm/drm_modes.h>
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struct device;
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struct device_node;
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struct drm_crtc;
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@ -85,6 +87,7 @@ struct mtk_ddp_comp_funcs {
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void (*add)(struct device *dev, struct mtk_mutex *mutex);
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void (*remove)(struct device *dev, struct mtk_mutex *mutex);
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unsigned int (*encoder_index)(struct device *dev);
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enum drm_mode_status (*mode_valid)(struct device *dev, const struct drm_display_mode *mode);
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};
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struct mtk_ddp_comp {
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@ -126,6 +129,15 @@ static inline void mtk_ddp_comp_clk_disable(struct mtk_ddp_comp *comp)
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comp->funcs->clk_disable(comp->dev);
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}
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static inline
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enum drm_mode_status mtk_ddp_comp_mode_valid(struct mtk_ddp_comp *comp,
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const struct drm_display_mode *mode)
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{
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if (comp && comp->funcs && comp->funcs->mode_valid)
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return comp->funcs->mode_valid(comp->dev, mode);
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return MODE_OK;
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}
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static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
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unsigned int w, unsigned int h,
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unsigned int vrefresh, unsigned int bpc,
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@ -293,7 +293,7 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
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.main_len = ARRAY_SIZE(mt8188_mtk_ddp_main),
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.conn_routes = mt8188_mtk_ddp_main_routes,
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.num_conn_routes = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
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.mmsys_dev_num = 1,
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.mmsys_dev_num = 2,
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};
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static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
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@ -334,6 +334,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
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.data = &mt8186_mmsys_driver_data},
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{ .compatible = "mediatek,mt8188-vdosys0",
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.data = &mt8188_vdosys0_driver_data},
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{ .compatible = "mediatek,mt8188-vdosys1",
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.data = &mt8195_vdosys1_driver_data},
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{ .compatible = "mediatek,mt8192-mmsys",
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.data = &mt8192_mmsys_driver_data},
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{ .compatible = "mediatek,mt8195-mmsys",
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@ -3,6 +3,7 @@
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/iopoll.h>
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@ -12,6 +13,7 @@
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/reset.h>
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#include <linux/units.h>
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#include <video/mipi_display.h>
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#include <video/videomode.h>
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@ -58,28 +60,31 @@
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#define DSI_TXRX_CTRL 0x18
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#define VC_NUM BIT(1)
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#define LANE_NUM (0xf << 2)
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#define LANE_NUM GENMASK(5, 2)
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#define DIS_EOT BIT(6)
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#define NULL_EN BIT(7)
|
||||
#define TE_FREERUN BIT(8)
|
||||
#define EXT_TE_EN BIT(9)
|
||||
#define EXT_TE_EDGE BIT(10)
|
||||
#define MAX_RTN_SIZE (0xf << 12)
|
||||
#define MAX_RTN_SIZE GENMASK(15, 12)
|
||||
#define HSTX_CKLP_EN BIT(16)
|
||||
|
||||
#define DSI_PSCTRL 0x1c
|
||||
#define DSI_PS_WC 0x3fff
|
||||
#define DSI_PS_SEL (3 << 16)
|
||||
#define PACKED_PS_16BIT_RGB565 (0 << 16)
|
||||
#define LOOSELY_PS_18BIT_RGB666 (1 << 16)
|
||||
#define PACKED_PS_18BIT_RGB666 (2 << 16)
|
||||
#define PACKED_PS_24BIT_RGB888 (3 << 16)
|
||||
#define DSI_PS_WC GENMASK(13, 0)
|
||||
#define DSI_PS_SEL GENMASK(17, 16)
|
||||
#define PACKED_PS_16BIT_RGB565 0
|
||||
#define PACKED_PS_18BIT_RGB666 1
|
||||
#define LOOSELY_PS_24BIT_RGB666 2
|
||||
#define PACKED_PS_24BIT_RGB888 3
|
||||
|
||||
#define DSI_VSA_NL 0x20
|
||||
#define DSI_VBP_NL 0x24
|
||||
#define DSI_VFP_NL 0x28
|
||||
#define DSI_VACT_NL 0x2C
|
||||
#define VACT_NL GENMASK(14, 0)
|
||||
#define DSI_SIZE_CON 0x38
|
||||
#define DSI_HEIGHT GENMASK(30, 16)
|
||||
#define DSI_WIDTH GENMASK(14, 0)
|
||||
#define DSI_HSA_WC 0x50
|
||||
#define DSI_HBP_WC 0x54
|
||||
#define DSI_HFP_WC 0x58
|
||||
|
|
@ -109,26 +114,27 @@
|
|||
#define LD0_WAKEUP_EN BIT(2)
|
||||
|
||||
#define DSI_PHY_TIMECON0 0x110
|
||||
#define LPX (0xff << 0)
|
||||
#define HS_PREP (0xff << 8)
|
||||
#define HS_ZERO (0xff << 16)
|
||||
#define HS_TRAIL (0xff << 24)
|
||||
#define LPX GENMASK(7, 0)
|
||||
#define HS_PREP GENMASK(15, 8)
|
||||
#define HS_ZERO GENMASK(23, 16)
|
||||
#define HS_TRAIL GENMASK(31, 24)
|
||||
|
||||
#define DSI_PHY_TIMECON1 0x114
|
||||
#define TA_GO (0xff << 0)
|
||||
#define TA_SURE (0xff << 8)
|
||||
#define TA_GET (0xff << 16)
|
||||
#define DA_HS_EXIT (0xff << 24)
|
||||
#define TA_GO GENMASK(7, 0)
|
||||
#define TA_SURE GENMASK(15, 8)
|
||||
#define TA_GET GENMASK(23, 16)
|
||||
#define DA_HS_EXIT GENMASK(31, 24)
|
||||
|
||||
#define DSI_PHY_TIMECON2 0x118
|
||||
#define CONT_DET (0xff << 0)
|
||||
#define CLK_ZERO (0xff << 16)
|
||||
#define CLK_TRAIL (0xff << 24)
|
||||
#define CONT_DET GENMASK(7, 0)
|
||||
#define DA_HS_SYNC GENMASK(15, 8)
|
||||
#define CLK_ZERO GENMASK(23, 16)
|
||||
#define CLK_TRAIL GENMASK(31, 24)
|
||||
|
||||
#define DSI_PHY_TIMECON3 0x11c
|
||||
#define CLK_HS_PREP (0xff << 0)
|
||||
#define CLK_HS_POST (0xff << 8)
|
||||
#define CLK_HS_EXIT (0xff << 16)
|
||||
#define CLK_HS_PREP GENMASK(7, 0)
|
||||
#define CLK_HS_POST GENMASK(15, 8)
|
||||
#define CLK_HS_EXIT GENMASK(23, 16)
|
||||
|
||||
#define DSI_VM_CMD_CON 0x130
|
||||
#define VM_CMD_EN BIT(0)
|
||||
|
|
@ -138,13 +144,14 @@
|
|||
#define FORCE_COMMIT BIT(0)
|
||||
#define BYPASS_SHADOW BIT(1)
|
||||
|
||||
#define CONFIG (0xff << 0)
|
||||
/* CMDQ related bits */
|
||||
#define CONFIG GENMASK(7, 0)
|
||||
#define SHORT_PACKET 0
|
||||
#define LONG_PACKET 2
|
||||
#define BTA BIT(2)
|
||||
#define DATA_ID (0xff << 8)
|
||||
#define DATA_0 (0xff << 16)
|
||||
#define DATA_1 (0xff << 24)
|
||||
#define DATA_ID GENMASK(15, 8)
|
||||
#define DATA_0 GENMASK(23, 16)
|
||||
#define DATA_1 GENMASK(31, 24)
|
||||
|
||||
#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
|
||||
|
||||
|
|
@ -232,7 +239,7 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
|
|||
static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
|
||||
{
|
||||
u32 timcon0, timcon1, timcon2, timcon3;
|
||||
u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
|
||||
u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ);
|
||||
struct mtk_phy_timing *timing = &dsi->phy_timing;
|
||||
|
||||
timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
|
||||
|
|
@ -252,14 +259,23 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
|
|||
timing->clk_hs_zero = timing->clk_hs_trail * 4;
|
||||
timing->clk_hs_exit = 2 * timing->clk_hs_trail;
|
||||
|
||||
timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
|
||||
timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
|
||||
timcon1 = timing->ta_go | timing->ta_sure << 8 |
|
||||
timing->ta_get << 16 | timing->da_hs_exit << 24;
|
||||
timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
|
||||
timing->clk_hs_trail << 24;
|
||||
timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
|
||||
timing->clk_hs_exit << 16;
|
||||
timcon0 = FIELD_PREP(LPX, timing->lpx) |
|
||||
FIELD_PREP(HS_PREP, timing->da_hs_prepare) |
|
||||
FIELD_PREP(HS_ZERO, timing->da_hs_zero) |
|
||||
FIELD_PREP(HS_TRAIL, timing->da_hs_trail);
|
||||
|
||||
timcon1 = FIELD_PREP(TA_GO, timing->ta_go) |
|
||||
FIELD_PREP(TA_SURE, timing->ta_sure) |
|
||||
FIELD_PREP(TA_GET, timing->ta_get) |
|
||||
FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit);
|
||||
|
||||
timcon2 = FIELD_PREP(DA_HS_SYNC, 1) |
|
||||
FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) |
|
||||
FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail);
|
||||
|
||||
timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) |
|
||||
FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) |
|
||||
FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit);
|
||||
|
||||
writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
|
||||
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
|
||||
|
|
@ -350,101 +366,63 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
|
|||
mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
|
||||
}
|
||||
|
||||
static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
|
||||
static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
|
||||
{
|
||||
struct videomode *vm = &dsi->vm;
|
||||
u32 dsi_buf_bpp, ps_wc;
|
||||
u32 ps_bpp_mode;
|
||||
u32 regval, tmp_reg = 0;
|
||||
u8 i;
|
||||
|
||||
/* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */
|
||||
for (i = 0; i < dsi->lanes; i++)
|
||||
tmp_reg |= BIT(i);
|
||||
|
||||
regval = FIELD_PREP(LANE_NUM, tmp_reg);
|
||||
|
||||
if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
|
||||
regval |= HSTX_CKLP_EN;
|
||||
|
||||
if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
|
||||
regval |= DIS_EOT;
|
||||
|
||||
writel(regval, dsi->regs + DSI_TXRX_CTRL);
|
||||
}
|
||||
|
||||
static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact)
|
||||
{
|
||||
u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl;
|
||||
|
||||
if (dsi->format == MIPI_DSI_FMT_RGB565)
|
||||
dsi_buf_bpp = 2;
|
||||
else
|
||||
dsi_buf_bpp = 3;
|
||||
|
||||
ps_wc = vm->hactive * dsi_buf_bpp;
|
||||
ps_bpp_mode = ps_wc;
|
||||
/* Word count */
|
||||
ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp);
|
||||
ps_val = ps_wc;
|
||||
|
||||
/* Pixel Stream type */
|
||||
switch (dsi->format) {
|
||||
default:
|
||||
fallthrough;
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
|
||||
ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888);
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
|
||||
ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666);
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
|
||||
ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666);
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
|
||||
ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565);
|
||||
break;
|
||||
}
|
||||
|
||||
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
|
||||
writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
|
||||
writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
|
||||
}
|
||||
|
||||
static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
|
||||
{
|
||||
u32 tmp_reg;
|
||||
|
||||
switch (dsi->lanes) {
|
||||
case 1:
|
||||
tmp_reg = 1 << 2;
|
||||
break;
|
||||
case 2:
|
||||
tmp_reg = 3 << 2;
|
||||
break;
|
||||
case 3:
|
||||
tmp_reg = 7 << 2;
|
||||
break;
|
||||
case 4:
|
||||
tmp_reg = 0xf << 2;
|
||||
break;
|
||||
default:
|
||||
tmp_reg = 0xf << 2;
|
||||
break;
|
||||
if (config_vact) {
|
||||
vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive);
|
||||
writel(vact_nl, dsi->regs + DSI_VACT_NL);
|
||||
writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
|
||||
}
|
||||
|
||||
if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
|
||||
tmp_reg |= HSTX_CKLP_EN;
|
||||
|
||||
if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
|
||||
tmp_reg |= DIS_EOT;
|
||||
|
||||
writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
|
||||
}
|
||||
|
||||
static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
|
||||
{
|
||||
u32 dsi_tmp_buf_bpp;
|
||||
u32 tmp_reg;
|
||||
|
||||
switch (dsi->format) {
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
tmp_reg = PACKED_PS_24BIT_RGB888;
|
||||
dsi_tmp_buf_bpp = 3;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
tmp_reg = LOOSELY_PS_18BIT_RGB666;
|
||||
dsi_tmp_buf_bpp = 3;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
tmp_reg = PACKED_PS_18BIT_RGB666;
|
||||
dsi_tmp_buf_bpp = 3;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
tmp_reg = PACKED_PS_16BIT_RGB565;
|
||||
dsi_tmp_buf_bpp = 2;
|
||||
break;
|
||||
default:
|
||||
tmp_reg = PACKED_PS_24BIT_RGB888;
|
||||
dsi_tmp_buf_bpp = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
|
||||
writel(tmp_reg, dsi->regs + DSI_PSCTRL);
|
||||
writel(ps_val, dsi->regs + DSI_PSCTRL);
|
||||
}
|
||||
|
||||
static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
|
||||
|
|
@ -471,7 +449,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
|
|||
writel(vm->vactive, dsi->regs + DSI_VACT_NL);
|
||||
|
||||
if (dsi->driver_data->has_size_ctl)
|
||||
writel(vm->vactive << 16 | vm->hactive,
|
||||
writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) |
|
||||
FIELD_PREP(DSI_WIDTH, vm->hactive),
|
||||
dsi->regs + DSI_SIZE_CON);
|
||||
|
||||
horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
|
||||
|
|
@ -520,7 +499,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
|
|||
writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
|
||||
writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
|
||||
|
||||
mtk_dsi_ps_control(dsi);
|
||||
mtk_dsi_ps_control(dsi, false);
|
||||
}
|
||||
|
||||
static void mtk_dsi_start(struct mtk_dsi *dsi)
|
||||
|
|
@ -619,19 +598,12 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
|
|||
if (++dsi->refcount != 1)
|
||||
return 0;
|
||||
|
||||
switch (dsi->format) {
|
||||
case MIPI_DSI_FMT_RGB565:
|
||||
bit_per_pixel = 16;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||
bit_per_pixel = 18;
|
||||
break;
|
||||
case MIPI_DSI_FMT_RGB666:
|
||||
case MIPI_DSI_FMT_RGB888:
|
||||
default:
|
||||
bit_per_pixel = 24;
|
||||
break;
|
||||
ret = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Unknown MIPI DSI format %d\n", dsi->format);
|
||||
return ret;
|
||||
}
|
||||
bit_per_pixel = ret;
|
||||
|
||||
dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
|
||||
dsi->lanes);
|
||||
|
|
@ -665,7 +637,7 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
|
|||
mtk_dsi_reset_engine(dsi);
|
||||
mtk_dsi_phy_timconfig(dsi);
|
||||
|
||||
mtk_dsi_ps_control_vact(dsi);
|
||||
mtk_dsi_ps_control(dsi, true);
|
||||
mtk_dsi_set_vm_cmd(dsi);
|
||||
mtk_dsi_config_vdo_timing(dsi);
|
||||
mtk_dsi_set_interrupt_enable(dsi);
|
||||
|
|
@ -814,12 +786,11 @@ mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
|
|||
const struct drm_display_mode *mode)
|
||||
{
|
||||
struct mtk_dsi *dsi = bridge_to_dsi(bridge);
|
||||
u32 bpp;
|
||||
int bpp;
|
||||
|
||||
if (dsi->format == MIPI_DSI_FMT_RGB565)
|
||||
bpp = 16;
|
||||
else
|
||||
bpp = 24;
|
||||
bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||
if (bpp < 0)
|
||||
return MODE_ERROR;
|
||||
|
||||
if (mode->clock * bpp / dsi->lanes > 1500000)
|
||||
return MODE_CLOCK_HIGH;
|
||||
|
|
@ -1135,67 +1106,47 @@ static int mtk_dsi_probe(struct platform_device *pdev)
|
|||
if (!dsi)
|
||||
return -ENOMEM;
|
||||
|
||||
dsi->host.ops = &mtk_dsi_ops;
|
||||
dsi->host.dev = dev;
|
||||
ret = mipi_dsi_host_register(&dsi->host);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to register DSI host: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
dsi->driver_data = of_device_get_match_data(dev);
|
||||
|
||||
dsi->engine_clk = devm_clk_get(dev, "engine");
|
||||
if (IS_ERR(dsi->engine_clk)) {
|
||||
ret = PTR_ERR(dsi->engine_clk);
|
||||
if (IS_ERR(dsi->engine_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(dsi->engine_clk),
|
||||
"Failed to get engine clock\n");
|
||||
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "Failed to get engine clock: %d\n", ret);
|
||||
goto err_unregister_host;
|
||||
}
|
||||
|
||||
dsi->digital_clk = devm_clk_get(dev, "digital");
|
||||
if (IS_ERR(dsi->digital_clk)) {
|
||||
ret = PTR_ERR(dsi->digital_clk);
|
||||
|
||||
if (ret != -EPROBE_DEFER)
|
||||
dev_err(dev, "Failed to get digital clock: %d\n", ret);
|
||||
goto err_unregister_host;
|
||||
}
|
||||
if (IS_ERR(dsi->digital_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(dsi->digital_clk),
|
||||
"Failed to get digital clock\n");
|
||||
|
||||
dsi->hs_clk = devm_clk_get(dev, "hs");
|
||||
if (IS_ERR(dsi->hs_clk)) {
|
||||
ret = PTR_ERR(dsi->hs_clk);
|
||||
dev_err(dev, "Failed to get hs clock: %d\n", ret);
|
||||
goto err_unregister_host;
|
||||
}
|
||||
if (IS_ERR(dsi->hs_clk))
|
||||
return dev_err_probe(dev, PTR_ERR(dsi->hs_clk), "Failed to get hs clock\n");
|
||||
|
||||
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
dsi->regs = devm_ioremap_resource(dev, regs);
|
||||
if (IS_ERR(dsi->regs)) {
|
||||
ret = PTR_ERR(dsi->regs);
|
||||
dev_err(dev, "Failed to ioremap memory: %d\n", ret);
|
||||
goto err_unregister_host;
|
||||
}
|
||||
if (IS_ERR(dsi->regs))
|
||||
return dev_err_probe(dev, PTR_ERR(dsi->regs), "Failed to ioremap memory\n");
|
||||
|
||||
dsi->phy = devm_phy_get(dev, "dphy");
|
||||
if (IS_ERR(dsi->phy)) {
|
||||
ret = PTR_ERR(dsi->phy);
|
||||
dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
|
||||
goto err_unregister_host;
|
||||
}
|
||||
if (IS_ERR(dsi->phy))
|
||||
return dev_err_probe(dev, PTR_ERR(dsi->phy), "Failed to get MIPI-DPHY\n");
|
||||
|
||||
irq_num = platform_get_irq(pdev, 0);
|
||||
if (irq_num < 0) {
|
||||
ret = irq_num;
|
||||
goto err_unregister_host;
|
||||
}
|
||||
if (irq_num < 0)
|
||||
return irq_num;
|
||||
|
||||
dsi->host.ops = &mtk_dsi_ops;
|
||||
dsi->host.dev = dev;
|
||||
ret = mipi_dsi_host_register(&dsi->host);
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "Failed to register DSI host\n");
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
|
||||
IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
|
||||
goto err_unregister_host;
|
||||
mipi_dsi_host_unregister(&dsi->host);
|
||||
return dev_err_probe(&pdev->dev, ret, "Failed to request DSI irq\n");
|
||||
}
|
||||
|
||||
init_waitqueue_head(&dsi->irq_wait_queue);
|
||||
|
|
@ -1207,10 +1158,6 @@ static int mtk_dsi_probe(struct platform_device *pdev)
|
|||
dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister_host:
|
||||
mipi_dsi_host_unregister(&dsi->host);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void mtk_dsi_remove(struct platform_device *pdev)
|
||||
|
|
@ -1249,17 +1196,12 @@ static const struct mtk_dsi_driver_data mt8188_dsi_driver_data = {
|
|||
};
|
||||
|
||||
static const struct of_device_id mtk_dsi_of_match[] = {
|
||||
{ .compatible = "mediatek,mt2701-dsi",
|
||||
.data = &mt2701_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8173-dsi",
|
||||
.data = &mt8173_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8183-dsi",
|
||||
.data = &mt8183_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8186-dsi",
|
||||
.data = &mt8186_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8188-dsi",
|
||||
.data = &mt8188_dsi_driver_data },
|
||||
{ },
|
||||
{ .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8183-dsi", .data = &mt8183_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
|
||||
{ .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue