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bnx2x: MDC/MDIO CL45 IOCTLs
As suggested by Ben Hutchings <bhutchings@solarflare.com>, using the MDC/MDIO IOCTL Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
239d686d49
commit
01cd452846
3 changed files with 94 additions and 43 deletions
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@ -2722,6 +2722,7 @@ config BNX2X
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select FW_LOADER
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select ZLIB_INFLATE
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select LIBCRC32C
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select MDIO
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help
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This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
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To compile this driver as a module, choose M here: the module
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@ -30,6 +30,8 @@
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#define BNX2X_NEW_NAPI
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#include <linux/mdio.h>
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#include "bnx2x_reg.h"
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#include "bnx2x_fw_defs.h"
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#include "bnx2x_hsi.h"
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@ -895,6 +897,7 @@ struct bnx2x {
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struct link_params link_params;
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struct link_vars link_vars;
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struct mdio_if_info mdio;
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struct bnx2x_common common;
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struct bnx2x_port port;
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@ -8331,6 +8331,7 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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u32 val, val2;
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u32 config;
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u16 i;
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u32 ext_phy_type;
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bp->link_params.bp = bp;
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bp->link_params.port = port;
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@ -8390,6 +8391,21 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
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bnx2x_link_settings_requested(bp);
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/*
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* If connected directly, work with the internal PHY, otherwise, work
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* with the external PHY
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*/
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ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
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if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
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bp->mdio.prtad = bp->link_params.phy_addr;
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else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
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(ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
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bp->mdio.prtad =
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(bp->link_params.ext_phy_config &
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT;
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val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
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val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
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bp->dev->dev_addr[0] = (u8)(val2 >> 8 & 0xff);
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@ -8614,7 +8630,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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} else
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cmd->port = PORT_TP;
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cmd->phy_address = bp->port.phy_addr;
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cmd->phy_address = bp->mdio.prtad;
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cmd->transceiver = XCVR_INTERNAL;
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if (bp->link_params.req_line_speed == SPEED_AUTO_NEG)
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@ -11148,55 +11164,78 @@ static int bnx2x_change_mac_addr(struct net_device *dev, void *p)
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return 0;
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}
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/* called with rtnl_lock */
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static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
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int devad, u16 addr)
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{
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struct bnx2x *bp = netdev_priv(netdev);
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u16 value;
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int rc;
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u32 phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
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DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
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prtad, devad, addr);
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if (prtad != bp->mdio.prtad) {
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DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
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prtad, bp->mdio.prtad);
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return -EINVAL;
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}
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/* The HW expects different devad if CL22 is used */
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devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
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bnx2x_acquire_phy_lock(bp);
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rc = bnx2x_cl45_read(bp, BP_PORT(bp), phy_type, prtad,
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devad, addr, &value);
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bnx2x_release_phy_lock(bp);
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DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
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if (!rc)
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rc = value;
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return rc;
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}
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/* called with rtnl_lock */
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static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
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u16 addr, u16 value)
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{
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struct bnx2x *bp = netdev_priv(netdev);
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u32 ext_phy_type = XGXS_EXT_PHY_TYPE(bp->link_params.ext_phy_config);
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int rc;
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DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
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" value 0x%x\n", prtad, devad, addr, value);
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if (prtad != bp->mdio.prtad) {
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DP(NETIF_MSG_LINK, "prtad missmatch (cmd:0x%x != bp:0x%x)\n",
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prtad, bp->mdio.prtad);
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return -EINVAL;
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}
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/* The HW expects different devad if CL22 is used */
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devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
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bnx2x_acquire_phy_lock(bp);
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rc = bnx2x_cl45_write(bp, BP_PORT(bp), ext_phy_type, prtad,
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devad, addr, value);
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bnx2x_release_phy_lock(bp);
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return rc;
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}
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/* called with rtnl_lock */
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static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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{
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struct mii_ioctl_data *data = if_mii(ifr);
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struct bnx2x *bp = netdev_priv(dev);
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int port = BP_PORT(bp);
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int err;
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struct mii_ioctl_data *mdio = if_mii(ifr);
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switch (cmd) {
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case SIOCGMIIPHY:
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data->phy_id = bp->port.phy_addr;
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DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
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mdio->phy_id, mdio->reg_num, mdio->val_in);
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/* fallthrough */
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if (!netif_running(dev))
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return -EAGAIN;
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case SIOCGMIIREG: {
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u16 mii_regval;
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if (!netif_running(dev))
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return -EAGAIN;
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mutex_lock(&bp->port.phy_mutex);
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err = bnx2x_cl45_read(bp, port, 0, bp->port.phy_addr,
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DEFAULT_PHY_DEV_ADDR,
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(data->reg_num & 0x1f), &mii_regval);
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data->val_out = mii_regval;
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mutex_unlock(&bp->port.phy_mutex);
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return err;
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}
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case SIOCSMIIREG:
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if (!capable(CAP_NET_ADMIN))
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return -EPERM;
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if (!netif_running(dev))
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return -EAGAIN;
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mutex_lock(&bp->port.phy_mutex);
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err = bnx2x_cl45_write(bp, port, 0, bp->port.phy_addr,
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DEFAULT_PHY_DEV_ADDR,
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(data->reg_num & 0x1f), data->val_in);
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mutex_unlock(&bp->port.phy_mutex);
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return err;
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default:
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/* do nothing */
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break;
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}
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return -EOPNOTSUPP;
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return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
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}
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/* called with rtnl_lock */
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@ -11420,6 +11459,14 @@ static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
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dev->vlan_features |= NETIF_F_TSO6;
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#endif
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/* get_port_hwinfo() will set prtad and mmds properly */
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bp->mdio.prtad = MDIO_PRTAD_NONE;
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bp->mdio.mmds = 0;
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bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
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bp->mdio.dev = dev;
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bp->mdio.mdio_read = bnx2x_mdio_read;
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bp->mdio.mdio_write = bnx2x_mdio_write;
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return 0;
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err_out_unmap:
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