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KVM: VMX: Check the posted interrupt capability
Detect the posted interrupt feature. If it exists, then set it in vmcs_config. Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Reviewed-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
This commit is contained in:
parent
d78f266483
commit
01e439be77
2 changed files with 66 additions and 20 deletions
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@ -71,6 +71,7 @@
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#define PIN_BASED_NMI_EXITING 0x00000008
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#define PIN_BASED_VIRTUAL_NMIS 0x00000020
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#define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
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#define PIN_BASED_POSTED_INTR 0x00000080
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#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
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@ -102,6 +103,7 @@
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/* VMCS Encodings */
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enum vmcs_field {
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VIRTUAL_PROCESSOR_ID = 0x00000000,
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POSTED_INTR_NV = 0x00000002,
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GUEST_ES_SELECTOR = 0x00000800,
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GUEST_CS_SELECTOR = 0x00000802,
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GUEST_SS_SELECTOR = 0x00000804,
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@ -136,6 +138,8 @@ enum vmcs_field {
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VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
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APIC_ACCESS_ADDR = 0x00002014,
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APIC_ACCESS_ADDR_HIGH = 0x00002015,
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POSTED_INTR_DESC_ADDR = 0x00002016,
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POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
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EPT_POINTER = 0x0000201a,
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EPT_POINTER_HIGH = 0x0000201b,
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EOI_EXIT_BITMAP0 = 0x0000201c,
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@ -84,7 +84,8 @@ module_param(vmm_exclusive, bool, S_IRUGO);
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static bool __read_mostly fasteoi = 1;
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module_param(fasteoi, bool, S_IRUGO);
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static bool __read_mostly enable_apicv_reg_vid;
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static bool __read_mostly enable_apicv;
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module_param(enable_apicv, bool, S_IRUGO);
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/*
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* If nested=1, nested virtualization is supported, i.e., guests may use
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@ -366,6 +367,14 @@ struct nested_vmx {
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struct page *apic_access_page;
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};
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#define POSTED_INTR_ON 0
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/* Posted-Interrupt Descriptor */
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struct pi_desc {
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u32 pir[8]; /* Posted interrupt requested */
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u32 control; /* bit 0 of control is outstanding notification bit */
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u32 rsvd[7];
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} __aligned(64);
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struct vcpu_vmx {
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struct kvm_vcpu vcpu;
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unsigned long host_rsp;
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@ -430,6 +439,9 @@ struct vcpu_vmx {
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bool rdtscp_enabled;
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/* Posted interrupt descriptor */
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struct pi_desc pi_desc;
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/* Support for a guest hypervisor (nested VMX) */
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struct nested_vmx nested;
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};
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@ -785,6 +797,18 @@ static inline bool cpu_has_vmx_virtual_intr_delivery(void)
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SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
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}
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static inline bool cpu_has_vmx_posted_intr(void)
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{
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return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
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}
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static inline bool cpu_has_vmx_apicv(void)
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{
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return cpu_has_vmx_apic_register_virt() &&
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cpu_has_vmx_virtual_intr_delivery() &&
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cpu_has_vmx_posted_intr();
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}
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static inline bool cpu_has_vmx_flexpriority(void)
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{
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return cpu_has_vmx_tpr_shadow() &&
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@ -2552,12 +2576,6 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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u32 _vmexit_control = 0;
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u32 _vmentry_control = 0;
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min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
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opt = PIN_BASED_VIRTUAL_NMIS;
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if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
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&_pin_based_exec_control) < 0)
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return -EIO;
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min = CPU_BASED_HLT_EXITING |
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#ifdef CONFIG_X86_64
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CPU_BASED_CR8_LOAD_EXITING |
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@ -2634,6 +2652,17 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
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&_vmexit_control) < 0)
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return -EIO;
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min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
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opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
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if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
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&_pin_based_exec_control) < 0)
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return -EIO;
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if (!(_cpu_based_2nd_exec_control &
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SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
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!(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
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_pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
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min = 0;
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opt = VM_ENTRY_LOAD_IA32_PAT;
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if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
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@ -2812,11 +2841,10 @@ static __init int hardware_setup(void)
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if (!cpu_has_vmx_ple())
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ple_gap = 0;
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if (!cpu_has_vmx_apic_register_virt() ||
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!cpu_has_vmx_virtual_intr_delivery())
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enable_apicv_reg_vid = 0;
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if (!cpu_has_vmx_apicv())
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enable_apicv = 0;
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if (enable_apicv_reg_vid)
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if (enable_apicv)
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kvm_x86_ops->update_cr8_intercept = NULL;
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else
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kvm_x86_ops->hwapic_irr_update = NULL;
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@ -3875,6 +3903,11 @@ static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
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msr, MSR_TYPE_W);
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}
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static int vmx_vm_has_apicv(struct kvm *kvm)
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{
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return enable_apicv && irqchip_in_kernel(kvm);
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}
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/*
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* Set up the vmcs's constant host-state fields, i.e., host-state fields that
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* will not change in the lifetime of the guest.
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@ -3935,6 +3968,15 @@ static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
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vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
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}
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static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
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{
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u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
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if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
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pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
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return pin_based_exec_ctrl;
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}
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static u32 vmx_exec_control(struct vcpu_vmx *vmx)
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{
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u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
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@ -3952,11 +3994,6 @@ static u32 vmx_exec_control(struct vcpu_vmx *vmx)
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return exec_control;
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}
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static int vmx_vm_has_apicv(struct kvm *kvm)
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{
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return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
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}
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static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
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{
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u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
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@ -4012,8 +4049,7 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
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vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
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/* Control */
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vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
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vmcs_config.pin_based_exec_ctrl);
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vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
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vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
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@ -4022,13 +4058,16 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
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vmx_secondary_exec_control(vmx));
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}
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if (enable_apicv_reg_vid) {
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if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
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vmcs_write64(EOI_EXIT_BITMAP0, 0);
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vmcs_write64(EOI_EXIT_BITMAP1, 0);
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vmcs_write64(EOI_EXIT_BITMAP2, 0);
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vmcs_write64(EOI_EXIT_BITMAP3, 0);
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vmcs_write16(GUEST_INTR_STATUS, 0);
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vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
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vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
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}
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if (ple_gap) {
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@ -4170,6 +4209,9 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
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vmcs_write64(APIC_ACCESS_ADDR,
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page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
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if (vmx_vm_has_apicv(vcpu->kvm))
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memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
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if (vmx->vpid != 0)
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vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
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@ -7842,7 +7884,7 @@ static int __init vmx_init(void)
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memcpy(vmx_msr_bitmap_longmode_x2apic,
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vmx_msr_bitmap_longmode, PAGE_SIZE);
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if (enable_apicv_reg_vid) {
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if (enable_apicv) {
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for (msr = 0x800; msr <= 0x8ff; msr++)
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vmx_disable_intercept_msr_read_x2apic(msr);
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