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ARM: socfpga: dts: fix s2f_* clock name
The s2f_* clocks are called h2f_* in the datasheets. Rename them accordingly in the socfpga.dtsi. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
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parent
7857d560da
commit
01ed80b07d
1 changed files with 8 additions and 8 deletions
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@ -147,7 +147,7 @@ main_nand_sdmmc_clk: main_nand_sdmmc_clk {
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reg = <0x58>;
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reg = <0x58>;
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};
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};
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cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
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cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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compatible = "altr,socfpga-perip-clk";
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clocks = <&main_pll>;
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clocks = <&main_pll>;
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@ -198,7 +198,7 @@ per_base_clk: per_base_clk {
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reg = <0x98>;
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reg = <0x98>;
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};
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};
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s2f_usr1_clk: s2f_usr1_clk {
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h2f_usr1_clk: h2f_usr1_clk {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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compatible = "altr,socfpga-perip-clk";
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clocks = <&periph_pll>;
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clocks = <&periph_pll>;
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@ -235,7 +235,7 @@ ddr_dq_clk: ddr_dq_clk {
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reg = <0xD0>;
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reg = <0xD0>;
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};
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};
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s2f_usr2_clk: s2f_usr2_clk {
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h2f_usr2_clk: h2f_usr2_clk {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-perip-clk";
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compatible = "altr,socfpga-perip-clk";
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clocks = <&sdram_pll>;
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clocks = <&sdram_pll>;
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@ -335,14 +335,14 @@ dbg_timer_clk: dbg_timer_clk {
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cfg_clk: cfg_clk {
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cfg_clk: cfg_clk {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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compatible = "altr,socfpga-gate-clk";
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clocks = <&cfg_s2f_usr0_clk>;
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clocks = <&cfg_h2f_usr0_clk>;
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clk-gate = <0x60 8>;
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clk-gate = <0x60 8>;
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};
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};
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s2f_user0_clk: s2f_user0_clk {
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h2f_user0_clk: h2f_user0_clk {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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compatible = "altr,socfpga-gate-clk";
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clocks = <&cfg_s2f_usr0_clk>;
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clocks = <&cfg_h2f_usr0_clk>;
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clk-gate = <0x60 9>;
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clk-gate = <0x60 9>;
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};
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};
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@ -400,10 +400,10 @@ gpio_db_clk: gpio_db_clk {
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div-reg = <0xa8 0 24>;
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div-reg = <0xa8 0 24>;
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};
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};
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s2f_user1_clk: s2f_user1_clk {
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h2f_user1_clk: h2f_user1_clk {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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compatible = "altr,socfpga-gate-clk";
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clocks = <&s2f_usr1_clk>;
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clocks = <&h2f_usr1_clk>;
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clk-gate = <0xa0 7>;
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clk-gate = <0xa0 7>;
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};
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};
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