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ARM: socfpga: dts: fix s2f_* clock name

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The s2f_* clocks are called h2f_* in the datasheets.
Rename them accordingly in the socfpga.dtsi.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
This commit is contained in:
Steffen Trumtrar 2013-10-07 11:11:38 -05:00 committed by Dinh Nguyen
parent 7857d560da
commit 01ed80b07d
1 changed files with 8 additions and 8 deletions
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16
arch/arm/boot/dts/socfpga.dtsi
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@ -147,7 +147,7 @@ main_nand_sdmmc_clk: main_nand_sdmmc_clk {
reg = <0x58>; reg = <0x58>;
}; };
cfg_s2f_usr0_clk: cfg_s2f_usr0_clk { cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-perip-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>; clocks = <&main_pll>;
@ -198,7 +198,7 @@ per_base_clk: per_base_clk {
reg = <0x98>; reg = <0x98>;
}; };
s2f_usr1_clk: s2f_usr1_clk { h2f_usr1_clk: h2f_usr1_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-perip-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>; clocks = <&periph_pll>;
@ -235,7 +235,7 @@ ddr_dq_clk: ddr_dq_clk {
reg = <0xD0>; reg = <0xD0>;
}; };
s2f_usr2_clk: s2f_usr2_clk { h2f_usr2_clk: h2f_usr2_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-perip-clk"; compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>; clocks = <&sdram_pll>;
@ -335,14 +335,14 @@ dbg_timer_clk: dbg_timer_clk {
cfg_clk: cfg_clk { cfg_clk: cfg_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-gate-clk";
clocks = <&cfg_s2f_usr0_clk>; clocks = <&cfg_h2f_usr0_clk>;
clk-gate = <0x60 8>; clk-gate = <0x60 8>;
}; };
s2f_user0_clk: s2f_user0_clk { h2f_user0_clk: h2f_user0_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-gate-clk";
clocks = <&cfg_s2f_usr0_clk>; clocks = <&cfg_h2f_usr0_clk>;
clk-gate = <0x60 9>; clk-gate = <0x60 9>;
}; };
@ -400,10 +400,10 @@ gpio_db_clk: gpio_db_clk {
div-reg = <0xa8 0 24>; div-reg = <0xa8 0 24>;
}; };
s2f_user1_clk: s2f_user1_clk { h2f_user1_clk: h2f_user1_clk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "altr,socfpga-gate-clk"; compatible = "altr,socfpga-gate-clk";
clocks = <&s2f_usr1_clk>; clocks = <&h2f_usr1_clk>;
clk-gate = <0xa0 7>; clk-gate = <0xa0 7>;
}; };