SoC: DT changes for 6.2
The devicetree changes contain exactly 1000 non-merge changesets,
including a number of new arm64 SoC variants from Qualcomm and Apple,
as well as the Renesas r9a07g043f/u chip in both arm64 and riscv variants
While we have occasionally merged support for non-arm SoCs in the past,
this is now the normal path for riscv devicetree files.
The most notable changes, by SoC platform, are:
- The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M2 Ultra)
chips now have initial support. This is particularly nice as I am
typing this on a T6002 Mac Studio with only a small number of driver
patches.
- Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662), SM4250
(Snapdragon 460), SM6375 (Snapdragon 695), SDM670 (Snapdragon 670),
MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon 650) are all mobile
phone chips that are closely related to others we already support.
Adding those helps support more phones and we add several models
from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and Google
(Pixel 3a). There are also new variants of the Herobrine and Trogdor
chromebook motherboards. SA8540P is an automotive SoC used in the
Qdrive-3 development platform
- Rockchips gains no new SoC variants, but a lot of new boards:
three mobile gaming systems based on RK3326 Odroid-Go/rg351 family,
two more Anbernic gaming systems based on RK3566 and a number of
other RK356x based single-board computers.
- Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
the newly added RZ/Five is based on the same design, this now gets
reorganized in order to share most of the dts description between
the two and add the RZ/Five SMARC EVK board support.
Aside from that, there are the usual changes all over the tree:
- New boards on other platforms contain two ASpeed BMC users, two
Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based Kobo
Aura2 ebook reader, two i.MX8 based development boards, two Uniphier
Pro5 development boards, the STM32MP1 testbench board from DHCOR,
the TI K3 based BeagleBone AI-64 board, and the Mediatek Helio X10
based Sony Xperia M5 phone.
- The Starfive JH7100 source gets reorganized in order to support the
VisionFive V1 board.
- Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168,
TI, ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
spear, ... The treewide cleanups now have a lot of fixes for cache
nodes and other binding violoations.
- Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm
and Renesas platforms, adding a lot more on-chip device support
- A rework of the way that DTB overlays are built.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmOSFNQACgkQmmx57+YA
GNnAIg/+KAiUHpSI02V2sQyDXout2laM8fxl8pW4qREQLKV7U+fi74vbd297HSsv
yxOrrvD6aU9QUzWvdYEezqZxUEoOAibEAE3qMaJZrCjzdtmQvIeUJQuNhhg/oGFP
ZcSN8E+60qxsYwfXw9OHp5TTLi5X/ejRmJoPkC/DHbxbpu07YKT0aHf9qoeD8ntM
8Y+qRiC9AYMnK49rw/HSsQIOXKC0tUQrfsavnJGKFE2wUAdD1ZFf34VtMu580USo
eVX++hun/AKKhdU/ZV9xZKUCQTU405SwscGdP5OFtkjNqHCHwdcU10Kp/PxR3XNq
t5Zmfg9PO/OfV17K91t60hkgfZsNojP6mvGwGhYSuIEYKbya3o4YrPJZb/8jd2Vr
QclwN94m53zDTEfhdW4sJ1HGFV8FhQGjQ1PNBuUf2YXIztpuhd4PnCc/R31K4Yr8
O0S2tl/PxUPB2ouHzpuB+4QMGYZjK3OmFNIEZ8tucIuwOeagkZmDUPuq6o1Nj0Je
9XDJVAZf0wFztnbnAKdJkF15Fs8wT8wZLIZOnzy4Zp2HhKHkCKQ0EFSyN37WmM6l
fKktQ/U7sULwrEGSz9cBuYjrq7uOsCnRZD2R6MbB0rs16oHIl4OrVSSzoqYQSTlo
JOAimJJo2mLsslzaKr4TrqhUj9zkrYaWgOLPXD3c4MSLRK/Tqnk=
=WCFd
-----END PGP SIGNATURE-----
Merge tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC DT updates from Arnd Bergmann:
"The devicetree changes contain exactly 1000 non-merge changesets,
including a number of new arm64 SoC variants from Qualcomm and Apple,
as well as the Renesas r9a07g043f/u chip in both arm64 and riscv
variants.
While we have occasionally merged support for non-arm SoCs in the
past, this is now the normal path for riscv devicetree files.
The most notable changes, by SoC platform, are:
- The Apple T6000 (M1 Pro), T6001 (M1 Max) and T6002 (M1 Ultra) chips
now have initial support. This is particularly nice as I am typing
this on a T6002 Mac Studio with only a small number of driver
patches.
- Qualcomm MSM8996 Pro (Snapdragon 821), SM6115 (Snapdragon 662),
SM4250 (Snapdragon 460), SM6375 (Snapdragon 695), SDM670
(Snapdragon 670), MSM8976 (Snapdragon 652) and MSM8956 (Snapdragon
650) are all mobile phone chips that are closely related to others
we already support.
Adding those helps support more phones and we add several models
from Sony (Xperia 10 IV, 5 IV, X, and X compact), OnePlus (One, 3,
3T, and Nord N100), Xiaomi (Poco F1, Mi6), Huawei (Watch) and
Google (Pixel 3a).
There are also new variants of the Herobrine and Trogdor chromebook
motherboards. SA8540P is an automotive SoC used in the Qdrive-3
development platform
- Rockchips gains no new SoC variants, but a lot of new boards: three
mobile gaming systems based on RK3326 Odroid-Go/rg351 family, two
more Anbernic gaming systems based on RK3566 and a number of other
RK356x based single-board computers.
- Renesas RZ/G2UL (r9a07g043) was already supported for arm64, but as
the newly added RZ/Five is based on the same design, this now gets
reorganized in order to share most of the dts description between
the two and add the RZ/Five SMARC EVK board support.
Aside from that, there are the usual changes all over the tree:
- New boards on other platforms contain two ASpeed BMC users, two
Broadcom based Wifi routers, Zyxel NSA310S NAS, the i.MX6 based
Kobo Aura2 ebook reader, two i.MX8 based development boards, two
Uniphier Pro5 development boards, the STM32MP1 testbench board from
DHCOR, the TI K3 based BeagleBone AI-64 board, and the Mediatek
Helio X10 based Sony Xperia M5 phone.
- The Starfive JH7100 source gets reorganized in order to support the
VisionFive V1 board.
- Minor updates and cleanups for Intel SoCFPGA, Marvell PXA168, TI,
ST, NXP, Apple, Broadcom, Juno, Marvell MVEBU, at91, nuvoton,
Tegra, Mediatek, Renesas, Hisilicon, Allwinner, Samsung, ux500,
spear, ... The treewide cleanups now have a lot of fixes for cache
nodes and other binding violoations.
- Somewhat larger sets of reworks for NVIDIA Tegra, Qualcomm and
Renesas platforms, adding a lot more on-chip device support
- A rework of the way that DTB overlays are built"
* tag 'soc-dt-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (979 commits)
arm64: dts: apple: t6002: Fix GPU power domains
arm64: dts: apple: t600x-pmgr: Fix search & replace typo
arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
arm64: dts: apple: Rename dart-sio* to sio-dart*
arch: arm64: apple: t600x: Use standard "iommu" node name
arch: arm64: apple: t8103: Use standard "iommu" node name
ARM: dts: socfpga: Fix pca9548 i2c-mux node name
dt-bindings: iio: adc: qcom,spmi-vadc: fix PM8350 define
dt-bindings: iio: adc: qcom,spmi-vadc: extend example
arm64: dts: qcom: sc8280xp: fix UFS DMA coherency
arm64: dts: qcom: sc7280: Add DT for sc7280-herobrine-zombie
arm64: dts: qcom: sm8250-sony-xperia-edo: fix no-mmc property for SDHCI
arm64: dts: qcom: sdm845-sony-xperia-tama: fix no-mmc property for SDHCI
arm64: dts: qcom: sda660-inforce-ifc6560: fix no-mmc property for SDHCI
arm64: dts: qcom: sa8155p-adp: fix no-mmc property for SDHCI
arm64: dts: qcom: qrb5165-rb: fix no-mmc property for SDHCI
arm64: dts: qcom: sm8450: align MMC node names with dtschema
arm64: dts: qcom: sc7180-trogdor: use generic node names
arm64: dts: qcom: sm8450-hdk: add sound support
arm64: dts: qcom: sm8450: add Soundwire and LPASS
...
This commit is contained in:
Linus Torvalds
commit
01f3cbb296
|
|
@ -20,6 +20,7 @@
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|||
*.dtb
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||||
*.dtbo
|
||||
*.dtb.S
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||||
*.dtbo.S
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||||
*.dwo
|
||||
*.elf
|
||||
*.gcno
|
||||
|
|
|
|||
|
|
@ -163,6 +163,7 @@ properties:
|
|||
- azw,gsking-x
|
||||
- azw,gtking
|
||||
- azw,gtking-pro
|
||||
- hardkernel,odroid-go-ultra
|
||||
- hardkernel,odroid-n2
|
||||
- hardkernel,odroid-n2-plus
|
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- khadas,vim3
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||||
|
|
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|||
|
|
@ -19,12 +19,14 @@ description: |
|
|||
- MacBook Air (M1, 2020)
|
||||
- iMac (24-inch, M1, 2021)
|
||||
|
||||
And devices based on the "M1 Pro" and "M1 Max" SoCs:
|
||||
And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:
|
||||
|
||||
- MacBook Pro (14-inch, M1 Pro, 2021)
|
||||
- MacBook Pro (14-inch, M1 Max, 2021)
|
||||
- MacBook Pro (16-inch, M1 Pro, 2021)
|
||||
- MacBook Pro (16-inch, M1 Max, 2021)
|
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- Mac Studio (M1 Max, 2022)
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- Mac Studio (M1 Ultra, 2022)
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|
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The compatible property should follow this format:
|
||||
|
||||
|
|
@ -67,6 +69,7 @@ properties:
|
|||
- apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
|
||||
- const: apple,t8103
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple M1 Pro SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -74,14 +77,23 @@ properties:
|
|||
- apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
|
||||
- const: apple,t6000
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple M1 Max SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
|
||||
- apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
|
||||
- apple,j375c # Mac Studio (M1 Max, 2022)
|
||||
- const: apple,t6001
|
||||
- const: apple,arm-platform
|
||||
|
||||
- description: Apple M1 Ultra SoC based platforms
|
||||
items:
|
||||
- enum:
|
||||
- apple,j375d # Mac Studio (M1 Ultra, 2022)
|
||||
- const: apple,t6002
|
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- const: apple,arm-platform
|
||||
|
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additionalProperties: true
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||||
|
||||
...
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||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ properties:
|
|||
- description: AST2400 based boards
|
||||
items:
|
||||
- enum:
|
||||
- delta,ahe50dc-bmc
|
||||
- facebook,galaxy100-bmc
|
||||
- facebook,wedge100-bmc
|
||||
- facebook,wedge40-bmc
|
||||
|
|
@ -82,7 +83,7 @@ properties:
|
|||
- ibm,tacoma-bmc
|
||||
- inventec,transformer-bmc
|
||||
- jabil,rbp-bmc
|
||||
- nuvia,dc-scm-bmc
|
||||
- qcom,dc-scm-v1-bmc
|
||||
- quanta,s6q-bmc
|
||||
- const: aspeed,ast2600
|
||||
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@ properties:
|
|||
- enum:
|
||||
- asus,rt-ac88u
|
||||
- dlink,dir-885l
|
||||
- dlink,dir-890l
|
||||
- linksys,panamera
|
||||
- luxul,abr-4500-v1
|
||||
- luxul,xap-1610-v1
|
||||
|
|
@ -97,6 +98,7 @@ properties:
|
|||
- description: BCM53016 based boards
|
||||
items:
|
||||
- enum:
|
||||
- dlink,dwl-8610ap
|
||||
- meraki,mr32
|
||||
- const: brcm,bcm53016
|
||||
- const: brcm,bcm4708
|
||||
|
|
|
|||
|
|
@ -178,11 +178,13 @@ properties:
|
|||
- qcom,kryo250
|
||||
- qcom,kryo260
|
||||
- qcom,kryo280
|
||||
- qcom,kryo360
|
||||
- qcom,kryo385
|
||||
- qcom,kryo468
|
||||
- qcom,kryo485
|
||||
- qcom,kryo560
|
||||
- qcom,kryo570
|
||||
- qcom,kryo660
|
||||
- qcom,kryo685
|
||||
- qcom,kryo780
|
||||
- qcom,scorpion
|
||||
|
|
|
|||
|
|
@ -520,6 +520,7 @@ properties:
|
|||
items:
|
||||
- enum:
|
||||
- fsl,imx6sl-evk # i.MX6 SoloLite EVK Board
|
||||
- kobo,aura2
|
||||
- kobo,tolino-shine2hd
|
||||
- kobo,tolino-shine3
|
||||
- kobo,tolino-vision5
|
||||
|
|
@ -814,6 +815,7 @@ properties:
|
|||
- enum:
|
||||
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
|
||||
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
|
||||
- cloos,imx8mm-phg # i.MX8MM Cloos PHG Board
|
||||
- dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC
|
||||
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
|
||||
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
|
||||
|
|
@ -825,6 +827,7 @@ properties:
|
|||
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
|
||||
- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
|
||||
- innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM
|
||||
- kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM
|
||||
- kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM
|
||||
- menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- mediatek,mt6795-evb
|
||||
- sony,xperia-m5
|
||||
- const: mediatek,mt6795
|
||||
- items:
|
||||
- enum:
|
||||
|
|
@ -83,6 +84,7 @@ properties:
|
|||
- const: mediatek,mt7629
|
||||
- items:
|
||||
- enum:
|
||||
- bananapi,bpi-r3
|
||||
- mediatek,mt7986a-rfb
|
||||
- const: mediatek,mt7986a
|
||||
- items:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/qcom-soc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SoC compatibles naming convention
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
Guidelines for new compatibles for SoC blocks/components.
|
||||
When adding new compatibles in new bindings, use the format::
|
||||
qcom,SoC-IP
|
||||
|
||||
For example::
|
||||
qcom,sdm845-llcc-bwmon
|
||||
|
||||
When adding new compatibles to existing bindings, use the format in the
|
||||
existing binding, even if it contradicts the above.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
# Preferred naming style for compatibles of SoC components:
|
||||
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$"
|
||||
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
|
||||
|
||||
# Legacy namings - variations of existing patterns/compatibles are OK,
|
||||
# but do not add completely new entries to these:
|
||||
- pattern: "^qcom,[ak]pss-wdt-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,gcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,mmcc-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,pcie-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,rpm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- pattern: "^qcom,scm-(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+.*$"
|
||||
- enum:
|
||||
- qcom,dsi-ctrl-6g-qcm2290
|
||||
- qcom,gpucc-sdm630
|
||||
- qcom,gpucc-sdm660
|
||||
- qcom,lcc-apq8064
|
||||
- qcom,lcc-ipq8064
|
||||
- qcom,lcc-mdm9615
|
||||
- qcom,lcc-msm8960
|
||||
- qcom,lpass-cpu-apq8016
|
||||
- qcom,usb-ss-ipq4019-phy
|
||||
- qcom,usb-hs-ipq4019-phy
|
||||
- qcom,vqmmc-ipq4019-regulator
|
||||
|
||||
# Legacy compatibles with wild-cards - list cannot grow with new bindings:
|
||||
- enum:
|
||||
- qcom,ipq806x-gmac
|
||||
- qcom,ipq806x-nand
|
||||
- qcom,ipq806x-sata-phy
|
||||
- qcom,ipq806x-usb-phy-ss
|
||||
- qcom,ipq806x-usb-phy-hs
|
||||
|
||||
additionalProperties: true
|
||||
|
|
@ -29,17 +29,22 @@ description: |
|
|||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
ipq4018
|
||||
ipq6018
|
||||
ipq8074
|
||||
mdm9615
|
||||
msm8226
|
||||
msm8916
|
||||
msm8956
|
||||
msm8974
|
||||
msm8976
|
||||
msm8992
|
||||
msm8994
|
||||
msm8996
|
||||
msm8998
|
||||
qcs404
|
||||
qdu1000
|
||||
qru1000
|
||||
sa8155p
|
||||
sa8540p
|
||||
sc7180
|
||||
|
|
@ -51,11 +56,15 @@ description: |
|
|||
sdm632
|
||||
sdm636
|
||||
sdm660
|
||||
sdm670
|
||||
sdm845
|
||||
sdx55
|
||||
sdx65
|
||||
sm4250
|
||||
sm6115
|
||||
sm6125
|
||||
sm6350
|
||||
sm6375
|
||||
sm7225
|
||||
sm8150
|
||||
sm8250
|
||||
|
|
@ -76,6 +85,7 @@ description: |
|
|||
mtp
|
||||
qrd
|
||||
sbc
|
||||
x100
|
||||
|
||||
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
|
||||
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
|
||||
|
|
@ -114,7 +124,9 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- asus,sparrow
|
||||
- huawei,sturgeon
|
||||
- lg,lenok
|
||||
- samsung,matisse-wifi
|
||||
- const: qcom,apq8026
|
||||
|
||||
- items:
|
||||
|
|
@ -148,6 +160,12 @@ properties:
|
|||
- samsung,s3ve3g
|
||||
- const: qcom,msm8226
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,kugo-row
|
||||
- sony,suzu-row
|
||||
- const: qcom,msm8956
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,msm8960-cdp
|
||||
|
|
@ -155,14 +173,20 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp2
|
||||
- lge,hammerhead
|
||||
- samsung,klte
|
||||
- sony,xperia-amami
|
||||
- sony,xperia-castor
|
||||
- sony,xperia-honami
|
||||
- const: qcom,msm8974
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp2
|
||||
- oneplus,bacon
|
||||
- samsung,klte
|
||||
- sony,xperia-castor
|
||||
- const: qcom,msm8974pro
|
||||
- const: qcom,msm8974
|
||||
|
||||
- items:
|
||||
- const: qcom,msm8916-mtp
|
||||
- const: qcom,msm8916-mtp/1
|
||||
|
|
@ -221,13 +245,20 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- oneplus,oneplus3
|
||||
- oneplus,oneplus3t
|
||||
- qcom,msm8996-mtp
|
||||
- sony,dora-row
|
||||
- sony,kagura-row
|
||||
- sony,keyaki-row
|
||||
- xiaomi,gemini
|
||||
- const: qcom,msm8996
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- xiaomi,natrium
|
||||
- xiaomi,scorpio
|
||||
- const: qcom,msm8996pro
|
||||
- const: qcom,msm8996
|
||||
|
||||
- items:
|
||||
|
|
@ -242,8 +273,15 @@ properties:
|
|||
- sony,xperia-lilac
|
||||
- sony,xperia-maple
|
||||
- sony,xperia-poplar
|
||||
- xiaomi,sagit
|
||||
- const: qcom,msm8998
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- 8dev,jalapeno
|
||||
- alfa-network,ap120c-ac
|
||||
- const: qcom,ipq4018
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq4019-ap-dk01.1-c1
|
||||
|
|
@ -255,6 +293,7 @@ properties:
|
|||
|
||||
- items:
|
||||
- enum:
|
||||
- mikrotik,rb3011
|
||||
- qcom,ipq8064-ap148
|
||||
- const: qcom,ipq8064
|
||||
|
||||
|
|
@ -265,6 +304,25 @@ properties:
|
|||
- qcom,ipq8074-hk10-c2
|
||||
- const: qcom,ipq8074
|
||||
|
||||
- description: Sierra Wireless MangOH Green with WP8548 Module
|
||||
items:
|
||||
- const: swir,mangoh-green-wp8548
|
||||
- const: swir,wp8548
|
||||
- const: qcom,mdm9615
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qdu1000-idp
|
||||
- qcom,qdu1000-x100
|
||||
- const: qcom,qdu1000
|
||||
|
||||
- description: Qualcomm Technologies, Inc. Radio Unit 1000 platform
|
||||
items:
|
||||
- enum:
|
||||
- qcom,qru1000-idp
|
||||
- const: qcom,qru1000
|
||||
|
||||
- description: Qualcomm Technologies, Inc. SC7180 IDP
|
||||
items:
|
||||
- enum:
|
||||
|
|
@ -463,6 +521,17 @@ properties:
|
|||
- const: google,pazquel-sku2
|
||||
- const: qcom,sc7180
|
||||
|
||||
- description: Google Pazquel360 with LTE (newest rev)
|
||||
items:
|
||||
- const: google,pazquel-sku22
|
||||
- const: google,pazquel-sku20
|
||||
- const: qcom,sc7180
|
||||
|
||||
- description: Google Pazquel360 with WiFi (newest rev)
|
||||
items:
|
||||
- const: google,pazquel-sku21
|
||||
- const: qcom,sc7180
|
||||
|
||||
- description: Sharp Dynabook Chromebook C1 (rev1)
|
||||
items:
|
||||
- const: google,pompom-rev1
|
||||
|
|
@ -575,6 +644,11 @@ properties:
|
|||
- const: google,evoker
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Google Evoker with LTE (newest rev)
|
||||
items:
|
||||
- const: google,evoker-sku512
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Google Herobrine (newest rev)
|
||||
items:
|
||||
- const: google,herobrine
|
||||
|
|
@ -595,6 +669,16 @@ properties:
|
|||
- const: google,villager-sku512
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Google Zombie (newest rev)
|
||||
items:
|
||||
- const: google,zombie
|
||||
- const: qcom,sc7280
|
||||
|
||||
- description: Google Zombie with LTE (newest rev)
|
||||
items:
|
||||
- const: google,zombie-sku512
|
||||
- const: qcom,sc7280
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- lenovo,flex-5g
|
||||
|
|
@ -637,6 +721,11 @@ properties:
|
|||
- xiaomi,lavender
|
||||
- const: qcom,sdm660
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,sargo
|
||||
- const: qcom,sdm670
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,sdx55-mtp
|
||||
|
|
@ -670,10 +759,14 @@ properties:
|
|||
- items:
|
||||
- enum:
|
||||
- qcom,sa8295p-adp
|
||||
- qcom,sa8540p-ride
|
||||
- const: qcom,sa8540p
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- google,cheza
|
||||
- google,cheza-rev1
|
||||
- google,cheza-rev2
|
||||
- lenovo,yoga-c630
|
||||
- lg,judyln
|
||||
- lg,judyp
|
||||
|
|
@ -681,15 +774,22 @@ properties:
|
|||
- oneplus,fajita
|
||||
- qcom,sdm845-mtp
|
||||
- shift,axolotl
|
||||
- samsung,starqltechn
|
||||
- samsung,w737
|
||||
- sony,akari-row
|
||||
- sony,akatsuki-row
|
||||
- sony,apollo-row
|
||||
- thundercomm,db845c
|
||||
- xiaomi,beryllium
|
||||
- xiaomi,beryllium-ebbg
|
||||
- xiaomi,polaris
|
||||
- const: qcom,sdm845
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- oneplus,billie2
|
||||
- const: qcom,sm4250
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,pdx201
|
||||
|
|
@ -700,6 +800,11 @@ properties:
|
|||
- sony,pdx213
|
||||
- const: qcom,sm6350
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- sony,pdx225
|
||||
- const: qcom,sm6375
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- fairphone,fp4
|
||||
|
|
@ -737,6 +842,7 @@ properties:
|
|||
- qcom,sm8450-hdk
|
||||
- qcom,sm8450-qrd
|
||||
- sony,pdx223
|
||||
- sony,pdx224
|
||||
- const: qcom,sm8450
|
||||
|
||||
# Board compatibles go above
|
||||
|
|
|
|||
|
|
@ -30,11 +30,26 @@ properties:
|
|||
- const: amarula,vyasa-rk3288
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Anbernic RG351M
|
||||
items:
|
||||
- const: anbernic,rg351m
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Anbernic RG353P
|
||||
items:
|
||||
- const: anbernic,rg353p
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG353V
|
||||
items:
|
||||
- const: anbernic,rg353v
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG353VS
|
||||
items:
|
||||
- const: anbernic,rg353vs
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Anbernic RG503
|
||||
items:
|
||||
- const: anbernic,rg503
|
||||
|
|
@ -468,6 +483,21 @@ properties:
|
|||
- const: hardkernel,rk3326-odroid-go2
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Hardkernel Odroid Go Advance Black Edition
|
||||
items:
|
||||
- const: hardkernel,rk3326-odroid-go2-v11
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Hardkernel Odroid Go Super
|
||||
items:
|
||||
- const: hardkernel,rk3326-odroid-go3
|
||||
- const: rockchip,rk3326
|
||||
|
||||
- description: Hardkernel Odroid M1
|
||||
items:
|
||||
- const: rockchip,rk3568-odroid-m1
|
||||
- const: rockchip,rk3568
|
||||
|
||||
- description: Hugsun X99 TV Box
|
||||
items:
|
||||
- const: hugsun,x99
|
||||
|
|
@ -563,7 +593,9 @@ properties:
|
|||
- description: Pine64 SoQuartz SoM
|
||||
items:
|
||||
- enum:
|
||||
- pine64,soquartz-blade
|
||||
- pine64,soquartz-cm4io
|
||||
- pine64,soquartz-model-a
|
||||
- const: pine64,soquartz
|
||||
- const: rockchip,rk3566
|
||||
|
||||
|
|
@ -709,6 +741,11 @@ properties:
|
|||
- const: rockchip,rv1108-evb
|
||||
- const: rockchip,rv1108
|
||||
|
||||
- description: Theobroma Systems PX30-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,px30-ringneck-haikou
|
||||
- const: rockchip,px30
|
||||
|
||||
- description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
|
||||
items:
|
||||
- const: tsd,rk3368-lion-haikou
|
||||
|
|
@ -729,6 +766,11 @@ properties:
|
|||
- const: zkmagic,a95x-z2
|
||||
- const: rockchip,rk3318
|
||||
|
||||
- description: Rockchip RK3566 BOX Evaluation Demo board
|
||||
items:
|
||||
- const: rockchip,rk3566-box-demo
|
||||
- const: rockchip,rk3566
|
||||
|
||||
- description: Rockchip RK3568 Evaluation board
|
||||
items:
|
||||
- const: rockchip,rk3568-evb1-v10
|
||||
|
|
|
|||
|
|
@ -26,6 +26,12 @@ properties:
|
|||
- socionext,uniphier-pro4-ref
|
||||
- socionext,uniphier-pro4-sanji
|
||||
- const: socionext,uniphier-pro4
|
||||
- description: Pro5 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
- socionext,uniphier-pro5-epcore
|
||||
- socionext,uniphier-pro5-proex
|
||||
- const: socionext,uniphier-pro5
|
||||
- description: sLD8 SoC boards
|
||||
items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -59,6 +59,12 @@ properties:
|
|||
- prt,prtt1s # Protonic PRTT1S
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: DH STM32MP151 DHCOR SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp151a-dhcor-testbench
|
||||
- const: dh,stm32mp151a-dhcor-som
|
||||
- const: st,stm32mp151
|
||||
|
||||
- description: DH STM32MP153 DHCOM SoM based Boards
|
||||
items:
|
||||
- const: dh,stm32mp153c-dhcom-drc02
|
||||
|
|
|
|||
|
|
@ -1,12 +0,0 @@
|
|||
Sierra Wireless Modules device tree bindings
|
||||
--------------------------------------------
|
||||
|
||||
Supported Modules :
|
||||
- WP8548 : Includes MDM9615 and PM8018 in a module
|
||||
|
||||
Sierra Wireless modules shall have the following properties :
|
||||
Required root node property
|
||||
- compatible: "swir,wp8548" for the WP8548 CF3 Module
|
||||
|
||||
Board compatible values:
|
||||
- "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module
|
||||
|
|
@ -61,6 +61,7 @@ properties:
|
|||
- const: ti,j721e
|
||||
- items:
|
||||
- enum:
|
||||
- beagle,j721e-beagleboneai64
|
||||
- ti,j721e-evm
|
||||
- ti,j721e-sk
|
||||
- const: ti,j721e
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/fsl,imx8m-anatop.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP i.MX8M Family Anatop Module
|
||||
|
||||
maintainers:
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
description: |
|
||||
NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- fsl,imx8mm-anatop
|
||||
- fsl,imx8mq-anatop
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8mn-anatop
|
||||
- fsl,imx8mp-anatop
|
||||
- const: fsl,imx8mm-anatop
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
anatop: clock-controller@30360000 {
|
||||
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
|
||||
reg = <0x30360000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -136,7 +136,7 @@ clock@70110000 {
|
|||
};
|
||||
|
||||
/* pinmux nodes added for completeness. Binding doc can be found in:
|
||||
* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.txt
|
||||
* Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml
|
||||
*/
|
||||
|
||||
pinmux: pinmux@700008d4 {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,117 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Apple SoC cluster cpufreq device
|
||||
|
||||
maintainers:
|
||||
- Hector Martin <marcan@marcan.st>
|
||||
|
||||
description: |
|
||||
Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
|
||||
the cluster management register block. This binding uses the standard
|
||||
operating-points-v2 table to define the CPU performance states, with the
|
||||
opp-level property specifying the hardware p-state index for that level.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- apple,t8103-cluster-cpufreq
|
||||
- apple,t8112-cluster-cpufreq
|
||||
- const: apple,cluster-cpufreq
|
||||
- items:
|
||||
- const: apple,t6000-cluster-cpufreq
|
||||
- const: apple,t8103-cluster-cpufreq
|
||||
- const: apple,cluster-cpufreq
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#performance-domain-cells':
|
||||
const: 0
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#performance-domain-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
// This example shows a single CPU per domain and 2 domains,
|
||||
// with two p-states per domain.
|
||||
// Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "apple,icestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x0>;
|
||||
operating-points-v2 = <&ecluster_opp>;
|
||||
performance-domains = <&cpufreq_e>;
|
||||
};
|
||||
|
||||
cpu@10100 {
|
||||
compatible = "apple,firestorm";
|
||||
device_type = "cpu";
|
||||
reg = <0x0 0x10100>;
|
||||
operating-points-v2 = <&pcluster_opp>;
|
||||
performance-domains = <&cpufreq_p>;
|
||||
};
|
||||
};
|
||||
|
||||
ecluster_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <7500>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <972000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <22000>;
|
||||
};
|
||||
};
|
||||
|
||||
pcluster_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
|
||||
opp01 {
|
||||
opp-hz = /bits/ 64 <600000000>;
|
||||
opp-level = <1>;
|
||||
clock-latency-ns = <8000>;
|
||||
};
|
||||
opp02 {
|
||||
opp-hz = /bits/ 64 <828000000>;
|
||||
opp-level = <2>;
|
||||
clock-latency-ns = <19000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpufreq_e: performance-controller@210e20000 {
|
||||
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x10e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
|
||||
cpufreq_p: performance-controller@211e20000 {
|
||||
compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
|
||||
reg = <0x2 0x11e20000 0 0x1000>;
|
||||
#performance-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -56,6 +56,9 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,156 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Device tree binding for NVIDIA Tegra234 NVDEC
|
||||
|
||||
description: |
|
||||
NVDEC is the hardware video decoder present on NVIDIA Tegra210
|
||||
and newer chips. It is located on the Host1x bus and typically
|
||||
programmed through Host1x channels.
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <treding@gmail.com>
|
||||
- Mikko Perttunen <mperttunen@nvidia.com>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "^nvdec@[0-9a-f]*$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra234-nvdec
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: nvdec
|
||||
- const: fuse
|
||||
- const: tsec_pka
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: nvdec
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
dma-coherent: true
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: DMA read memory client
|
||||
- description: DMA write memory client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem
|
||||
- const: write
|
||||
|
||||
nvidia,memory-controller:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the memory controller for determining information for the NVDEC
|
||||
firmware secure carveout. This carveout is configured by the bootloader and
|
||||
not accessible to CPU.
|
||||
|
||||
nvidia,bl-manifest-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to bootloader manifest from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,bl-code-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to bootloader code section from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,bl-data-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to bootloader data section from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,os-manifest-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to operating system manifest from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,os-code-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to operating system code section from beginning of firmware that was configured by
|
||||
the bootloader.
|
||||
|
||||
nvidia,os-data-offset:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Offset to operating system data section from beginning of firmware that was configured
|
||||
by the bootloader.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- power-domains
|
||||
- nvidia,memory-controller
|
||||
- nvidia,bl-manifest-offset
|
||||
- nvidia,bl-code-offset
|
||||
- nvidia,bl-data-offset
|
||||
- nvidia,os-manifest-offset
|
||||
- nvidia,os-code-offset
|
||||
- nvidia,os-data-offset
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra234-clock.h>
|
||||
#include <dt-bindings/memory/tegra234-mc.h>
|
||||
#include <dt-bindings/power/tegra234-powergate.h>
|
||||
#include <dt-bindings/reset/tegra234-reset.h>
|
||||
|
||||
nvdec@15480000 {
|
||||
compatible = "nvidia,tegra234-nvdec";
|
||||
reg = <0x15480000 0x00040000>;
|
||||
clocks = <&bpmp TEGRA234_CLK_NVDEC>,
|
||||
<&bpmp TEGRA234_CLK_FUSE>,
|
||||
<&bpmp TEGRA234_CLK_TSEC_PKA>;
|
||||
clock-names = "nvdec", "fuse", "tsec_pka";
|
||||
resets = <&bpmp TEGRA234_RESET_NVDEC>;
|
||||
reset-names = "nvdec";
|
||||
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
|
||||
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
|
||||
<&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
|
||||
dma-coherent;
|
||||
|
||||
nvidia,memory-controller = <&mc>;
|
||||
|
||||
/* Placeholder values, to be replaced with values from overlay */
|
||||
nvidia,bl-manifest-offset = <0>;
|
||||
nvidia,bl-data-offset = <0>;
|
||||
nvidia,bl-code-offset = <0>;
|
||||
nvidia,os-manifest-offset = <0>;
|
||||
nvidia,os-data-offset = <0>;
|
||||
nvidia,os-code-offset = <0>;
|
||||
};
|
||||
|
|
@ -238,42 +238,72 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
spmi_bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
/* VADC node */
|
||||
pmic_vadc: adc@3100 {
|
||||
compatible = "qcom,spmi-vadc";
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x0 0x31 0x0 0x1>;
|
||||
spmi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
/* VADC node */
|
||||
pmic_vadc: adc@3100 {
|
||||
compatible = "qcom,spmi-vadc";
|
||||
reg = <0x3100>;
|
||||
interrupts = <0x0 0x31 0x0 0x1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
/* Channel node */
|
||||
adc-chan@39 {
|
||||
reg = <0x39>;
|
||||
qcom,decimation = <512>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,avg-samples = <1>;
|
||||
qcom,pre-scaling = <1 3>;
|
||||
};
|
||||
/* Channel node */
|
||||
adc-chan@39 {
|
||||
reg = <0x39>;
|
||||
qcom,decimation = <512>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
qcom,avg-samples = <1>;
|
||||
qcom,pre-scaling = <1 3>;
|
||||
};
|
||||
|
||||
adc-chan@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
adc-chan@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
adc-chan@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
adc-chan@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
adc-chan@e {
|
||||
reg = <0xe>;
|
||||
};
|
||||
adc-chan@e {
|
||||
reg = <0xe>;
|
||||
};
|
||||
|
||||
adc-chan@f {
|
||||
reg = <0xf>;
|
||||
adc-chan@f {
|
||||
reg = <0xf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
|
||||
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
spmi {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
adc@3100 {
|
||||
reg = <0x3100>;
|
||||
compatible = "qcom,spmi-adc7";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#io-channel-cells = <1>;
|
||||
|
||||
/* Other properties are omitted */
|
||||
xo-therm@44 {
|
||||
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
|
||||
conn-therm@47 {
|
||||
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -69,6 +69,35 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
affinities:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description:
|
||||
FIQ affinity can be expressed as a single "affinities" node,
|
||||
containing a set of sub-nodes, one per FIQ with a non-default
|
||||
affinity.
|
||||
patternProperties:
|
||||
"^.+-affinity$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
properties:
|
||||
apple,fiq-index:
|
||||
description:
|
||||
The interrupt number specified as a FIQ, and for which
|
||||
the affinity is not the default.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
maximum: 5
|
||||
|
||||
cpus:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
description:
|
||||
Should be a list of phandles to CPU nodes (as described in
|
||||
Documentation/devicetree/bindings/arm/cpus.yaml).
|
||||
|
||||
required:
|
||||
- apple,fiq-index
|
||||
- cpus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#interrupt-cells'
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ description: |+
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
const: apple,t8103-dart
|
||||
enum:
|
||||
- apple,t8103-dart
|
||||
- apple,t6000-dart
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@ properties:
|
|||
- const: allwinner,sun6i-a31-ir
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,suniv-f1c100s-ir
|
||||
- allwinner,sun8i-a83t-ir
|
||||
- allwinner,sun8i-r40-ir
|
||||
- allwinner,sun50i-a64-ir
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@ properties:
|
|||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,pm6125
|
||||
- qcom,pm6150
|
||||
- qcom,pm6150l
|
||||
- qcom,pm6350
|
||||
|
|
|
|||
|
|
@ -11,14 +11,18 @@ maintainers:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx6q-snvs-lpgpr
|
||||
- fsl,imx6ul-snvs-lpgpr
|
||||
- fsl,imx7d-snvs-lpgpr
|
||||
- fsl,imx8mm-snvs-lpgpr
|
||||
- fsl,imx8mn-snvs-lpgpr
|
||||
- fsl,imx8mp-snvs-lpgpr
|
||||
- fsl,imx8mq-snvs-lpgpr
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx8mm-snvs-lpgpr
|
||||
- fsl,imx8mn-snvs-lpgpr
|
||||
- fsl,imx8mp-snvs-lpgpr
|
||||
- fsl,imx8mq-snvs-lpgpr
|
||||
- const: fsl,imx7d-snvs-lpgpr
|
||||
- enum:
|
||||
- fsl,imx6q-snvs-lpgpr
|
||||
- fsl,imx6ul-snvs-lpgpr
|
||||
- fsl,imx7d-snvs-lpgpr
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ properties:
|
|||
- nvidia,tegra234-pcie
|
||||
|
||||
reg:
|
||||
minItems: 4
|
||||
items:
|
||||
- description: controller's application logic registers
|
||||
- description: configuration registers
|
||||
|
|
@ -35,13 +36,16 @@ properties:
|
|||
available for software access.
|
||||
- description: aperture where the Root Port's own configuration
|
||||
registers are available.
|
||||
- description: aperture to access the configuration space through ECAM.
|
||||
|
||||
reg-names:
|
||||
minItems: 4
|
||||
items:
|
||||
- const: appl
|
||||
- const: config
|
||||
- const: atu_dma
|
||||
- const: dbi
|
||||
- const: ecam
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
|
|
@ -202,6 +206,31 @@ properties:
|
|||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/snps,dw-pcie.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra194-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 4
|
||||
reg-names:
|
||||
maxItems: 4
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- nvidia,tegra234-pcie
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 5
|
||||
reg-names:
|
||||
minItems: 5
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
@ -305,8 +334,9 @@ examples:
|
|||
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
|
||||
<0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
|
||||
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||
<0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi";
|
||||
<0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
|
||||
<0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
|
||||
reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ properties:
|
|||
maxItems: 5
|
||||
items:
|
||||
enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
|
||||
parf, cfg, link, ulreg, smu, mpu, apb, phy ]
|
||||
parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
|
||||
|
||||
num-lanes:
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -0,0 +1,178 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra Pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jonathan Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: |
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of
|
||||
the phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an arbitrary number
|
||||
of subnodes. Each of these subnodes represents some desired configuration
|
||||
for a pin, a group, or a list of pins or groups. This configuration can
|
||||
include the mux function to select on those pin(s)/ group(s), and various
|
||||
pin configuration parameters, such as pull-up, tristate, drive strength,
|
||||
etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be
|
||||
enumerated and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function or tristate parameter. For this
|
||||
reason, even seemingly boolean values are actually tristates in this
|
||||
binding: unspecified, off, or on. Unspecified is represented as an absent
|
||||
property, and off/on are represented as integer values 0 and 1.
|
||||
|
||||
Note that many of these properties are only valid for certain specific pins
|
||||
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
|
||||
details regarding which groups support which functionality. The Linux
|
||||
pinctrl driver may also be a useful reference, since it consolidates,
|
||||
disambiguates, and corrects data from all those sources.
|
||||
|
||||
properties:
|
||||
nvidia,pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: An array of strings. Each string contains the name of a pin
|
||||
or group. Valid values for these names are listed below.
|
||||
|
||||
nvidia,function:
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
description: A string containing the name of the function to mux to the
|
||||
pin or group. Valid values for function names are listed below. See the
|
||||
Tegra TRM to determine which are valid for each pin or group.
|
||||
|
||||
nvidia,pull:
|
||||
description: Pull-down/up setting to apply to the pin.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: none
|
||||
const: 0
|
||||
- description: down
|
||||
const: 1
|
||||
- description: up
|
||||
const: 2
|
||||
|
||||
nvidia,tristate:
|
||||
description: Tristate setting to apply to the pin.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: drive
|
||||
const: 0
|
||||
- description: tristate
|
||||
const: 1
|
||||
|
||||
nvidia,schmitt:
|
||||
description: Enable Schmitt trigger on the input.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: disable Schmitt trigger on the input
|
||||
const: 0
|
||||
- description: enable Schmitt trigger on the input
|
||||
const: 1
|
||||
|
||||
nvidia,pull-down-strength:
|
||||
description: Controls drive strength. 0 is weakest. The range of valid
|
||||
values depends on the pingroup. See "CAL_DRVDN" in the Tegra TRM.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
nvidia,pull-up-strength:
|
||||
description: Controls drive strength. 0 is weakest. The range of valid
|
||||
values depends on the pingroup. See "CAL_DRVUP" in the Tegra TRM.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
nvidia,high-speed-mode:
|
||||
description: Enable high speed mode the pins.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: normal speed mode
|
||||
const: 0
|
||||
- description: high speed mode
|
||||
const: 1
|
||||
|
||||
nvidia,low-power-mode:
|
||||
description: Controls the drive power or current. Valid values are from 0
|
||||
through 3, where 0 specifies the least power and 3 specifies the most
|
||||
power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the Tegra TRM.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
nvidia,enable-input:
|
||||
description: Enable the pin's input path.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: disable input (i.e. output only)
|
||||
const: 0
|
||||
- description: enable input
|
||||
const: 1
|
||||
|
||||
nvidia,open-drain:
|
||||
description: Open-drain configuration for the pin.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: disable open-drain
|
||||
const: 0
|
||||
- description: enable open-drain
|
||||
const: 1
|
||||
|
||||
nvidia,lock:
|
||||
description: Lock the pin configuration against further changes until
|
||||
reset.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: disable pin configuration lock
|
||||
const: 0
|
||||
- description: enable pin configuration lock
|
||||
const: 1
|
||||
|
||||
nvidia,io-reset:
|
||||
description: reset the I/O path
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1 ]
|
||||
|
||||
nvidia,rcv-sel:
|
||||
description: select VIL/VIH receivers
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: normal receivers
|
||||
const: 0
|
||||
- description: high-voltage receivers
|
||||
const: 1
|
||||
|
||||
nvidia,drive-type:
|
||||
description: Drive type to configure for the pin.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
|
||||
nvidia,io-hv:
|
||||
description: Select high-voltage receivers.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
oneOf:
|
||||
- description: Use normal receivers.
|
||||
const: 0
|
||||
- description: Use high-voltage receivers.
|
||||
const: 1
|
||||
|
||||
nvidia,slew-rate-rising:
|
||||
description: Controls rising signal slew rate. 0 is fastest. The range of
|
||||
valid values depends on the pingroup. See "DRVDN_SLWR" in the Tegra TRM.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
nvidia,slew-rate-falling:
|
||||
description: Controls falling signal slew rate. 0 is fastest. The range of
|
||||
valid values depends on the pingroup. See "DRVUP_SLWF" in the Tegra TRM.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
additionalProperties: true
|
||||
...
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
NVIDIA Tegra114 pinmux controller
|
||||
|
||||
The Tegra114 pinctrl binding is very similar to the Tegra20 and Tegra30
|
||||
pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
|
||||
nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
|
||||
a baseline, and only documents the differences between the two bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra114-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the pad control and mux registers. The first bank of address must be the
|
||||
driver strength pad control register address and second bank address must
|
||||
be pinmux register address.
|
||||
|
||||
Tegra114 adds the following optional properties for pin configuration subnodes:
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
|
||||
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset. 0: no, 1: yes.
|
||||
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
|
||||
- nvidia,rcv-sel: Integer. Select VIL/VIH receivers. 0: normal, 1: high.
|
||||
- nvidia,drive-type: Integer. Valid range 0...3.
|
||||
|
||||
As with Tegra20 and Terga30, see the Tegra TRM for complete details regarding
|
||||
which groups support which functionality.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
per-pin mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, nvidia,pull,
|
||||
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
|
||||
nvidia,io-reset and nvidia,rcv-sel.
|
||||
|
||||
ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
|
||||
ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
|
||||
ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
|
||||
dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
|
||||
sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
|
||||
sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
|
||||
ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
|
||||
uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
|
||||
uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_sda_pc5,
|
||||
gen1_i2c_scl_pc4, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7,
|
||||
clk3_out_pee0, clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
|
||||
gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, gmi_cs2_n_pk3,
|
||||
gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, gmi_cs7_n_pi6, gmi_ad0_pg0,
|
||||
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
|
||||
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
|
||||
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
|
||||
gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, gmi_a19_pk7, gmi_wr_n_pi0,
|
||||
gmi_oe_n_pi1, gmi_dqs_p_pj3, gmi_rst_n_pi4, gen2_i2c_scl_pt5,
|
||||
gen2_i2c_sda_pt6, sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
|
||||
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
|
||||
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, cam_mclk_pcc0,
|
||||
pcc1, pbb0, cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
|
||||
pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1,
|
||||
kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6,
|
||||
kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_col0_pq0,
|
||||
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
|
||||
kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, core_pwr_req,
|
||||
cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
|
||||
dap1_sclk_pn3, clk1_req_pee2, clk1_out_pw4, spdif_in_pk6, spdif_out_pk5,
|
||||
dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
|
||||
gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, gpio_x4_aud_px4,
|
||||
gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7, sdmmc3_clk_pa6,
|
||||
sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
|
||||
gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, usb_vbus_en1_pn5,
|
||||
sdmmc3_clk_lb_in_pee5, sdmmc3_clk_lb_out_pee4, reset_out_n.
|
||||
|
||||
drive groups:
|
||||
|
||||
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
|
||||
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
|
||||
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
|
||||
and nvidia,drive-type.
|
||||
|
||||
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
|
||||
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
|
||||
gmh, owr, uda.
|
||||
|
||||
Valid values for nvidia,functions are:
|
||||
|
||||
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
|
||||
displaya_alt, displayb, dtv, emc_dll, extperiph1, extperiph2,
|
||||
extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr,
|
||||
i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, nand, nand_alt, owr, pmi,
|
||||
pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, rsvd2, rsvd3,
|
||||
rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3,
|
||||
spi4, spi5, spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi,
|
||||
usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3
|
||||
|
||||
Example:
|
||||
|
||||
pinmux: pinmux {
|
||||
compatible = "nvidia,tegra114-pinmux";
|
||||
reg = <0x70000868 0x148 /* Pad control registers */
|
||||
0x70003000 0x40c>; /* PinMux registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl {
|
||||
sdmmc4_default: pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc4_default>;
|
||||
};
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra114 pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra114-pinmux
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: pad control registers
|
||||
- description: mux registers
|
||||
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
# pin groups
|
||||
additionalProperties:
|
||||
$ref: nvidia,tegra-pinmux-common.yaml
|
||||
additionalProperties: false
|
||||
properties:
|
||||
nvidia,pins:
|
||||
items:
|
||||
enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
|
||||
ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
|
||||
ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
|
||||
ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
|
||||
dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
|
||||
sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
|
||||
sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
|
||||
clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
|
||||
uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
|
||||
uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
|
||||
uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
|
||||
pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4,
|
||||
dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
|
||||
clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7,
|
||||
gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2,
|
||||
gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3,
|
||||
gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
|
||||
gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
|
||||
gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
|
||||
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
|
||||
gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1,
|
||||
gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3,
|
||||
gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
|
||||
sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
|
||||
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
|
||||
sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
|
||||
sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
|
||||
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
|
||||
pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0,
|
||||
kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4,
|
||||
kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0,
|
||||
kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1,
|
||||
kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
|
||||
kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5,
|
||||
core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0,
|
||||
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2,
|
||||
clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2,
|
||||
dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
|
||||
gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
|
||||
gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
|
||||
gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
|
||||
sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
|
||||
sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3,
|
||||
usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5,
|
||||
sdmmc3_clk_lb_out_pee4, reset_out_n,
|
||||
# drive groups
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
|
||||
drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
|
||||
drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
|
||||
drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
|
||||
drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
|
||||
drive_gmg, drive_gmh, drive_owr, drive_uda ]
|
||||
|
||||
nvidia,function:
|
||||
enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
|
||||
displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1,
|
||||
extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
|
||||
i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
|
||||
nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron,
|
||||
reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2,
|
||||
sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5,
|
||||
spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb,
|
||||
vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ]
|
||||
|
||||
nvidia,pull: true
|
||||
nvidia,tristate: true
|
||||
nvidia,schmitt: true
|
||||
nvidia,pull-down-strength: true
|
||||
nvidia,pull-up-strength: true
|
||||
nvidia,high-speed-mode: true
|
||||
nvidia,low-power-mode: true
|
||||
nvidia,enable-input: true
|
||||
nvidia,open-drain: true
|
||||
nvidia,lock: true
|
||||
nvidia,io-reset: true
|
||||
nvidia,rcv-sel: true
|
||||
nvidia,drive-type: true
|
||||
nvidia,slew-rate-rising: true
|
||||
nvidia,slew-rate-falling: true
|
||||
|
||||
required:
|
||||
- nvidia,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
pinmux@70000868 {
|
||||
compatible = "nvidia,tegra114-pinmux";
|
||||
reg = <0x70000868 0x148>, /* Pad control registers */
|
||||
<0x70003000 0x40c>; /* PinMux registers */
|
||||
|
||||
pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,153 +0,0 @@
|
|||
NVIDIA Tegra124 pinmux controller
|
||||
|
||||
The Tegra124 pinctrl binding is very similar to the Tegra20 and Tegra30
|
||||
pinctrl binding, as described in nvidia,tegra20-pinmux.txt and
|
||||
nvidia,tegra30-pinmux.txt. In fact, this document assumes that binding as
|
||||
a baseline, and only documents the differences between the two bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: For Tegra124, must contain "nvidia,tegra124-pinmux". For
|
||||
Tegra132, must contain '"nvidia,tegra132-pinmux", "nvidia-tegra124-pinmux"'.
|
||||
- reg: Should contain a list of base address and size pairs for:
|
||||
-- first entry - the drive strength and pad control registers.
|
||||
-- second entry - the pinmux registers
|
||||
-- third entry - the MIPI_PAD_CTRL register
|
||||
|
||||
Tegra124 adds the following optional properties for pin configuration subnodes.
|
||||
The macros for options are defined in the
|
||||
include/dt-binding/pinctrl/pinctrl-tegra.h.
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path.
|
||||
enable :TEGRA_PIN_ENABLE and
|
||||
disable or output only: TEGRA_PIN_DISABLE.
|
||||
- nvidia,open-drain: Integer.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,io-reset: Integer. Reset the IO path.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,rcv-sel: Integer. Select VIL/VIH receivers.
|
||||
normal: TEGRA_PIN_DISABLE
|
||||
high: TEGRA_PIN_ENABLE
|
||||
|
||||
Please refer the Tegra TRM for complete details regarding which groups
|
||||
support which functionality.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
per-pin mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, nvidia,pull,
|
||||
nvidia,enable-input. Some support nvidia,lock nvidia,open-drain,
|
||||
nvidia,io-reset and nvidia,rcv-sel.
|
||||
|
||||
ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, ulpi_data3_po4,
|
||||
ulpi_data4_po5, ulpi_data5_po6, ulpi_data6_po7, ulpi_data7_po0,
|
||||
ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0,
|
||||
dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
|
||||
sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6,
|
||||
sdmmc1_dat0_py7, clk2_out_pw5, clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4,
|
||||
ddc_sda_pv5, uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
|
||||
uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, uart3_cts_n_pa1,
|
||||
uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, pu5, pu6, gen1_i2c_scl_pc4,
|
||||
gen1_i2c_sda_pc5, dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6,
|
||||
dap4_sclk_pp7, clk3_out_pee0, clk3_req_pee1, pc7, pi5, pi7, pk0, pk1,
|
||||
pj0, pj2, pk3, pk4, pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6,
|
||||
pg7, ph0, ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
|
||||
pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, sdmmc4_clk_pcc4,
|
||||
sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, sdmmc4_dat2_paa2,
|
||||
sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
|
||||
sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, cam_i2c_scl_pbb1,
|
||||
cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7, pcc2, jtag_rtck,
|
||||
pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
|
||||
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
|
||||
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
|
||||
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, kb_col0_pq0, kb_col1_pq1,
|
||||
kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, kb_col6_pq6,
|
||||
kb_col7_pq7, clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
|
||||
clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
|
||||
dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, spdif_in_pk6,
|
||||
spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3,
|
||||
dvfs_pwm_px0, gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
|
||||
gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, gpio_x7_aud_px7,
|
||||
sdmmc3_clk_pa6, sdmmc3_cmd_pa7, sdmmc3_dat0_pb7, sdmmc3_dat1_pb6,
|
||||
sdmmc3_dat2_pb5, sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1,
|
||||
pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, pex_l1_rst_n_pdd5,
|
||||
pex_l1_clkreq_n_pdd6, hdmi_cec_pee3, sdmmc1_wp_n_pv3,
|
||||
sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
|
||||
usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, sdmmc3_clk_lb_in_pee5,
|
||||
gmi_clk_lb, reset_out_n, kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1,
|
||||
pff2, dp_hpd_pff0,
|
||||
|
||||
drive groups:
|
||||
|
||||
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
|
||||
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
|
||||
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode
|
||||
and nvidia,drive-type.
|
||||
|
||||
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, dap1, dap2, dap3, dap4,
|
||||
dbg, sdio3, spi, uaa, uab, uart2, uart3, sdio1, ddc, gma, gme, gmf, gmg,
|
||||
gmh, owr, uda, gpv, dev3, cec, usb_vbus_en, ao3, ao0, hv0, sdio4, ao4.
|
||||
|
||||
MIPI pad control groups:
|
||||
|
||||
These support only the nvidia,function property.
|
||||
|
||||
dsi_b
|
||||
|
||||
Valid values for nvidia,functions are:
|
||||
|
||||
blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, displaya,
|
||||
displaya_alt, displayb, dtv, extperiph1, extperiph2, extperiph3,
|
||||
gmi, gmi_alt, hda, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0,
|
||||
i2s1, i2s2, i2s3, i2s4, irda, kbc, owr, pmi, pwm0, pwm1, pwm2, pwm3,
|
||||
pwron, reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3,
|
||||
sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
|
||||
uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
|
||||
vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, pe0, pe, pe1,
|
||||
dp, rtck, sys, clk tmds, csi, dsi_b
|
||||
|
||||
Example:
|
||||
|
||||
pinmux: pinmux {
|
||||
compatible = "nvidia,tegra124-pinmux";
|
||||
reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
|
||||
<0x0 0x70003000 0x0 0x434>, /* Mux registers */
|
||||
<0x0 0x70000820 0x0 0x8>; /* MIPI pad control */
|
||||
};
|
||||
|
||||
Example pinmux entries:
|
||||
|
||||
pinctrl {
|
||||
sdmmc4_default: pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc4_default>;
|
||||
};
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra124 Pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The Tegra124 pinctrl binding is very similar to the Tegra20 and
|
||||
Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and
|
||||
nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a
|
||||
baseline, and only documents the differences between the two bindings.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: nvidia,tegra124-pinmux
|
||||
- items:
|
||||
- const: nvidia,tegra132-pinmux
|
||||
- const: nvidia,tegra124-pinmux
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: driver strength and pad control registers
|
||||
- description: pinmux registers
|
||||
- description: MIPI_PAD_CTRL registers
|
||||
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
# pin groups
|
||||
additionalProperties:
|
||||
$ref: nvidia,tegra-pinmux-common.yaml
|
||||
additionalProperties: false
|
||||
properties:
|
||||
nvidia,pins:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
items:
|
||||
enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3,
|
||||
ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
|
||||
ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1,
|
||||
ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1,
|
||||
dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0,
|
||||
sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5,
|
||||
sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5,
|
||||
clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5,
|
||||
uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6,
|
||||
uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7,
|
||||
uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4,
|
||||
pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4,
|
||||
dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0,
|
||||
clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4,
|
||||
pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0,
|
||||
ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0,
|
||||
pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
|
||||
sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0,
|
||||
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3,
|
||||
sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6,
|
||||
sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0,
|
||||
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
|
||||
pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7,
|
||||
kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3,
|
||||
kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
|
||||
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3,
|
||||
kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7,
|
||||
kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3,
|
||||
kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7,
|
||||
clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n,
|
||||
clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2,
|
||||
dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4,
|
||||
spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4,
|
||||
dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0,
|
||||
gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2,
|
||||
gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6,
|
||||
gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7,
|
||||
sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
|
||||
pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6,
|
||||
hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2,
|
||||
gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4,
|
||||
usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4,
|
||||
sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n,
|
||||
kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2,
|
||||
dp_hpd_pff0,
|
||||
# drive groups
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
|
||||
drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1,
|
||||
drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3,
|
||||
drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
|
||||
drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf,
|
||||
drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv,
|
||||
drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3,
|
||||
drive_ao0, drive_hv0, drive_sdio4, drive_ao4,
|
||||
# MIPI pad control groups
|
||||
mipi_pad_ctrl_dsi_b ]
|
||||
|
||||
nvidia,function:
|
||||
enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3,
|
||||
displaya, displaya_alt, displayb, dtv, extperiph1,
|
||||
extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2,
|
||||
i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc,
|
||||
owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1,
|
||||
rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc,
|
||||
spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta,
|
||||
uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
|
||||
vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla,
|
||||
pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ]
|
||||
|
||||
nvidia,pull: true
|
||||
nvidia,tristate: true
|
||||
nvidia,schmitt: true
|
||||
nvidia,pull-down-strength: true
|
||||
nvidia,pull-up-strength: true
|
||||
nvidia,high-speed-mode: true
|
||||
nvidia,low-power-mode: true
|
||||
nvidia,enable-input: true
|
||||
nvidia,open-drain: true
|
||||
nvidia,lock: true
|
||||
nvidia,io-reset: true
|
||||
nvidia,rcv-sel: true
|
||||
nvidia,drive-type: true
|
||||
nvidia,slew-rate-rising: true
|
||||
nvidia,slew-rate-falling: true
|
||||
|
||||
required:
|
||||
- nvidia,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
|
||||
pinmux@70000868 {
|
||||
compatible = "nvidia,tegra124-pinmux";
|
||||
reg = <0x70000868 0x164>, /* Pad control registers */
|
||||
<0x70003000 0x434>, /* Mux registers */
|
||||
<0x70000820 0x8>; /* MIPI pad control */
|
||||
|
||||
sdmmc4_default: pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
NVIDIA Tegra194 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra194-pinmux"
|
||||
- reg: Should contain a list of base address and size pairs for:
|
||||
- first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
|
||||
- second entry: The PINMUX_AUX_* registers (pinmux)
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, tristate, drive strength, etc.
|
||||
|
||||
See the TRM to determine which properties and values apply to each pin/group.
|
||||
Macro values for property values are defined in
|
||||
include/dt-binding/pinctrl/pinctrl-tegra.h.
|
||||
|
||||
Required subnode-properties:
|
||||
- nvidia,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- nvidia,function: A string containing the name of the function to mux to the
|
||||
pin or group.
|
||||
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
|
||||
0: none, 1: down, 2: up.
|
||||
- nvidia,tristate: Integer.
|
||||
0: drive, 1: tristate.
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path.
|
||||
enable :TEGRA_PIN_ENABLE and
|
||||
disable or output only: TEGRA_PIN_DISABLE.
|
||||
- nvidia,open-drain: Integer.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,io-hv: Integer. Select high-voltage receivers.
|
||||
normal: TEGRA_PIN_DISABLE
|
||||
high: TEGRA_PIN_ENABLE
|
||||
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
|
||||
normal: TEGRA_PIN_DISABLE
|
||||
high: TEGRA_PIN_ENABLE
|
||||
- nvidia,drive-type: Integer. Valid range 0...3.
|
||||
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
|
||||
Tegra TRM.
|
||||
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
|
||||
Tegra TRM.
|
||||
|
||||
Valid values for pin and group names (nvidia,pin) are:
|
||||
|
||||
These correspond to Tegra PADCTL_* (pinmux) registers.
|
||||
|
||||
Mux groups:
|
||||
|
||||
These correspond to Tegra PADCTL_* (pinmux) registers. Any property
|
||||
that exists in those registers may be set for the following pin names.
|
||||
|
||||
pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
|
||||
|
||||
Drive groups:
|
||||
|
||||
These registers controls a single pin for which a mux group exists.
|
||||
See the list above for the pin name to use when configuring the pinmux.
|
||||
|
||||
pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
|
||||
|
||||
Valid values for nvidia,functions are:
|
||||
|
||||
pe5
|
||||
|
||||
Power Domain:
|
||||
pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 are part of PCIE C5 power
|
||||
partition. Client devices must enable this partition before accessing
|
||||
these pins here.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
tegra_pinctrl: pinmux: pinmux@2430000 {
|
||||
compatible = "nvidia,tegra194-pinmux";
|
||||
reg = <0x2430000 0x17000
|
||||
0xc300000 0x4000>;
|
||||
|
||||
pinctrl-names = "pex_rst";
|
||||
pinctrl-0 = <&pex_rst_c5_out_state>;
|
||||
|
||||
pex_rst_c5_out_state: pex_rst_c5_out {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l5_rst_n_pgg1";
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,284 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 Pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nvidia,tegra194-pinmux
|
||||
- nvidia,tegra194-pinmux-aon
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: pinmux registers
|
||||
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
# pin groups
|
||||
additionalProperties:
|
||||
$ref: nvidia,tegra-pinmux-common.yaml
|
||||
unevaluatedProperties: false
|
||||
properties:
|
||||
nvidia,function:
|
||||
enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1,
|
||||
displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp,
|
||||
dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3,
|
||||
extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8,
|
||||
i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi,
|
||||
nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0,
|
||||
rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs,
|
||||
soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc,
|
||||
uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
|
||||
vgp6, wdt ]
|
||||
|
||||
nvidia,pull: true
|
||||
nvidia,tristate: true
|
||||
nvidia,schmitt: true
|
||||
nvidia,enable-input: true
|
||||
nvidia,open-drain: true
|
||||
nvidia,lock: true
|
||||
nvidia,drive-type: true
|
||||
nvidia,io-hv: true
|
||||
|
||||
required:
|
||||
- nvidia,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-pinmux
|
||||
then:
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
additionalProperties:
|
||||
properties:
|
||||
nvidia,pins:
|
||||
description: An array of strings. Each string contains the name
|
||||
of a pin or group. Valid values for these names are listed
|
||||
below.
|
||||
|
||||
Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins
|
||||
are part of PCIE C5 power partition. Client devices must
|
||||
enable this partition before accessing the configuration for
|
||||
these pins.
|
||||
items:
|
||||
enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2,
|
||||
dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5,
|
||||
dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0,
|
||||
cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1,
|
||||
qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4,
|
||||
qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7,
|
||||
qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2,
|
||||
qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1,
|
||||
eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4,
|
||||
eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7,
|
||||
eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2,
|
||||
eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5,
|
||||
soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2,
|
||||
soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5,
|
||||
soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0,
|
||||
soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3,
|
||||
uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6,
|
||||
dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1,
|
||||
dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4,
|
||||
sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2,
|
||||
sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5,
|
||||
pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1,
|
||||
pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3,
|
||||
pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5,
|
||||
pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7,
|
||||
pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1,
|
||||
pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0,
|
||||
dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2,
|
||||
dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5,
|
||||
soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0,
|
||||
soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0,
|
||||
sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3,
|
||||
sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0,
|
||||
extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3,
|
||||
soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6,
|
||||
soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1,
|
||||
soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4,
|
||||
soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7,
|
||||
soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2,
|
||||
uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5,
|
||||
dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2,
|
||||
dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5,
|
||||
soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0,
|
||||
dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3,
|
||||
dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6,
|
||||
dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0,
|
||||
directdc1_in_pv1, directdc1_out0_pv2,
|
||||
directdc1_out1_pv3, directdc1_out2_pv4,
|
||||
directdc1_out3_pv5, directdc1_out4_pv6,
|
||||
directdc1_out5_pv7, directdc1_out6_pw0,
|
||||
directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1,
|
||||
gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5,
|
||||
uart2_rts_px6, uart2_cts_px7, spi3_sck_py0,
|
||||
spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3,
|
||||
spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6,
|
||||
uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1,
|
||||
usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4,
|
||||
spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7,
|
||||
ufs0_ref_clk_pff0, ufs0_rst_pff1,
|
||||
pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1,
|
||||
directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs,
|
||||
sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4,
|
||||
sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0,
|
||||
sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp,
|
||||
sdmmc3_hv_trim, eqos_comp, qspi_comp,
|
||||
# drive groups
|
||||
drive_soc_gpio33_pt0, drive_soc_gpio32_ps7,
|
||||
drive_soc_gpio31_ps6, drive_soc_gpio30_ps5,
|
||||
drive_aud_mclk_ps4, drive_dap1_fs_ps3,
|
||||
drive_dap1_din_ps2, drive_dap1_dout_ps1,
|
||||
drive_dap1_sclk_ps0, drive_dap3_fs_pt4,
|
||||
drive_dap3_din_pt3, drive_dap3_dout_pt2,
|
||||
drive_dap3_sclk_pt1, drive_dap5_fs_pu0,
|
||||
drive_dap5_din_pt7, drive_dap5_dout_pt6,
|
||||
drive_dap5_sclk_pt5, drive_dap6_fs_pa3,
|
||||
drive_dap6_din_pa2, drive_dap6_dout_pa1,
|
||||
drive_dap6_sclk_pa0, drive_dap4_fs_pa7,
|
||||
drive_dap4_din_pa6, drive_dap4_dout_pa5,
|
||||
drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1,
|
||||
drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3,
|
||||
drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4,
|
||||
drive_soc_gpio41_pq5, drive_soc_gpio42_pq6,
|
||||
drive_soc_gpio43_pq7, drive_soc_gpio44_pr0,
|
||||
drive_soc_gpio45_pr1, drive_soc_gpio20_pq0,
|
||||
drive_soc_gpio21_pq1, drive_soc_gpio22_pq2,
|
||||
drive_soc_gpio23_pq3, drive_soc_gpio04_pp4,
|
||||
drive_soc_gpio05_pp5, drive_soc_gpio06_pp6,
|
||||
drive_soc_gpio07_pp7, drive_uart1_cts_pr5,
|
||||
drive_uart1_rts_pr4, drive_uart1_rx_pr3,
|
||||
drive_uart1_tx_pr2, drive_dap2_din_pi1,
|
||||
drive_dap2_dout_pi0, drive_dap2_fs_pi2,
|
||||
drive_dap2_sclk_ph7, drive_uart4_cts_ph6,
|
||||
drive_uart4_rts_ph5, drive_uart4_rx_ph4,
|
||||
drive_uart4_tx_ph3, drive_soc_gpio03_pg3,
|
||||
drive_soc_gpio02_pg2, drive_soc_gpio01_pg1,
|
||||
drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3,
|
||||
drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4,
|
||||
drive_soc_gpio09_pg5, drive_soc_gpio10_pg6,
|
||||
drive_soc_gpio11_pg7, drive_soc_gpio12_ph0,
|
||||
drive_soc_gpio13_ph1, drive_soc_gpio14_ph2,
|
||||
drive_soc_gpio50_pm5, drive_soc_gpio51_pm6,
|
||||
drive_soc_gpio52_pm7, drive_soc_gpio53_pn0,
|
||||
drive_soc_gpio54_pn1, drive_soc_gpio55_pn2,
|
||||
drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1,
|
||||
drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3,
|
||||
drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4,
|
||||
drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2,
|
||||
drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0,
|
||||
drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5,
|
||||
drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7,
|
||||
drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1,
|
||||
drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0,
|
||||
drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1,
|
||||
drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0,
|
||||
drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5,
|
||||
drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3,
|
||||
drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5,
|
||||
drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3,
|
||||
drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1,
|
||||
drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0,
|
||||
drive_spi3_miso_py1, drive_spi1_cs0_pz6,
|
||||
drive_spi3_cs0_py3, drive_spi1_miso_pz4,
|
||||
drive_spi3_cs1_py4, drive_gp_pwm3_px3,
|
||||
drive_gp_pwm2_px2, drive_spi1_sck_pz3,
|
||||
drive_spi3_sck_py0, drive_spi1_cs1_pz7,
|
||||
drive_spi1_mosi_pz5, drive_spi3_mosi_py2,
|
||||
drive_cv_pwr_req_px1, drive_uart2_tx_px4,
|
||||
drive_uart2_rx_px5, drive_uart2_rts_px6,
|
||||
drive_uart2_cts_px7, drive_uart5_rx_py6,
|
||||
drive_uart5_tx_py5, drive_uart5_rts_py7,
|
||||
drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1,
|
||||
drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1,
|
||||
drive_ufs0_ref_clk_pff0 ]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-pinmux-aon
|
||||
then:
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
additionalProperties:
|
||||
properties:
|
||||
nvidia,pins:
|
||||
items:
|
||||
enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2,
|
||||
can0_din_paa3, can0_stb_paa4, can0_en_paa5,
|
||||
can0_wake_paa6, can0_err_paa7, can1_stb_pbb0,
|
||||
can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3,
|
||||
spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2,
|
||||
spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5,
|
||||
uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0,
|
||||
gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2,
|
||||
safe_state_pee0, vcomp_alert_pee1,
|
||||
ao_retention_n_pee2, batt_oc_pee3, power_on_pee4,
|
||||
pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n,
|
||||
shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in,
|
||||
# drive groups
|
||||
drive_shutdown_n, drive_pmu_int_n,
|
||||
drive_safe_state_pee0, drive_vcomp_alert_pee1,
|
||||
drive_soc_pwr_req, drive_batt_oc_pee3,
|
||||
drive_clk_32k_in, drive_power_on_pee4,
|
||||
drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6,
|
||||
drive_ao_retention_n_pee2, drive_touch_clk_pcc4,
|
||||
drive_uart3_rx_pcc6, drive_uart3_tx_pcc5,
|
||||
drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1,
|
||||
drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7,
|
||||
drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0,
|
||||
drive_spi2_sck_pcc0, drive_spi2_miso_pcc1,
|
||||
drive_can1_dout_paa0, drive_can1_din_paa1,
|
||||
drive_can0_dout_paa2, drive_can0_din_paa3,
|
||||
drive_can0_stb_paa4, drive_can0_en_paa5,
|
||||
drive_can0_wake_paa6, drive_can0_err_paa7,
|
||||
drive_can1_stb_pbb0, drive_can1_en_pbb1,
|
||||
drive_can1_wake_pbb2, drive_can1_err_pbb3 ]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
|
||||
pinmux@2430000 {
|
||||
compatible = "nvidia,tegra194-pinmux";
|
||||
reg = <0x2430000 0x17000>;
|
||||
|
||||
pinctrl-names = "pex_rst";
|
||||
pinctrl-0 = <&pex_rst_c5_out_state>;
|
||||
|
||||
pex_rst_c5_out_state: pinmux-pex-rst-c5-out {
|
||||
pex_rst {
|
||||
nvidia,pins = "pex_l5_rst_n_pgg1";
|
||||
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,143 +0,0 @@
|
|||
NVIDIA Tegra20 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra20-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the tri-state, mux, pull-up/down, and pad control register sets.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, tristate, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function or tristate parameter. For this
|
||||
reason, even seemingly boolean values are actually tristates in this binding:
|
||||
unspecified, off, or on. Unspecified is represented as an absent property,
|
||||
and off/on are represented as integer values 0 and 1.
|
||||
|
||||
Required subnode-properties:
|
||||
- nvidia,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- nvidia,function: A string containing the name of the function to mux to the
|
||||
pin or group. Valid values for function names are listed below. See the Tegra
|
||||
TRM to determine which are valid for each pin or group.
|
||||
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
|
||||
0: none, 1: down, 2: up.
|
||||
- nvidia,tristate: Integer.
|
||||
0: drive, 1: tristate.
|
||||
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
|
||||
0: no, 1: yes.
|
||||
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
|
||||
0: no, 1: yes.
|
||||
- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
|
||||
most power. Controls the drive power or current. See "Low Power Mode"
|
||||
or "LPMD1" and "LPMD0" in the Tegra TRM.
|
||||
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
|
||||
Tegra TRM.
|
||||
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
|
||||
Tegra TRM.
|
||||
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVDN_SLWR" in the Tegra TRM.
|
||||
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVUP_SLWF" in the Tegra TRM.
|
||||
|
||||
Note that many of these properties are only valid for certain specific pins
|
||||
or groups. See the Tegra TRM and various pinmux spreadsheets for complete
|
||||
details regarding which groups support which functionality. The Linux pinctrl
|
||||
driver may also be a useful reference, since it consolidates, disambiguates,
|
||||
and corrects data from all those sources.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, and many support
|
||||
nvidia,pull.
|
||||
|
||||
ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
|
||||
ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
|
||||
gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
|
||||
ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
|
||||
ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
|
||||
lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
|
||||
owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
|
||||
spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
|
||||
uca, ucb, uda.
|
||||
|
||||
tristate groups:
|
||||
|
||||
These only support nvidia,pull.
|
||||
|
||||
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
|
||||
ld19_18, ld21_20, ld23_22.
|
||||
|
||||
drive groups:
|
||||
|
||||
With some exceptions, these support nvidia,high-speed-mode,
|
||||
nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
|
||||
nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
|
||||
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
|
||||
drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
|
||||
drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
|
||||
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
|
||||
drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
|
||||
drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
|
||||
drive_uda.
|
||||
|
||||
Valid values for nvidia,functions are:
|
||||
|
||||
ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5,
|
||||
displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int,
|
||||
hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
|
||||
osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3,
|
||||
pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck,
|
||||
sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt,
|
||||
spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
|
||||
vi, vi_sensor_clk, xio
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra20-pinmux";
|
||||
reg = < 0x70000014 0x10 /* Tri-state registers */
|
||||
0x70000080 0x20 /* Mux registers */
|
||||
0x700000a0 0x14 /* Pull-up/down registers */
|
||||
0x70000868 0xa8 >; /* Pad control registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl@70000000 {
|
||||
sdio4_default: sdio4_default {
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@c8000600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio4_default>;
|
||||
};
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra20 Pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra20-pinmux
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: tri-state registers
|
||||
- description: mux register
|
||||
- description: pull-up/down registers
|
||||
- description: pad control registers
|
||||
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
# pin groups
|
||||
additionalProperties:
|
||||
$ref: nvidia,tegra-pinmux-common.yaml
|
||||
additionalProperties: false
|
||||
properties:
|
||||
nvidia,pins:
|
||||
items:
|
||||
enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1,
|
||||
dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma,
|
||||
gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx,
|
||||
irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1,
|
||||
ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12,
|
||||
ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2,
|
||||
lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck,
|
||||
lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb,
|
||||
sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia,
|
||||
spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac,
|
||||
uad, uca, ucb, uda,
|
||||
# tristate groups
|
||||
ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls,
|
||||
lc, ld17_0, ld19_18, ld21_20, ld23_22,
|
||||
# drive groups
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1,
|
||||
drive_cdev2, drive_csus, drive_dap1, drive_dap2,
|
||||
drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2,
|
||||
drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
|
||||
drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2,
|
||||
drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk,
|
||||
drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb,
|
||||
drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ]
|
||||
|
||||
nvidia,function:
|
||||
enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4,
|
||||
dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi,
|
||||
gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio,
|
||||
mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1,
|
||||
pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr,
|
||||
pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2,
|
||||
sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3,
|
||||
spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
|
||||
vi, vi_sensor_clk, xio ]
|
||||
|
||||
nvidia,pull: true
|
||||
nvidia,tristate: true
|
||||
nvidia,schmitt: true
|
||||
nvidia,pull-down-strength: true
|
||||
nvidia,pull-up-strength: true
|
||||
nvidia,high-speed-mode: true
|
||||
nvidia,low-power-mode: true
|
||||
nvidia,slew-rate-rising: true
|
||||
nvidia,slew-rate-falling: true
|
||||
|
||||
required:
|
||||
- nvidia,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra20-pinmux";
|
||||
reg = <0x70000014 0x10>, /* Tri-state registers */
|
||||
<0x70000080 0x20>, /* Mux registers */
|
||||
<0x700000a0 0x14>, /* Pull-up/down registers */
|
||||
<0x70000868 0xa8>; /* Pad control registers */
|
||||
|
||||
pinmux {
|
||||
atb {
|
||||
nvidia,pins = "atb", "gma", "gme";
|
||||
nvidia,function = "sdio4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,166 +0,0 @@
|
|||
NVIDIA Tegra210 pinmux controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra210-pinmux"
|
||||
- reg: Should contain a list of base address and size pairs for:
|
||||
- first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
|
||||
- second entry: The PINMUX_AUX_* registers (pinmux)
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Tegra's pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, tristate, drive strength, etc.
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function or tristate parameter. For this
|
||||
reason, even seemingly boolean values are actually tristates in this binding:
|
||||
unspecified, off, or on. Unspecified is represented as an absent property,
|
||||
and off/on are represented as integer values 0 and 1.
|
||||
|
||||
See the TRM to determine which properties and values apply to each pin/group.
|
||||
Macro values for property values are defined in
|
||||
include/dt-binding/pinctrl/pinctrl-tegra.h.
|
||||
|
||||
Required subnode-properties:
|
||||
- nvidia,pins : An array of strings. Each string contains the name of a pin or
|
||||
group. Valid values for these names are listed below.
|
||||
|
||||
Optional subnode-properties:
|
||||
- nvidia,function: A string containing the name of the function to mux to the
|
||||
pin or group.
|
||||
- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
|
||||
0: none, 1: down, 2: up.
|
||||
- nvidia,tristate: Integer.
|
||||
0: drive, 1: tristate.
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path.
|
||||
enable :TEGRA_PIN_ENABLE and
|
||||
disable or output only: TEGRA_PIN_DISABLE.
|
||||
- nvidia,open-drain: Integer.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset.
|
||||
enable: TEGRA_PIN_ENABLE.
|
||||
disable: TEGRA_PIN_DISABLE.
|
||||
- nvidia,io-hv: Integer. Select high-voltage receivers.
|
||||
normal: TEGRA_PIN_DISABLE
|
||||
high: TEGRA_PIN_ENABLE
|
||||
- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
|
||||
normal: TEGRA_PIN_DISABLE
|
||||
high: TEGRA_PIN_ENABLE
|
||||
- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
|
||||
normal: TEGRA_PIN_DISABLE
|
||||
high: TEGRA_PIN_ENABLE
|
||||
- nvidia,drive-type: Integer. Valid range 0...3.
|
||||
- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
|
||||
Tegra TRM.
|
||||
- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
|
||||
The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
|
||||
Tegra TRM.
|
||||
- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVDN_SLWR" in the Tegra TRM.
|
||||
- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
|
||||
fastest. The range of valid values depends on the pingroup. See
|
||||
"DRVUP_SLWF" in the Tegra TRM.
|
||||
|
||||
Valid values for pin and group names (nvidia,pin) are:
|
||||
|
||||
Mux groups:
|
||||
|
||||
These correspond to Tegra PINMUX_AUX_* (pinmux) registers. Any property
|
||||
that exists in those registers may be set for the following pin names.
|
||||
|
||||
In Tegra210, many pins also have a dedicated APB_MISC_GP_*_PADCTRL
|
||||
register. Where that is true, and property that exists in that register
|
||||
may also be set on the following pin names.
|
||||
|
||||
als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, ap_wake_nfc_ph7,
|
||||
aud_mclk_pbb0, batt_bcl, bt_rst_ph4, bt_wake_ap_ph5, button_home_py1,
|
||||
button_power_on_px5, button_slide_sw_py0, button_vol_down_px7,
|
||||
button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, cam1_strobe_pt1,
|
||||
cam2_mclk_ps1, cam2_pwdn_pt0, cam_af_en_ps5, cam_flash_en_ps6,
|
||||
cam_i2c_scl_ps2, cam_i2c_sda_ps3, cam_rst_ps4cam_rst_ps4, clk_32k_in,
|
||||
clk_32k_out_py5, clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
|
||||
dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, dap2_dout_paa3,
|
||||
dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, dap4_dout_pj6, dap4_fs_pj4,
|
||||
dap4_sclk_pj7, dmic1_clk_pe0, dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3,
|
||||
dmic3_clk_pe4, dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
|
||||
gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, gen2_i2c_sda_pj3,
|
||||
gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, gpio_x1_aud_pbb3, gpio_x3_aud_pbb4,
|
||||
gps_en_pi2, gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, jtag_rtck,
|
||||
lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, lcd_gpio2_pv4, lcd_rst_pv2,
|
||||
lcd_te_py2, modem_wake_ap_px0, motion_int_px2, nfc_en_pi0, nfc_int_pi1,
|
||||
pa6, pcc7, pe6, pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
|
||||
pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, pk0, pk1, pk2,
|
||||
pk3, pk4, pk5, pk6, pk7, pl0, pl1, pwr_i2c_scl_py3, pwr_i2c_sda_py4,
|
||||
pwr_int_n, pz0, pz1, pz2, pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
|
||||
qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
|
||||
sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, sdmmc1_dat0_pm5,
|
||||
sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, sdmmc1_dat3_pm2, sdmmc3_clk_pp0,
|
||||
sdmmc3_cmd_pp1, sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
|
||||
sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, spi1_cs0_pc3,
|
||||
spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, spi1_sck_pc2, spi2_cs0_pb7,
|
||||
spi2_cs1_pdd0, spi2_miso_pb5, spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6,
|
||||
spi4_miso_pd0, spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
|
||||
touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, uart1_rx_pu1,
|
||||
uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, uart2_rx_pg1, uart2_tx_pg0,
|
||||
uart3_cts_pd4, uart3_rts_pd3, uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7,
|
||||
uart4_rts_pi6, uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
|
||||
usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, wifi_wake_ap_ph2
|
||||
|
||||
Drive groups:
|
||||
|
||||
These correspond to the Tegra APB_MISC_GP_*_PADCTRL (pad control)
|
||||
registers. Note that where one of these registers controls a single pin
|
||||
for which a PINMUX_AUX_* exists, see the list above for the pin name to
|
||||
use when configuring the pinmux.
|
||||
|
||||
pa6, pcc7, pe6, pe7, ph6, pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
|
||||
pz0, pz1, pz2, pz3, pz4, pz5, sdmmc1, sdmmc2, sdmmc3, sdmmc4
|
||||
|
||||
Valid values for nvidia,functions are:
|
||||
|
||||
aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, displayb,
|
||||
dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, i2c2, i2c3, i2cpmu, i2cvi,
|
||||
i2s1, i2s2, i2s3, i2s4a, i2s4b, i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0,
|
||||
pe1, pmi, pwm0, pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
|
||||
sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, spi3, spi4,
|
||||
sys, touch, uart, uarta, uartb, uartc, uartd, usb, vgp1, vgp2, vgp3, vgp4,
|
||||
vgp5, vgp6, vimclk, vimclk2
|
||||
|
||||
Example:
|
||||
|
||||
pinmux: pinmux@70000800 {
|
||||
compatible = "nvidia,tegra210-pinmux";
|
||||
reg = <0x0 0x700008d4 0x0 0x2a8>, /* Pad control registers */
|
||||
<0x0 0x70003000 0x0 0x1000>; /* Mux registers */
|
||||
|
||||
pinctrl-names = "boot";
|
||||
pinctrl-0 = <&state_boot>;
|
||||
|
||||
state_boot: pinmux {
|
||||
gen1_i2c_scl_pj1 {
|
||||
nvidia,pins = "gen1_i2c_scl_pj1",
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra210 Pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra210-pinmux
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: APB_MISC_GP_*_PADCTRL register (pad control)
|
||||
- description: PINMUX_AUX_* registers (pinmux)
|
||||
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
# pin groups
|
||||
additionalProperties:
|
||||
$ref: nvidia,tegra-pinmux-common.yaml
|
||||
additionalProperties: false
|
||||
properties:
|
||||
nvidia,pins:
|
||||
items:
|
||||
enum: [ als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3,
|
||||
ap_wake_nfc_ph7, aud_mclk_pbb0, batt_bcl, bt_rst_ph4,
|
||||
bt_wake_ap_ph5, button_home_py1, button_power_on_px5,
|
||||
button_slide_sw_py0, button_vol_down_px7,
|
||||
button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7,
|
||||
cam1_strobe_pt1, cam2_mclk_ps1, cam2_pwdn_pt0,
|
||||
cam_af_en_ps5, cam_flash_en_ps6, cam_i2c_scl_ps2,
|
||||
cam_i2c_sda_ps3, cam_rst_ps4, clk_32k_in, clk_32k_out_py5,
|
||||
clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1,
|
||||
dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2,
|
||||
dap2_dout_paa3, dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5,
|
||||
dap4_dout_pj6, dap4_fs_pj4, dap4_sclk_pj7, dmic1_clk_pe0,
|
||||
dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, dmic3_clk_pe4,
|
||||
dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1,
|
||||
gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2,
|
||||
gen2_i2c_sda_pj3, gen3_i2c_scl_pf0, gen3_i2c_sda_pf1,
|
||||
gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, gps_en_pi2,
|
||||
gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1,
|
||||
jtag_rtck, lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3,
|
||||
lcd_gpio2_pv4, lcd_rst_pv2, lcd_te_py2, modem_wake_ap_px0,
|
||||
motion_int_px2, nfc_en_pi0, nfc_int_pi1, pa6, pcc7, pe6,
|
||||
pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0,
|
||||
pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6,
|
||||
pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1,
|
||||
pwr_i2c_scl_py3, pwr_i2c_sda_py4, pwr_int_n, pz0, pz1, pz2,
|
||||
pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2,
|
||||
qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0,
|
||||
sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1,
|
||||
sdmmc1_dat0_pm5, sdmmc1_dat1_pm4, sdmmc1_dat2_pm3,
|
||||
sdmmc1_dat3_pm2, sdmmc3_clk_pp0, sdmmc3_cmd_pp1,
|
||||
sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3,
|
||||
sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2,
|
||||
spi1_cs0_pc3, spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0,
|
||||
spi1_sck_pc2, spi2_cs0_pb7, spi2_cs1_pdd0, spi2_miso_pb5,
|
||||
spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, spi4_miso_pd0,
|
||||
spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7,
|
||||
touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2,
|
||||
uart1_rx_pu1, uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2,
|
||||
uart2_rx_pg1, uart2_tx_pg0, uart3_cts_pd4, uart3_rts_pd3,
|
||||
uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, uart4_rts_pi6,
|
||||
uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4,
|
||||
usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1,
|
||||
wifi_wake_ap_ph2,
|
||||
# drive groups
|
||||
drive_pa6, drive_pcc7, drive_pe6, drive_pe7, drive_ph6,
|
||||
drive_pk0, drive_pk1, drive_pk2, drive_pk3, drive_pk4,
|
||||
drive_pk5, drive_pk6, drive_pk7, drive_pl0, drive_pl1,
|
||||
drive_pz0, drive_pz1, drive_pz2, drive_pz3, drive_pz4,
|
||||
drive_pz5, drive_sdmmc1, drive_sdmmc2, drive_sdmmc3,
|
||||
drive_sdmmc4 ]
|
||||
|
||||
nvidia,function:
|
||||
enum: [ aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya,
|
||||
displayb, dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1,
|
||||
i2c2, i2c3, i2cpmu, i2cvi, i2s1, i2s2, i2s3, i2s4a, i2s4b,
|
||||
i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, pe1, pmi, pwm0,
|
||||
pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata,
|
||||
sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2,
|
||||
spi3, spi4, sys, touch, uart, uarta, uartb, uartc, uartd,
|
||||
usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vimclk, vimclk2 ]
|
||||
|
||||
nvidia,pull: true
|
||||
nvidia,tristate: true
|
||||
nvidia,pull-down-strength: true
|
||||
nvidia,pull-up-strength: true
|
||||
nvidia,high-speed-mode: true
|
||||
nvidia,enable-input: true
|
||||
nvidia,open-drain: true
|
||||
nvidia,lock: true
|
||||
nvidia,drive-type: true
|
||||
nvidia,io-hv: true
|
||||
nvidia,slew-rate-rising: true
|
||||
nvidia,slew-rate-falling: true
|
||||
|
||||
required:
|
||||
- nvidia,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
|
||||
pinmux: pinmux@70000800 {
|
||||
compatible = "nvidia,tegra210-pinmux";
|
||||
reg = <0x700008d4 0x02a8>, /* Pad control registers */
|
||||
<0x70003000 0x1000>; /* Mux registers */
|
||||
|
||||
pinctrl-names = "boot";
|
||||
pinctrl-0 = <&state_boot>;
|
||||
|
||||
state_boot: pinmux {
|
||||
gen1_i2c_scl_pj1 {
|
||||
nvidia,pins = "gen1_i2c_scl_pj1";
|
||||
nvidia,function = "i2c1";
|
||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
|
||||
nvidia,io-hv = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -1,144 +0,0 @@
|
|||
NVIDIA Tegra30 pinmux controller
|
||||
|
||||
The Tegra30 pinctrl binding is very similar to the Tegra20 pinctrl binding,
|
||||
as described in nvidia,tegra20-pinmux.txt. In fact, this document assumes
|
||||
that binding as a baseline, and only documents the differences between the
|
||||
two bindings.
|
||||
|
||||
Required properties:
|
||||
- compatible: "nvidia,tegra30-pinmux"
|
||||
- reg: Should contain the register physical address and length for each of
|
||||
the pad control and mux registers.
|
||||
|
||||
Tegra30 adds the following optional properties for pin configuration subnodes:
|
||||
- nvidia,enable-input: Integer. Enable the pin's input path. 0: no, 1: yes.
|
||||
- nvidia,open-drain: Integer. Enable open drain mode. 0: no, 1: yes.
|
||||
- nvidia,lock: Integer. Lock the pin configuration against further changes
|
||||
until reset. 0: no, 1: yes.
|
||||
- nvidia,io-reset: Integer. Reset the IO path. 0: no, 1: yes.
|
||||
|
||||
As with Tegra20, see the Tegra TRM for complete details regarding which groups
|
||||
support which functionality.
|
||||
|
||||
Valid values for pin and group names are:
|
||||
|
||||
per-pin mux groups:
|
||||
|
||||
These all support nvidia,function, nvidia,tristate, nvidia,pull,
|
||||
nvidia,enable-input, nvidia,lock. Some support nvidia,open-drain,
|
||||
nvidia,io-reset.
|
||||
|
||||
clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, dap2_sclk_pa3,
|
||||
dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, gmi_a17_pb0,
|
||||
gmi_a18_pb1, lcd_pwr0_pb2, lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, lcd_pwr1_pc1,
|
||||
uart2_txd_pc2, uart2_rxd_pc3, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5,
|
||||
lcd_pwr2_pc6, gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, lcd_dc1_pd2,
|
||||
sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, vi_vsync_pd6, vi_hsync_pd7,
|
||||
lcd_d0_pe0, lcd_d1_pe1, lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5,
|
||||
lcd_d6_pe6, lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, lcd_d11_pf3,
|
||||
lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, lcd_d15_pf7, gmi_ad0_pg0,
|
||||
gmi_ad1_pg1, gmi_ad2_pg2, gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5,
|
||||
gmi_ad6_pg6, gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
|
||||
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, gmi_ad15_ph7,
|
||||
gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, gmi_cs6_n_pi3, gmi_rst_n_pi4,
|
||||
gmi_iordy_pi5, gmi_cs7_n_pi6, gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1,
|
||||
gmi_cs1_n_pj2, lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
|
||||
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs4_n_pk2,
|
||||
gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, spdif_in_pk6, gmi_a19_pk7,
|
||||
vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, vi_d5_pl3, vi_d6_pl4, vi_d7_pl5,
|
||||
vi_d8_pl6, vi_d9_pl7, lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
|
||||
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, dap1_fs_pn0,
|
||||
dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, lcd_cs0_n_pn4, lcd_sdout_pn5,
|
||||
lcd_dc0_pn6, hdmi_int_pn7, ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
|
||||
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6,
|
||||
ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, dap3_dout_pp2, dap3_sclk_pp3,
|
||||
dap4_fs_pp4, dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0,
|
||||
kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
|
||||
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, kb_row2_pr2,
|
||||
kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7,
|
||||
kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, kb_row12_ps4,
|
||||
kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
|
||||
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6,
|
||||
sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, pu5, pu6, jtag_rtck_pu7, pv0,
|
||||
pv1, pv2, pv3, ddc_scl_pv4, ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7,
|
||||
lcd_cs1_n_pw0, lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
|
||||
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, spi2_miso_px1,
|
||||
spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, spi1_sck_px5, spi1_cs0_n_px6,
|
||||
spi1_miso_px7, ulpi_clk_py0, ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3,
|
||||
sdmmc1_dat3_py4, sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
|
||||
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, lcd_sck_pz4,
|
||||
sys_clk_req_pz5, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, sdmmc4_dat0_paa0,
|
||||
sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
|
||||
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
|
||||
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, pbb7,
|
||||
cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, sdmmc4_clk_pcc4,
|
||||
clk2_req_pcc5, pex_l2_rst_n_pcc6, pex_l2_clkreq_n_pcc7,
|
||||
pex_l0_prsnt_n_pdd0, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2,
|
||||
pex_wake_n_pdd3, pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
|
||||
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, clk3_req_pee1,
|
||||
clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, core_pwr_req, cpu_pwr_req, owr,
|
||||
pwr_int_n.
|
||||
|
||||
drive groups:
|
||||
|
||||
These all support nvidia,pull-down-strength, nvidia,pull-up-strength,
|
||||
nvidia,slew-rate-rising, nvidia,slew-rate-falling. Most but not all
|
||||
support nvidia,high-speed-mode, nvidia,schmitt, nvidia,low-power-mode.
|
||||
|
||||
ao1, ao2, at1, at2, at3, at4, at5, cdev1, cdev2, cec, crt, csus, dap1,
|
||||
dap2, dap3, dap4, dbg, ddc, dev3, gma, gmb, gmc, gmd, gme, gmf, gmg,
|
||||
gmh, gpv, lcd1, lcd2, owr, sdio1, sdio2, sdio3, spi, uaa, uab, uart2,
|
||||
uart3, uda, vi1.
|
||||
|
||||
Valid values for nvidia,functions are:
|
||||
|
||||
blink, cec, clk_12m_out, clk_32k_in, core_pwr_req, cpu_pwr_req, crt,
|
||||
dap, ddr, dev3, displaya, displayb, dtv, extperiph1, extperiph2,
|
||||
extperiph3, gmi, gmi_alt, hda, hdcp, hdmi, hsi, i2c1, i2c2, i2c3,
|
||||
i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, invalid, kbc, mio, nand,
|
||||
nand_alt, owr, pcie, pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2,
|
||||
rsvd3, rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif, spi1,
|
||||
spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test, trace, uarta,
|
||||
uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6,
|
||||
vi, vi_alt1, vi_alt2, vi_alt3
|
||||
|
||||
Example:
|
||||
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra30-pinmux";
|
||||
reg = < 0x70000868 0xd0 /* Pad control registers */
|
||||
0x70003000 0x3e0 >; /* Mux registers */
|
||||
};
|
||||
|
||||
Example board file extract:
|
||||
|
||||
pinctrl@70000000 {
|
||||
sdmmc4_default: pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@78000400 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc4_default>;
|
||||
};
|
||||
|
|
@ -0,0 +1,176 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra30 pinmux Controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra30-pinmux
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: pad control registers
|
||||
- description: mux registers
|
||||
|
||||
patternProperties:
|
||||
"^pinmux(-[a-z0-9-_]+)?$":
|
||||
type: object
|
||||
properties:
|
||||
phandle: true
|
||||
|
||||
# pin groups
|
||||
additionalProperties:
|
||||
$ref: nvidia,tegra-pinmux-common.yaml
|
||||
additionalProperties: false
|
||||
properties:
|
||||
nvidia,pins:
|
||||
items:
|
||||
enum: [ clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2,
|
||||
dap2_sclk_pa3, dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6,
|
||||
sdmmc3_cmd_pa7, gmi_a17_pb0, gmi_a18_pb1, lcd_pwr0_pb2,
|
||||
lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5,
|
||||
sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0,
|
||||
lcd_pwr1_pc1, uart2_txd_pc2, uart2_rxd_pc3,
|
||||
gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, lcd_pwr2_pc6,
|
||||
gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1,
|
||||
lcd_dc1_pd2, sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5,
|
||||
vi_vsync_pd6, vi_hsync_pd7, lcd_d0_pe0, lcd_d1_pe1,
|
||||
lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, lcd_d6_pe6,
|
||||
lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2,
|
||||
lcd_d11_pf3, lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6,
|
||||
lcd_d15_pf7, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2,
|
||||
gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6,
|
||||
gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2,
|
||||
gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6,
|
||||
gmi_ad15_ph7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2,
|
||||
gmi_cs6_n_pi3, gmi_rst_n_pi4, gmi_iordy_pi5, gmi_cs7_n_pi6,
|
||||
gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, gmi_cs1_n_pj2,
|
||||
lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5,
|
||||
uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1,
|
||||
gmi_cs4_n_pk2, gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5,
|
||||
spdif_in_pk6, gmi_a19_pk7, vi_d2_pl0, vi_d3_pl1, vi_d4_pl2,
|
||||
vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, vi_d8_pl6, vi_d9_pl7,
|
||||
lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3,
|
||||
lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7,
|
||||
dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3,
|
||||
lcd_cs0_n_pn4, lcd_sdout_pn5, lcd_dc0_pn6, hdmi_int_pn7,
|
||||
ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2,
|
||||
ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5,
|
||||
ulpi_data5_po6, ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1,
|
||||
dap3_dout_pp2, dap3_sclk_pp3, dap4_fs_pp4, dap4_din_pp5,
|
||||
dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, kb_col1_pq1,
|
||||
kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5,
|
||||
kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1,
|
||||
kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5,
|
||||
kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, kb_row9_ps1,
|
||||
kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, kb_row13_ps5,
|
||||
kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1,
|
||||
vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5,
|
||||
gen2_i2c_sda_pt6, sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4,
|
||||
pu5, pu6, jtag_rtck_pu7, pv0, pv1, pv2, pv3, ddc_scl_pv4,
|
||||
ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, lcd_cs1_n_pw0,
|
||||
lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4,
|
||||
clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0,
|
||||
spi2_miso_px1, spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4,
|
||||
spi1_sck_px5, spi1_cs0_n_px6, spi1_miso_px7, ulpi_clk_py0,
|
||||
ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, sdmmc1_dat3_py4,
|
||||
sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7,
|
||||
sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3,
|
||||
lcd_sck_pz4, sys_clk_req_pz5, pwr_i2c_scl_pz6,
|
||||
pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1,
|
||||
sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4,
|
||||
sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0,
|
||||
cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6,
|
||||
pbb7, cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3,
|
||||
sdmmc4_clk_pcc4, clk2_req_pcc5, pex_l2_rst_n_pcc6,
|
||||
pex_l2_clkreq_n_pcc7, pex_l0_prsnt_n_pdd0,
|
||||
pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3,
|
||||
pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5,
|
||||
pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0,
|
||||
clk3_req_pee1, clk1_req_pee2, hdmi_cec_pee3, clk_32k_in,
|
||||
core_pwr_req, cpu_pwr_req, owr, pwr_int_n,
|
||||
# drive groups
|
||||
drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3,
|
||||
drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_cec,
|
||||
drive_crt, drive_csus, drive_dap1, drive_dap2, drive_dap3,
|
||||
drive_dap4, drive_dbg, drive_ddc, drive_dev3, drive_gma,
|
||||
drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_gmf,
|
||||
drive_gmg, drive_gmh, drive_gpv, drive_lcd1, drive_lcd2,
|
||||
drive_owr, drive_sdio1, drive_sdio2, drive_sdio3,
|
||||
drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3,
|
||||
drive_uda, drive_vi1 ]
|
||||
|
||||
nvidia,function:
|
||||
enum: [ blink, cec, clk_12m_out, clk_32k_in, core_pwr_req,
|
||||
cpu_pwr_req, crt, dap, ddr, dev3, displaya, displayb, dtv,
|
||||
extperiph1, extperiph2, extperiph3, gmi, gmi_alt, hda, hdcp,
|
||||
hdmi, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2,
|
||||
i2s3, i2s4, invalid, kbc, mio, nand, nand_alt, owr, pcie,
|
||||
pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2, rsvd3,
|
||||
rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif,
|
||||
spi1, spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test,
|
||||
trace, uarta, uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2,
|
||||
vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt2, vi_alt3 ]
|
||||
|
||||
nvidia,pull: true
|
||||
nvidia,tristate: true
|
||||
nvidia,schmitt: true
|
||||
nvidia,pull-down-strength: true
|
||||
nvidia,pull-up-strength: true
|
||||
nvidia,high-speed-mode: true
|
||||
nvidia,low-power-mode: true
|
||||
nvidia,enable-input: true
|
||||
nvidia,open-drain: true
|
||||
nvidia,lock: true
|
||||
nvidia,io-reset: true
|
||||
nvidia,slew-rate-rising: true
|
||||
nvidia,slew-rate-falling: true
|
||||
|
||||
required:
|
||||
- nvidia,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
pinctrl@70000000 {
|
||||
compatible = "nvidia,tegra30-pinmux";
|
||||
reg = <0x70000868 0x0d0>, /* Pad control registers */
|
||||
<0x70003000 0x3e0>; /* Mux registers */
|
||||
|
||||
pinmux {
|
||||
sdmmc4_clk_pcc4 {
|
||||
nvidia,pins = "sdmmc4_clk_pcc4",
|
||||
"sdmmc4_rst_n_pcc3";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <0>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
|
||||
sdmmc4_dat0_paa0 {
|
||||
nvidia,pins = "sdmmc4_dat0_paa0",
|
||||
"sdmmc4_dat1_paa1",
|
||||
"sdmmc4_dat2_paa2",
|
||||
"sdmmc4_dat3_paa3",
|
||||
"sdmmc4_dat4_paa4",
|
||||
"sdmmc4_dat5_paa5",
|
||||
"sdmmc4_dat6_paa6",
|
||||
"sdmmc4_dat7_paa7";
|
||||
nvidia,function = "sdmmc4";
|
||||
nvidia,pull = <2>;
|
||||
nvidia,tristate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -25,7 +25,9 @@ properties:
|
|||
- const: allwinner,sun8i-a83t-pwm
|
||||
- const: allwinner,sun8i-h3-pwm
|
||||
- items:
|
||||
- const: allwinner,sun8i-v3s-pwm
|
||||
- enum:
|
||||
- allwinner,suniv-f1c100s-pwm
|
||||
- allwinner,sun8i-v3s-pwm
|
||||
- const: allwinner,sun7i-a20-pwm
|
||||
- items:
|
||||
- const: allwinner,sun50i-a64-pwm
|
||||
|
|
|
|||
|
|
@ -30,7 +30,9 @@ properties:
|
|||
maxItems: 1
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
enum: [2, 3]
|
||||
description:
|
||||
The only flag supported by the controller is PWM_POLARITY_INVERTED.
|
||||
|
||||
microchip,sync-update-mask:
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -1,77 +0,0 @@
|
|||
Tegra SoC PWFM controller
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be:
|
||||
- "nvidia,tegra20-pwm": for Tegra20
|
||||
- "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
|
||||
- "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
|
||||
- "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
|
||||
- "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
|
||||
- "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
|
||||
- "nvidia,tegra186-pwm": for Tegra186
|
||||
- "nvidia,tegra194-pwm": for Tegra194
|
||||
- reg: physical base address and length of the controller's registers
|
||||
- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
|
||||
the cells format.
|
||||
- clocks: Must contain one entry, for the module clock.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- pwm
|
||||
|
||||
Optional properties:
|
||||
============================
|
||||
In some of the interface like PWM based regulator device, it is required
|
||||
to configure the pins differently in different states, especially in suspend
|
||||
state of the system. The configuration of pin is provided via the pinctrl
|
||||
DT node as detailed in the pinctrl DT binding document
|
||||
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
The PWM node will have following optional properties.
|
||||
pinctrl-names: Pin state names. Must be "default" and "sleep".
|
||||
pinctrl-0: phandle for the default/active state of pin configurations.
|
||||
pinctrl-1: phandle for the sleep state of pin configurations.
|
||||
|
||||
Example:
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car 17>;
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
};
|
||||
|
||||
|
||||
Example with the pin configuration for suspend and resume:
|
||||
=========================================================
|
||||
Suppose pin PE7 (On Tegra210) interfaced with the regulator device and
|
||||
it requires PWM output to be tristated when system enters suspend.
|
||||
Following will be DT binding to achieve this:
|
||||
|
||||
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
|
||||
|
||||
pinmux@700008d4 {
|
||||
pwm_active_state: pwm_active_state {
|
||||
pe7 {
|
||||
nvidia,pins = "pe7";
|
||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm_sleep_state: pwm_sleep_state {
|
||||
pe7 {
|
||||
nvidia,pins = "pe7";
|
||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@7000a000 {
|
||||
/* Mandatory PWM properties */
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pwm_active_state>;
|
||||
pinctrl-1 = <&pwm_sleep_state>;
|
||||
};
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra PWFM controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- nvidia,tegra20-pwm
|
||||
- nvidia,tegra186-pwm
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,tegra30-pwm
|
||||
- nvidia,tegra114-pwm
|
||||
- nvidia,tegra124-pwm
|
||||
- nvidia,tegra132-pwm
|
||||
- nvidia,tegra210-pwm
|
||||
- enum:
|
||||
- nvidia,tegra20-pwm
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra194-pwm
|
||||
- const: nvidia,tegra186-pwm
|
||||
|
||||
- items:
|
||||
- const: nvidia,tegra234-pwm
|
||||
- const: nvidia,tegra194-pwm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: module reset
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: pwm
|
||||
|
||||
"#pwm-cells":
|
||||
const: 2
|
||||
|
||||
pinctrl-names:
|
||||
items:
|
||||
- const: default
|
||||
- const: sleep
|
||||
|
||||
pinctrl-0:
|
||||
description: configuration for the default/active state
|
||||
|
||||
pinctrl-1:
|
||||
description: configuration for the sleep state
|
||||
|
||||
operating-points-v2:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: phandle to the core power domain
|
||||
|
||||
allOf:
|
||||
- $ref: pwm.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra20-car.h>
|
||||
|
||||
pwm: pwm@7000a000 {
|
||||
compatible = "nvidia,tegra20-pwm";
|
||||
reg = <0x7000a000 0x100>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&tegra_car TEGRA20_CLK_PWM>;
|
||||
resets = <&tegra_car 17>;
|
||||
reset-names = "pwm";
|
||||
};
|
||||
|
|
@ -28,17 +28,20 @@ properties:
|
|||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sifive,rocket0
|
||||
- andestech,ax45mp
|
||||
- canaan,k210
|
||||
- sifive,bullet0
|
||||
- sifive,e5
|
||||
- sifive,e7
|
||||
- sifive,e71
|
||||
- sifive,u74-mc
|
||||
- sifive,u54
|
||||
- sifive,u74
|
||||
- sifive,rocket0
|
||||
- sifive,u5
|
||||
- sifive,u54
|
||||
- sifive,u7
|
||||
- canaan,k210
|
||||
- sifive,u74
|
||||
- sifive,u74-mc
|
||||
- thead,c906
|
||||
- thead,c910
|
||||
- const: riscv
|
||||
- items:
|
||||
- enum:
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@ properties:
|
|||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- const: beagle,beaglev-starlight-jh7100-r0
|
||||
- enum:
|
||||
- beagle,beaglev-starlight-jh7100-r0
|
||||
- starfive,visionfive-v1
|
||||
- const: starfive,jh7100
|
||||
|
||||
additionalProperties: true
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/renesas/renesas,r9a09g011-sys.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/V2M System Configuration (SYS)
|
||||
|
||||
maintainers:
|
||||
- Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
|
||||
description:
|
||||
The RZ/V2M-alike SYS (System Configuration) controls the overall
|
||||
configuration of the LSI and supports the following functions,
|
||||
- Bank address settings for DMAC
|
||||
- Bank address settings of the units for ICB
|
||||
- ETHER AxCACHE[1] (C bit) control function
|
||||
- RAMA initialization control
|
||||
- MD[7:0] pin monitoring
|
||||
- LSI version
|
||||
- PCIe related settings
|
||||
- WDT stop control
|
||||
- Temperature sensor (TSU) monitor
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: renesas,r9a09g011-sys
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
sys: system-controller@a3f03000 {
|
||||
compatible = "renesas,r9a09g011-sys";
|
||||
reg = <0xa3f03000 0x400>;
|
||||
};
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/renesas.yaml#
|
||||
$id: http://devicetree.org/schemas/soc/renesas/renesas.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas SH-Mobile, R-Mobile, and R-Car Platform
|
||||
|
|
@ -431,11 +431,12 @@ properties:
|
|||
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
|
||||
- const: renesas,r9a06g032
|
||||
|
||||
- description: RZ/G2UL (R9A07G043)
|
||||
- description: RZ/Five and RZ/G2UL (R9A07G043)
|
||||
items:
|
||||
- enum:
|
||||
- renesas,smarc-evk # SMARC EVK
|
||||
- enum:
|
||||
- renesas,r9a07g043f01 # RZ/Five
|
||||
- renesas,r9a07g043u11 # RZ/G2UL Type-1
|
||||
- renesas,r9a07g043u12 # RZ/G2UL Type-2
|
||||
- const: renesas,r9a07g043
|
||||
|
|
@ -22,6 +22,9 @@ properties:
|
|||
- const: fsl,imx35-cspi
|
||||
- const: fsl,imx51-ecspi
|
||||
- const: fsl,imx53-ecspi
|
||||
- items:
|
||||
- const: fsl,imx8mp-ecspi
|
||||
- const: fsl,imx6ul-ecspi
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx50-ecspi
|
||||
|
|
@ -34,7 +37,6 @@ properties:
|
|||
- fsl,imx8mq-ecspi
|
||||
- fsl,imx8mm-ecspi
|
||||
- fsl,imx8mn-ecspi
|
||||
- fsl,imx8mp-ecspi
|
||||
- const: fsl,imx51-ecspi
|
||||
|
||||
reg:
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ properties:
|
|||
- qcom,sdm630-imem
|
||||
- qcom,sdm845-imem
|
||||
- qcom,sdx55-imem
|
||||
- qcom,sdx65-imem
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
|
|
|
|||
|
|
@ -222,8 +222,8 @@ examples:
|
|||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
|
||||
conn-therm@47 {
|
||||
reg = <PM8350_ADC7_AMUX_THM4_100K_PU>;
|
||||
conn-therm@147 {
|
||||
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time = <200>;
|
||||
};
|
||||
|
|
@ -247,7 +247,7 @@ examples:
|
|||
|
||||
conn-therm@1 {
|
||||
reg = <1>;
|
||||
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU>;
|
||||
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
|
||||
qcom,avg-samples = <2>;
|
||||
qcom,ratiometric;
|
||||
qcom,hw-settle-time-us = <200>;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ properties:
|
|||
- allwinner,sun4i-a10-ehci
|
||||
- allwinner,sun50i-a64-ehci
|
||||
- allwinner,sun50i-h6-ehci
|
||||
- allwinner,sun50i-h616-ehci
|
||||
- allwinner,sun5i-a13-ehci
|
||||
- allwinner,sun6i-a31-ehci
|
||||
- allwinner,sun7i-a20-ehci
|
||||
|
|
|
|||
|
|
@ -20,6 +20,7 @@ properties:
|
|||
- allwinner,sun4i-a10-ohci
|
||||
- allwinner,sun50i-a64-ohci
|
||||
- allwinner,sun50i-h6-ohci
|
||||
- allwinner,sun50i-h616-ohci
|
||||
- allwinner,sun5i-a13-ohci
|
||||
- allwinner,sun6i-a31-ohci
|
||||
- allwinner,sun7i-a20-ohci
|
||||
|
|
|
|||
|
|
@ -1,132 +0,0 @@
|
|||
NVIDIA Tegra xHCI controller
|
||||
============================
|
||||
|
||||
The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by
|
||||
the Tegra XUSB pad controller.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
- compatible: Must be:
|
||||
- Tegra124: "nvidia,tegra124-xusb"
|
||||
- Tegra132: "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"
|
||||
- Tegra210: "nvidia,tegra210-xusb"
|
||||
- Tegra186: "nvidia,tegra186-xusb"
|
||||
- reg: Must contain the base and length of the xHCI host registers, XUSB FPCI
|
||||
registers and XUSB IPFS registers.
|
||||
- reg-names: Must contain the following entries:
|
||||
- "hcd"
|
||||
- "fpci"
|
||||
- "ipfs"
|
||||
- interrupts: Must contain the xHCI host interrupt and the mailbox interrupt.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clock/clock-bindings.txt for details.
|
||||
- clock-names: Must include the following entries:
|
||||
- xusb_host
|
||||
- xusb_host_src
|
||||
- xusb_falcon_src
|
||||
- xusb_ss
|
||||
- xusb_ss_src
|
||||
- xusb_ss_div2
|
||||
- xusb_hs_src
|
||||
- xusb_fs_src
|
||||
- pll_u_480m
|
||||
- clk_m
|
||||
- pll_e
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- xusb_host
|
||||
- xusb_ss
|
||||
- xusb_src
|
||||
Note that xusb_src is the shared reset for xusb_{ss,hs,fs,falcon,host}_src.
|
||||
- nvidia,xusb-padctl: phandle to the XUSB pad controller that is used to
|
||||
configure the USB pads used by the XHCI controller
|
||||
|
||||
For Tegra124 and Tegra132:
|
||||
- avddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
- dvddio-pex-supply: PCIe/USB3 digital logic power supply. Must supply 1.05 V.
|
||||
- avdd-usb-supply: USB controller power supply. Must supply 3.3 V.
|
||||
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
|
||||
- avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
- avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
- hvdd-usb-ss-supply: High-voltage PCIe/USB3 power supply. Must supply 3.3 V.
|
||||
- hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
|
||||
|
||||
For Tegra210:
|
||||
- dvddio-pex-supply: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
- hvddio-pex-supply: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
|
||||
- avdd-usb-supply: USB controller power supply. Must supply 3.3 V.
|
||||
- avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
|
||||
- avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
- dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
- hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
|
||||
|
||||
For Tegra210 and Tegra186:
|
||||
- power-domains: A list of PM domain specifiers that reference each power-domain
|
||||
used by the xHCI controller. This list must comprise of a specifier for the
|
||||
XUSBA and XUSBC power-domains. See ../power/power_domain.txt and
|
||||
../arm/tegra/nvidia,tegra20-pmc.txt for details.
|
||||
- power-domain-names: A list of names that represent each of the specifiers in
|
||||
the 'power-domains' property. Must include 'xusb_ss' and 'xusb_host' which
|
||||
represent the power-domains XUSBA and XUSBC, respectively. See
|
||||
../power/power_domain.txt for details.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
- phys: Must contain an entry for each entry in phy-names.
|
||||
See ../phy/phy-bindings.txt for details.
|
||||
- phy-names: Should include an entry for each PHY used by the controller. The
|
||||
following PHYs are available:
|
||||
- Tegra124: usb2-0, usb2-1, usb2-2, hsic-0, hsic-1, usb3-0, usb3-1
|
||||
- Tegra132: usb2-0, usb2-1, usb2-2, hsic-0, hsic-1, usb3-0, usb3-1
|
||||
- Tegra210: usb2-0, usb2-1, usb2-2, usb2-3, hsic-0, usb3-0, usb3-1, usb3-2,
|
||||
usb3-3
|
||||
- Tegra186: usb2-0, usb2-1, usb2-2, hsic-0, usb3-0, usb3-1, usb3-2
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
usb@0,70090000 {
|
||||
compatible = "nvidia,tegra124-xusb";
|
||||
reg = <0x0 0x70090000 0x0 0x8000>,
|
||||
<0x0 0x70098000 0x0 0x1000>,
|
||||
<0x0 0x70099000 0x0 0x1000>;
|
||||
reg-names = "hcd", "fpci", "ipfs";
|
||||
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
|
||||
<&tegra_car TEGRA124_CLK_CLK_M>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>;
|
||||
clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src",
|
||||
"xusb_ss", "xusb_ss_div2", "xusb_ss_src",
|
||||
"xusb_hs_src", "xusb_fs_src", "pll_u_480m",
|
||||
"clk_m", "pll_e";
|
||||
resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>;
|
||||
reset-names = "xusb_host", "xusb_ss", "xusb_src";
|
||||
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
|
||||
phy-names = "usb2-1", "usb2-2", "usb3-0";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-usb-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-utmip-supply = <&vddio_1v8>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra124 xHCI controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
|
||||
exposed by the Tegra XUSB pad controller.
|
||||
|
||||
properties:
|
||||
# required
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: NVIDIA Tegra124
|
||||
const: nvidia,tegra124-xusb
|
||||
|
||||
- description: NVIDIA Tegra132
|
||||
items:
|
||||
- const: nvidia,tegra132-xusb
|
||||
- const: nvidia,tegra124-xusb
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: base and length of the xHCI host registers
|
||||
- description: base and length of the XUSB FPCI registers
|
||||
- description: base and length of the XUSB IPFS registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: hcd
|
||||
- const: fpci
|
||||
- const: ipfs
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: xHCI host interrupt
|
||||
- description: mailbox interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XUSB host clock
|
||||
- description: XUSB host source clock
|
||||
- description: XUSB Falcon source clock
|
||||
- description: XUSB SuperSpeed clock
|
||||
- description: XUSB SuperSpeed clock divider
|
||||
- description: XUSB SuperSpeed source clock
|
||||
- description: XUSB HighSpeed clock source
|
||||
- description: XUSB FullSpeed clock source
|
||||
- description: USB PLL
|
||||
- description: reference clock
|
||||
- description: I/O PLL
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_host_src
|
||||
- const: xusb_falcon_src
|
||||
- const: xusb_ss
|
||||
- const: xusb_ss_div2
|
||||
- const: xusb_ss_src
|
||||
- const: xusb_hs_src
|
||||
- const: xusb_fs_src
|
||||
- const: pll_u_480m
|
||||
- const: clk_m
|
||||
- const: pll_e
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: reset for the XUSB host controller
|
||||
- description: reset for the SuperSpeed logic
|
||||
- description: shared reset for xusb_{ss,hs,fs,falcon,host}_src.
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_ss
|
||||
- const: xusb_src
|
||||
|
||||
nvidia,xusb-padctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to the XUSB pad controller that is used to configure
|
||||
the USB pads used by the XHCI controller
|
||||
|
||||
# optional
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
items:
|
||||
enum:
|
||||
- usb2-0
|
||||
- usb2-1
|
||||
- usb2-2
|
||||
- hsic-0
|
||||
- hsic-1
|
||||
- usb3-0
|
||||
- usb3-1
|
||||
|
||||
avddio-pex-supply:
|
||||
description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
|
||||
dvddio-pex-supply:
|
||||
description: PCIe/USB3 digital logic power supply. Must supply 1.05 V.
|
||||
|
||||
avdd-usb-supply:
|
||||
description: USB controller power supply. Must supply 3.3 V.
|
||||
|
||||
avdd-pll-utmip-supply:
|
||||
description: UTMI PLL power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-pll-erefe-supply:
|
||||
description: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
|
||||
avdd-usb-ss-pll-supply:
|
||||
description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
|
||||
hvdd-usb-ss-supply:
|
||||
description: High-voltage PCIe/USB3 power supply. Must supply 3.3 V.
|
||||
|
||||
hvdd-usb-ss-pll-e-supply:
|
||||
description: High-voltage PLLE power supply. Must supply 3.3 V.
|
||||
|
||||
allOf:
|
||||
- $ref: usb-xhci.yaml
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- nvidia,xusb-padctl
|
||||
- phys
|
||||
- phy-names
|
||||
- avddio-pex-supply
|
||||
- dvddio-pex-supply
|
||||
- avdd-usb-supply
|
||||
- hvdd-usb-ss-supply
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra124-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
usb@70090000 {
|
||||
compatible = "nvidia,tegra124-xusb";
|
||||
reg = <0x70090000 0x8000>,
|
||||
<0x70098000 0x1000>,
|
||||
<0x70099000 0x1000>;
|
||||
reg-names = "hcd", "fpci", "ipfs";
|
||||
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_U_480M>,
|
||||
<&tegra_car TEGRA124_CLK_CLK_M>,
|
||||
<&tegra_car TEGRA124_CLK_PLL_E>;
|
||||
clock-names = "xusb_host", "xusb_host_src", "xusb_falcon_src",
|
||||
"xusb_ss", "xusb_ss_div2", "xusb_ss_src",
|
||||
"xusb_hs_src", "xusb_fs_src", "pll_u_480m",
|
||||
"clk_m", "pll_e";
|
||||
resets = <&tegra_car 89>, <&tegra_car 156>, <&tegra_car 143>;
|
||||
reset-names = "xusb_host", "xusb_ss", "xusb_src";
|
||||
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
|
||||
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
|
||||
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
|
||||
phy-names = "usb2-1", "usb2-2", "usb3-0";
|
||||
|
||||
avddio-pex-supply = <&vdd_1v05_run>;
|
||||
dvddio-pex-supply = <&vdd_1v05_run>;
|
||||
avdd-usb-supply = <&vdd_3v3_lp0>;
|
||||
avdd-pll-utmip-supply = <&vddio_1v8>;
|
||||
avdd-pll-erefe-supply = <&avdd_1v05_run>;
|
||||
avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
|
||||
hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra186 xHCI controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
|
||||
exposed by the Tegra XUSB pad controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra186-xusb
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: base and length of the xHCI host registers
|
||||
- description: base and length of the XUSB FPCI registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: hcd
|
||||
- const: fpci
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: xHCI host interrupt
|
||||
- description: mailbox interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XUSB host clock
|
||||
- description: XUSB Falcon source clock
|
||||
- description: XUSB SuperSpeed clock
|
||||
- description: XUSB SuperSpeed source clock
|
||||
- description: XUSB HighSpeed clock source
|
||||
- description: XUSB FullSpeed clock source
|
||||
- description: USB PLL
|
||||
- description: reference clock
|
||||
- description: I/O PLL
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_falcon_src
|
||||
- const: xusb_ss
|
||||
- const: xusb_ss_src
|
||||
- const: xusb_hs_src
|
||||
- const: xusb_fs_src
|
||||
- const: pll_u_480m
|
||||
- const: clk_m
|
||||
- const: pll_e
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: read client
|
||||
- description: write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,xusb-padctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to the XUSB pad controller that is used to configure
|
||||
the USB pads used by the XHCI controller
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
maxItems: 7
|
||||
items:
|
||||
enum:
|
||||
- usb2-0
|
||||
- usb2-1
|
||||
- usb2-2
|
||||
- hsic-0
|
||||
- usb3-0
|
||||
- usb3-1
|
||||
- usb3-2
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: XUSBC power domain (for Host and USB 2.0)
|
||||
- description: XUSBA power domain (for SuperSpeed)
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_ss
|
||||
|
||||
dvddio-pex-supply:
|
||||
description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
|
||||
hvddio-pex-supply:
|
||||
description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-usb-supply:
|
||||
description: USB controller power supply. Must supply 3.3 V.
|
||||
|
||||
avdd-pll-utmip-supply:
|
||||
description: UTMI PLL power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-pll-uerefe-supply:
|
||||
description: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
|
||||
dvdd-usb-ss-pll-supply:
|
||||
description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
|
||||
hvdd-usb-ss-pll-e-supply:
|
||||
description: High-voltage PLLE power supply. Must supply 1.8 V.
|
||||
|
||||
allOf:
|
||||
- $ref: usb-xhci.yaml
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra186-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/memory/tegra186-mc.h>
|
||||
#include <dt-bindings/power/tegra186-powergate.h>
|
||||
#include <dt-bindings/reset/tegra186-reset.h>
|
||||
|
||||
usb@3530000 {
|
||||
compatible = "nvidia,tegra186-xusb";
|
||||
reg = <0x03530000 0x8000>,
|
||||
<0x03538000 0x1000>;
|
||||
reg-names = "hcd", "fpci";
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
|
||||
<&bpmp TEGRA186_CLK_XUSB_FALCON>,
|
||||
<&bpmp TEGRA186_CLK_XUSB_SS>,
|
||||
<&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
|
||||
<&bpmp TEGRA186_CLK_CLK_M>,
|
||||
<&bpmp TEGRA186_CLK_XUSB_FS>,
|
||||
<&bpmp TEGRA186_CLK_PLLU>,
|
||||
<&bpmp TEGRA186_CLK_CLK_M>,
|
||||
<&bpmp TEGRA186_CLK_PLLE>;
|
||||
clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
|
||||
"xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
|
||||
"pll_u_480m", "clk_m", "pll_e";
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
|
||||
<&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
|
||||
power-domain-names = "xusb_host", "xusb_ss";
|
||||
interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
|
||||
<&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phys = <&{/padctl@3520000/pads/usb2/lanes/usb2-0}>,
|
||||
<&{/padctl@3520000/pads/usb2/lanes/usb2-1}>,
|
||||
<&{/padctl@3520000/pads/usb3/lanes/usb3-0}>;
|
||||
phy-names = "usb2-0", "usb2-1", "usb3-0";
|
||||
};
|
||||
|
|
@ -0,0 +1,179 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra194 xHCI controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
|
||||
exposed by the Tegra XUSB pad controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra194-xusb
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: base and length of the xHCI host registers
|
||||
- description: base and length of the XUSB FPCI registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: hcd
|
||||
- const: fpci
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: xHCI host interrupt
|
||||
- description: mailbox interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XUSB host clock
|
||||
- description: XUSB Falcon source clock
|
||||
- description: XUSB SuperSpeed clock
|
||||
- description: XUSB SuperSpeed source clock
|
||||
- description: XUSB HighSpeed clock source
|
||||
- description: XUSB FullSpeed clock source
|
||||
- description: USB PLL
|
||||
- description: reference clock
|
||||
- description: I/O PLL
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_falcon_src
|
||||
- const: xusb_ss
|
||||
- const: xusb_ss_src
|
||||
- const: xusb_hs_src
|
||||
- const: xusb_fs_src
|
||||
- const: pll_u_480m
|
||||
- const: clk_m
|
||||
- const: pll_e
|
||||
|
||||
interconnects:
|
||||
items:
|
||||
- description: read client
|
||||
- description: write client
|
||||
|
||||
interconnect-names:
|
||||
items:
|
||||
- const: dma-mem # read
|
||||
- const: write
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
nvidia,xusb-padctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to the XUSB pad controller that is used to configure
|
||||
the USB pads used by the XHCI controller
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
items:
|
||||
enum:
|
||||
- usb2-0
|
||||
- usb2-1
|
||||
- usb2-2
|
||||
- usb2-3
|
||||
- usb3-0
|
||||
- usb3-1
|
||||
- usb3-2
|
||||
- usb3-3
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: XUSBC power domain (for Host and USB 2.0)
|
||||
- description: XUSBA power domain (for SuperSpeed)
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_ss
|
||||
|
||||
dvddio-pex-supply:
|
||||
description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
|
||||
hvddio-pex-supply:
|
||||
description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-usb-supply:
|
||||
description: USB controller power supply. Must supply 3.3 V.
|
||||
|
||||
avdd-pll-utmip-supply:
|
||||
description: UTMI PLL power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-pll-uerefe-supply:
|
||||
description: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
|
||||
dvdd-usb-ss-pll-supply:
|
||||
description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
|
||||
hvdd-usb-ss-pll-e-supply:
|
||||
description: High-voltage PLLE power supply. Must supply 1.8 V.
|
||||
|
||||
allOf:
|
||||
- $ref: usb-xhci.yaml
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra194-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/memory/tegra194-mc.h>
|
||||
#include <dt-bindings/power/tegra194-powergate.h>
|
||||
#include <dt-bindings/reset/tegra194-reset.h>
|
||||
|
||||
usb@3610000 {
|
||||
compatible = "nvidia,tegra194-xusb";
|
||||
reg = <0x03610000 0x40000>,
|
||||
<0x03600000 0x10000>;
|
||||
reg-names = "hcd", "fpci";
|
||||
|
||||
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
|
||||
<&bpmp TEGRA194_CLK_XUSB_FALCON>,
|
||||
<&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
|
||||
<&bpmp TEGRA194_CLK_XUSB_SS>,
|
||||
<&bpmp TEGRA194_CLK_CLK_M>,
|
||||
<&bpmp TEGRA194_CLK_XUSB_FS>,
|
||||
<&bpmp TEGRA194_CLK_UTMIPLL>,
|
||||
<&bpmp TEGRA194_CLK_CLK_M>,
|
||||
<&bpmp TEGRA194_CLK_PLLE>;
|
||||
clock-names = "xusb_host", "xusb_falcon_src",
|
||||
"xusb_ss", "xusb_ss_src", "xusb_hs_src",
|
||||
"xusb_fs_src", "pll_u_480m", "clk_m",
|
||||
"pll_e";
|
||||
interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
|
||||
<&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
|
||||
interconnect-names = "dma-mem", "write";
|
||||
iommus = <&smmu TEGRA194_SID_XUSB_HOST>;
|
||||
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
|
||||
<&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
|
||||
power-domain-names = "xusb_host", "xusb_ss";
|
||||
|
||||
nvidia,xusb-padctl = <&xusb_padctl>;
|
||||
|
||||
phys = <&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-0}>,
|
||||
<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-1}>,
|
||||
<&{/bus@0/padctl@3520000/pads/usb2/lanes/usb2-3}>,
|
||||
<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-0}>,
|
||||
<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-2}>,
|
||||
<&{/bus@0/padctl@3520000/pads/usb3/lanes/usb3-3}>;
|
||||
phy-names = "usb2-0", "usb2-1", "usb2-3", "usb3-0", "usb3-2", "usb3-3";
|
||||
};
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/usb/nvidia,tegra210-xusb.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NVIDIA Tegra210 xHCI controller
|
||||
|
||||
maintainers:
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
- Jon Hunter <jonathanh@nvidia.com>
|
||||
|
||||
description: The Tegra xHCI controller supports both USB2 and USB3 interfaces
|
||||
exposed by the Tegra XUSB pad controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra210-xusb
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: base and length of the xHCI host registers
|
||||
- description: base and length of the XUSB FPCI registers
|
||||
- description: base and length of the XUSB IPFS registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: hcd
|
||||
- const: fpci
|
||||
- const: ipfs
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: xHCI host interrupt
|
||||
- description: mailbox interrupt
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: XUSB host clock
|
||||
- description: XUSB host source clock
|
||||
- description: XUSB Falcon source clock
|
||||
- description: XUSB SuperSpeed clock
|
||||
- description: XUSB SuperSpeed clock divider
|
||||
- description: XUSB SuperSpeed source clock
|
||||
- description: XUSB HighSpeed clock source
|
||||
- description: XUSB FullSpeed clock source
|
||||
- description: USB PLL
|
||||
- description: reference clock
|
||||
- description: I/O PLL
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_host_src
|
||||
- const: xusb_falcon_src
|
||||
- const: xusb_ss
|
||||
- const: xusb_ss_div2
|
||||
- const: xusb_ss_src
|
||||
- const: xusb_hs_src
|
||||
- const: xusb_fs_src
|
||||
- const: pll_u_480m
|
||||
- const: clk_m
|
||||
- const: pll_e
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: reset for the XUSB host controller
|
||||
- description: reset for the SuperSpeed logic
|
||||
- description: shared reset for xusb_{ss,hs,fs,falcon,host}_src.
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_ss
|
||||
- const: xusb_src
|
||||
|
||||
nvidia,xusb-padctl:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to the XUSB pad controller that is used to configure
|
||||
the USB pads used by the XHCI controller
|
||||
|
||||
phys:
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
phy-names:
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
items:
|
||||
enum:
|
||||
- usb2-0
|
||||
- usb2-1
|
||||
- usb2-2
|
||||
- usb2-3
|
||||
- hsic-0
|
||||
- usb3-0
|
||||
- usb3-1
|
||||
- usb3-2
|
||||
- usb3-3
|
||||
|
||||
power-domains:
|
||||
items:
|
||||
- description: XUSBC power domain (for Host and USB 2.0)
|
||||
- description: XUSBA power domain (for SuperSpeed)
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: xusb_host
|
||||
- const: xusb_ss
|
||||
|
||||
dvddio-pex-supply:
|
||||
description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
|
||||
|
||||
hvddio-pex-supply:
|
||||
description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-usb-supply:
|
||||
description: USB controller power supply. Must supply 3.3 V.
|
||||
|
||||
avdd-pll-utmip-supply:
|
||||
description: UTMI PLL power supply. Must supply 1.8 V.
|
||||
|
||||
avdd-pll-uerefe-supply:
|
||||
description: PLLE reference PLL power supply. Must supply 1.05 V.
|
||||
|
||||
dvdd-usb-ss-pll-supply:
|
||||
description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
|
||||
|
||||
hvdd-usb-ss-pll-e-supply:
|
||||
description: High-voltage PLLE power supply. Must supply 1.8 V.
|
||||
|
||||
allOf:
|
||||
- $ref: usb-xhci.yaml
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/tegra210-car.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
usb@70090000 {
|
||||
compatible = "nvidia,tegra210-xusb";
|
||||
reg = <0x70090000 0x8000>,
|
||||
<0x70098000 0x1000>,
|
||||
<0x70099000 0x1000>;
|
||||
reg-names = "hcd", "fpci", "ipfs";
|
||||
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_SS>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_U_480M>,
|
||||
<&tegra_car TEGRA210_CLK_CLK_M>,
|
||||
<&tegra_car TEGRA210_CLK_PLL_E>;
|
||||
clock-names = "xusb_host", "xusb_host_src",
|
||||
"xusb_falcon_src", "xusb_ss",
|
||||
"xusb_ss_div2", "xusb_ss_src",
|
||||
"xusb_hs_src", "xusb_fs_src",
|
||||
"pll_u_480m", "clk_m", "pll_e";
|
||||
resets = <&tegra_car 89>, <&tegra_car 156>,
|
||||
<&tegra_car 143>;
|
||||
reset-names = "xusb_host", "xusb_ss", "xusb_src";
|
||||
power-domains = <&pd_xusbhost>, <&pd_xusbss>;
|
||||
power-domain-names = "xusb_host", "xusb_ss";
|
||||
|
||||
nvidia,xusb-padctl = <&padctl>;
|
||||
|
||||
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
|
||||
<&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
|
||||
<&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
|
||||
<&{/padctl@7009f000/pads/usb2/lanes/usb2-3}>,
|
||||
<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>,
|
||||
<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
|
||||
phy-names = "usb2-0", "usb2-1", "usb2-2", "usb2-3", "usb3-0",
|
||||
"usb3-1";
|
||||
dvddio-pex-supply = <&vdd_pex_1v05>;
|
||||
hvddio-pex-supply = <&vdd_1v8>;
|
||||
avdd-usb-supply = <&vdd_3v3_sys>;
|
||||
avdd-pll-utmip-supply = <&vdd_1v8>;
|
||||
avdd-pll-uerefe-supply = <&vdd_pex_1v05>;
|
||||
dvdd-usb-ss-pll-supply = <&vdd_pex_1v05>;
|
||||
hvdd-usb-ss-pll-e-supply = <&vdd_1v8>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "usb955,9ff";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
|
@ -69,6 +69,8 @@ patternProperties:
|
|||
description: Annapurna Labs
|
||||
"^alcatel,.*":
|
||||
description: Alcatel
|
||||
"^alfa-network,.*":
|
||||
description: ALFA Network Inc.
|
||||
"^allegro,.*":
|
||||
description: Allegro DVT
|
||||
"^allo,.*":
|
||||
|
|
@ -260,6 +262,8 @@ patternProperties:
|
|||
description: Cirrus Logic, Inc.
|
||||
"^cisco,.*":
|
||||
description: Cisco Systems, Inc.
|
||||
"^cloos,.*":
|
||||
description: Carl Cloos Schweisstechnik GmbH.
|
||||
"^cloudengines,.*":
|
||||
description: Cloud Engines, Inc.
|
||||
"^cnm,.*":
|
||||
|
|
@ -605,6 +609,8 @@ patternProperties:
|
|||
description: Ingenic Semiconductor
|
||||
"^injoinic,.*":
|
||||
description: Injoinic Technology Corp.
|
||||
"^innocomm,.*":
|
||||
description: InnoComm Mobile Technology Corp.
|
||||
"^innolux,.*":
|
||||
description: Innolux Corporation
|
||||
"^inside-secure,.*":
|
||||
|
|
|
|||
11
MAINTAINERS
11
MAINTAINERS
|
|
@ -1907,6 +1907,7 @@ T: git https://github.com/AsahiLinux/linux.git
|
|||
F: Documentation/devicetree/bindings/arm/apple.yaml
|
||||
F: Documentation/devicetree/bindings/arm/apple/*
|
||||
F: Documentation/devicetree/bindings/clock/apple,nco.yaml
|
||||
F: Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml
|
||||
F: Documentation/devicetree/bindings/dma/apple,admac.yaml
|
||||
F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml
|
||||
F: Documentation/devicetree/bindings/interrupt-controller/apple,*
|
||||
|
|
@ -1921,6 +1922,7 @@ F: Documentation/devicetree/bindings/power/apple*
|
|||
F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml
|
||||
F: arch/arm64/boot/dts/apple/
|
||||
F: drivers/clk/clk-apple-nco.c
|
||||
F: drivers/cpufreq/apple-soc-cpufreq.c
|
||||
F: drivers/dma/apple-admac.c
|
||||
F: drivers/i2c/busses/i2c-pasemi-core.c
|
||||
F: drivers/i2c/busses/i2c-pasemi-platform.c
|
||||
|
|
@ -2349,6 +2351,8 @@ M: Gregory Clement <gregory.clement@bootlin.com>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
|
||||
F: Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt
|
||||
F: Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt
|
||||
F: Documentation/devicetree/bindings/soc/dove/
|
||||
F: arch/arm/boot/dts/dove*
|
||||
F: arch/arm/boot/dts/orion5x*
|
||||
|
|
@ -2365,6 +2369,7 @@ M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
|||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git
|
||||
F: Documentation/devicetree/bindings/arm/marvell/
|
||||
F: arch/arm/boot/dts/armada*
|
||||
F: arch/arm/boot/dts/kirkwood*
|
||||
F: arch/arm/configs/mvebu_*_defconfig
|
||||
|
|
@ -2628,7 +2633,7 @@ W: http://www.armlinux.org.uk/
|
|||
ARM/QUALCOMM SUPPORT
|
||||
M: Andy Gross <agross@kernel.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
R: Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
R: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
|
||||
|
|
@ -2699,7 +2704,7 @@ F: arch/arm/boot/dts/rtd*
|
|||
F: arch/arm/mach-realtek/
|
||||
F: arch/arm64/boot/dts/realtek/
|
||||
|
||||
ARM/RENESAS ARCHITECTURE
|
||||
ARM/RISC-V/RENESAS ARCHITECTURE
|
||||
M: Geert Uytterhoeven <geert+renesas@glider.be>
|
||||
M: Magnus Damm <magnus.damm@gmail.com>
|
||||
L: linux-renesas-soc@vger.kernel.org
|
||||
|
|
@ -2707,7 +2712,6 @@ S: Supported
|
|||
Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
|
||||
C: irc://irc.libera.chat/renesas-soc
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
|
||||
F: Documentation/devicetree/bindings/arm/renesas.yaml
|
||||
F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml
|
||||
F: Documentation/devicetree/bindings/soc/renesas/
|
||||
F: arch/arm/boot/dts/emev2*
|
||||
|
|
@ -2721,6 +2725,7 @@ F: arch/arm/configs/shmobile_defconfig
|
|||
F: arch/arm/include/debug/renesas-scif.S
|
||||
F: arch/arm/mach-shmobile/
|
||||
F: arch/arm64/boot/dts/renesas/
|
||||
F: arch/riscv/boot/dts/renesas/
|
||||
F: drivers/soc/renesas/
|
||||
F: include/linux/soc/renesas/
|
||||
|
||||
|
|
|
|||
4
Makefile
4
Makefile
|
|
@ -2003,7 +2003,9 @@ clean: $(clean-dirs)
|
|||
@find $(or $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
|
||||
\( -name '*.[aios]' -o -name '*.rsi' -o -name '*.ko' -o -name '.*.cmd' \
|
||||
-o -name '*.ko.*' \
|
||||
-o -name '*.dtb' -o -name '*.dtbo' -o -name '*.dtb.S' -o -name '*.dt.yaml' \
|
||||
-o -name '*.dtb' -o -name '*.dtbo' \
|
||||
-o -name '*.dtb.S' -o -name '*.dtbo.S' \
|
||||
-o -name '*.dt.yaml' \
|
||||
-o -name '*.dwo' -o -name '*.lst' \
|
||||
-o -name '*.su' -o -name '*.mod' -o -name '*.usyms' \
|
||||
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
|
||||
|
|
|
|||
|
|
@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
|||
bcm4709-tplink-archer-c9-v1.dtb \
|
||||
bcm47094-asus-rt-ac88u.dtb \
|
||||
bcm47094-dlink-dir-885l.dtb \
|
||||
bcm47094-dlink-dir-890l.dtb \
|
||||
bcm47094-linksys-panamera.dtb \
|
||||
bcm47094-luxul-abr-4500.dtb \
|
||||
bcm47094-luxul-xap-1610.dtb \
|
||||
|
|
@ -139,6 +140,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
|||
bcm47094-netgear-r8500.dtb \
|
||||
bcm47094-phicomm-k3.dtb \
|
||||
bcm53015-meraki-mr26.dtb \
|
||||
bcm53016-dlink-dwl-8610ap.dtb \
|
||||
bcm53016-meraki-mr32.dtb \
|
||||
bcm94708.dtb \
|
||||
bcm94709.dtb \
|
||||
|
|
@ -355,6 +357,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
|
|||
kirkwood-ns2mini.dtb \
|
||||
kirkwood-nsa310.dtb \
|
||||
kirkwood-nsa310a.dtb \
|
||||
kirkwood-nsa310s.dtb \
|
||||
kirkwood-nsa320.dtb \
|
||||
kirkwood-nsa325.dtb \
|
||||
kirkwood-openblocks_a6.dtb \
|
||||
|
|
@ -681,6 +684,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
|||
imx6s-dhcom-drc02.dtb
|
||||
dtb-$(CONFIG_SOC_IMX6SL) += \
|
||||
imx6sl-evk.dtb \
|
||||
imx6sl-kobo-aura2.dtb \
|
||||
imx6sl-tolino-shine2hd.dtb \
|
||||
imx6sl-tolino-shine3.dtb \
|
||||
imx6sl-tolino-vision5.dtb \
|
||||
|
|
@ -1029,7 +1033,9 @@ dtb-$(CONFIG_ARCH_OXNAS) += \
|
|||
dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-apq8016-sbc.dtb \
|
||||
qcom-apq8026-asus-sparrow.dtb \
|
||||
qcom-apq8026-huawei-sturgeon.dtb \
|
||||
qcom-apq8026-lg-lenok.dtb \
|
||||
qcom-apq8026-samsung-matisse-wifi.dtb \
|
||||
qcom-apq8060-dragonboard.dtb \
|
||||
qcom-apq8064-cm-qs600.dtb \
|
||||
qcom-apq8064-ifc6410.dtb \
|
||||
|
|
@ -1059,6 +1065,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
|||
qcom-msm8974-sony-xperia-rhine-amami.dtb \
|
||||
qcom-msm8974-sony-xperia-rhine-honami.dtb \
|
||||
qcom-msm8974pro-fairphone-fp2.dtb \
|
||||
qcom-msm8974pro-oneplus-bacon.dtb \
|
||||
qcom-msm8974pro-samsung-klte.dtb \
|
||||
qcom-msm8974pro-sony-xperia-shinano-castor.dtb \
|
||||
qcom-mdm9615-wp8548-mangoh-green.dtb \
|
||||
|
|
@ -1214,6 +1221,7 @@ dtb-$(CONFIG_ARCH_STM32) += \
|
|||
stm32mp151a-prtt1a.dtb \
|
||||
stm32mp151a-prtt1c.dtb \
|
||||
stm32mp151a-prtt1s.dtb \
|
||||
stm32mp151a-dhcor-testbench.dtb \
|
||||
stm32mp153c-dhcom-drc02.dtb \
|
||||
stm32mp153c-dhcor-drc-compact.dtb \
|
||||
stm32mp157a-avenger96.dtb \
|
||||
|
|
@ -1454,6 +1462,8 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
|
|||
uniphier-pro4-ace.dtb \
|
||||
uniphier-pro4-ref.dtb \
|
||||
uniphier-pro4-sanji.dtb \
|
||||
uniphier-pro5-epcore.dtb \
|
||||
uniphier-pro5-proex.dtb \
|
||||
uniphier-pxs2-gentil.dtb \
|
||||
uniphier-pxs2-vodka.dtb \
|
||||
uniphier-sld8-ref.dtb
|
||||
|
|
@ -1588,6 +1598,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
|||
aspeed-bmc-asrock-e3c246d4i.dtb \
|
||||
aspeed-bmc-asrock-romed8hm3.dtb \
|
||||
aspeed-bmc-bytedance-g220a.dtb \
|
||||
aspeed-bmc-delta-ahe50dc.dtb \
|
||||
aspeed-bmc-facebook-bletchley.dtb \
|
||||
aspeed-bmc-facebook-cloudripper.dtb \
|
||||
aspeed-bmc-facebook-cmm.dtb \
|
||||
|
|
@ -1601,6 +1612,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
|||
aspeed-bmc-facebook-wedge400.dtb \
|
||||
aspeed-bmc-facebook-yamp.dtb \
|
||||
aspeed-bmc-facebook-yosemitev2.dtb \
|
||||
aspeed-bmc-ibm-bonnell.dtb \
|
||||
aspeed-bmc-ibm-everest.dtb \
|
||||
aspeed-bmc-ibm-rainier.dtb \
|
||||
aspeed-bmc-ibm-rainier-1s4u.dtb \
|
||||
|
|
@ -1612,7 +1624,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
|
|||
aspeed-bmc-lenovo-hr855xg2.dtb \
|
||||
aspeed-bmc-microsoft-olympus.dtb \
|
||||
aspeed-bmc-opp-lanyang.dtb \
|
||||
aspeed-bmc-opp-mihawk.dtb \
|
||||
aspeed-bmc-opp-mowgli.dtb \
|
||||
aspeed-bmc-opp-nicole.dtb \
|
||||
aspeed-bmc-opp-palmetto.dtb \
|
||||
|
|
|
|||
|
|
@ -17,18 +17,18 @@
|
|||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power {
|
||||
led-power {
|
||||
label = "onrisc:red:power";
|
||||
linux,default-trigger = "default-on";
|
||||
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
wlan {
|
||||
led-wlan {
|
||||
label = "onrisc:blue:wlan";
|
||||
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
app {
|
||||
led-app {
|
||||
label = "onrisc:green:app";
|
||||
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
|
|
|
|||
|
|
@ -85,8 +85,13 @@
|
|||
audio-ports = < TDA998x_I2S 0x03>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
hdmi_0: endpoint@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_0: endpoint {
|
||||
remote-endpoint = <&lcdc_0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -126,7 +126,7 @@
|
|||
backlight = <&backlight>;
|
||||
|
||||
port {
|
||||
panel_0: endpoint@0 {
|
||||
panel_0: endpoint {
|
||||
remote-endpoint = <&lcdc_0>;
|
||||
};
|
||||
};
|
||||
|
|
@ -544,7 +544,7 @@
|
|||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x000020000>;
|
||||
reg = <0x00000000 0x00020000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
|
|
|
|||
|
|
@ -191,7 +191,7 @@
|
|||
backlight = <&lcd_bl>;
|
||||
|
||||
port {
|
||||
panel_0: endpoint@0 {
|
||||
panel_0: endpoint {
|
||||
remote-endpoint = <&lcdc_0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -103,8 +103,9 @@
|
|||
|
||||
};
|
||||
|
||||
guardian_beeper: dmtimer-pwm@7 {
|
||||
guardian_beeper: pwm-7 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
#pwm-cells = <3>;
|
||||
ti,timers = <&timer7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&guardian_beeper_pins>;
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@
|
|||
/* MTD partition table */
|
||||
partition@0 {
|
||||
label = "SPL";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
|
|
@ -188,7 +188,7 @@
|
|||
|
||||
partition@4 {
|
||||
label = "File System";
|
||||
reg = <0x00780000 0x007880000>;
|
||||
reg = <0x00780000 0x07880000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -16,11 +16,11 @@
|
|||
|
||||
/* Power supply provides a fixed 3.3V @3A */
|
||||
vmmcsd_fixed: vmmcsd-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buttons: push_button {
|
||||
|
|
|
|||
|
|
@ -21,11 +21,11 @@
|
|||
|
||||
/* Power supply provides a fixed 3.3V @3A */
|
||||
vmmcsd_fixed: vmmcsd-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
buttons: push_button {
|
||||
|
|
|
|||
|
|
@ -161,8 +161,13 @@
|
|||
#sound-dai-cells = <0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
hdmi_0: endpoint@0 {
|
||||
reg = <0>;
|
||||
|
||||
hdmi_0: endpoint {
|
||||
remote-endpoint = <&lcdc_0>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -555,11 +555,11 @@
|
|||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "host";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
|
|
|
|||
|
|
@ -23,28 +23,28 @@
|
|||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
usr0 {
|
||||
led-usr0 {
|
||||
label = "beaglebone:green:usr0";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
usr1 {
|
||||
led-usr1 {
|
||||
label = "beaglebone:green:usr1";
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
usr2 {
|
||||
led-usr2 {
|
||||
label = "beaglebone:green:usr2";
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
usr3 {
|
||||
led-usr3 {
|
||||
label = "beaglebone:green:usr3";
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
|
|
|
|||
|
|
@ -26,12 +26,12 @@
|
|||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vmmc_fixed: vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
vmmc_fixed: vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
|
|
@ -150,7 +150,7 @@
|
|||
enable-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* gpio_182 */
|
||||
};
|
||||
|
||||
pwm11: dmtimer-pwm@11 {
|
||||
pwm11: pwm-11 {
|
||||
compatible = "ti,omap-dmtimer-pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm_pins>;
|
||||
|
|
@ -176,7 +176,7 @@
|
|||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dss {
|
||||
|
|
@ -227,7 +227,7 @@
|
|||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
|
|
|
|||
|
|
@ -49,13 +49,35 @@
|
|||
};
|
||||
|
||||
ocp@68000000 {
|
||||
am35x_otg_hs: am35x_otg_hs@5c040000 {
|
||||
compatible = "ti,omap3-musb";
|
||||
ti,hwmods = "am35x_otg_hs";
|
||||
status = "disabled";
|
||||
reg = <0x5c040000 0x1000>;
|
||||
interrupts = <71>;
|
||||
interrupt-names = "mc";
|
||||
target-module@5c040000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x5c040400 0x4>,
|
||||
<0x5c040404 0x4>,
|
||||
<0x5c040408 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&hsotgusb_ick_am35xx>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x5c040000 0x1000>;
|
||||
|
||||
am35x_otg_hs: am35x_otg_hs@0 {
|
||||
compatible = "ti,omap3-musb";
|
||||
status = "disabled";
|
||||
reg = <0 0x1000>;
|
||||
interrupts = <71>;
|
||||
interrupt-names = "mc";
|
||||
};
|
||||
};
|
||||
|
||||
davinci_emac: ethernet@5c000000 {
|
||||
|
|
@ -154,7 +176,7 @@
|
|||
};
|
||||
|
||||
/* Table Table 5-79 of the TRM shows 480ab000 is reserved */
|
||||
&usb_otg_hs {
|
||||
&usb_otg_target {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -452,7 +452,7 @@
|
|||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
|
|
|
|||
|
|
@ -763,7 +763,7 @@
|
|||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
|
|
|
|||
|
|
@ -919,7 +919,7 @@
|
|||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
reg = <0x00000000 0x00080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
|
|
|
|||
|
|
@ -542,7 +542,7 @@
|
|||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.SPL";
|
||||
reg = <0x00000000 0x000040000>;
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.u-boot";
|
||||
|
|
|
|||
|
|
@ -86,19 +86,19 @@
|
|||
|
||||
pinctrl-names = "default";
|
||||
|
||||
sata-r-amber-pin {
|
||||
led-sata-r-amber {
|
||||
label = "dns327l:amber:sata-r";
|
||||
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
sata-l-amber-pin {
|
||||
led-sata-l-amber {
|
||||
label = "dns327l:amber:sata-l";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
backup-led-pin {
|
||||
led-backup {
|
||||
label = "dns327l:white:usb";
|
||||
gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "keep";
|
||||
|
|
|
|||
|
|
@ -85,11 +85,11 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <8192>;
|
||||
};
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <8192>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
|
|
|||
|
|
@ -94,11 +94,11 @@
|
|||
};
|
||||
|
||||
clocks {
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <8192>;
|
||||
};
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <8192>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
|
|
|
|||
|
|
@ -61,8 +61,8 @@
|
|||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -155,18 +155,18 @@
|
|||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
|
|
|
|||
|
|
@ -72,11 +72,11 @@
|
|||
};
|
||||
|
||||
gpio-leds {
|
||||
red-sata2 {
|
||||
led-red-sata2 {
|
||||
label = "dart:red:sata2";
|
||||
gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
red-sata3 {
|
||||
led-red-sata3 {
|
||||
label = "dart:red:sata3";
|
||||
gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -132,21 +132,21 @@
|
|||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
white-power {
|
||||
led-white-power {
|
||||
label = "dart:white:power";
|
||||
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "timer";
|
||||
|
||||
};
|
||||
red-power {
|
||||
led-red-power {
|
||||
label = "dart:red:power";
|
||||
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
red-sata0 {
|
||||
led-red-sata0 {
|
||||
label = "dart:red:sata0";
|
||||
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
red-sata1 {
|
||||
led-red-sata1 {
|
||||
label = "dart:red:sata1";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@
|
|||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
red-sata0 {
|
||||
led-red-sata0 {
|
||||
label = "cumulus:red:sata0";
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
|
|
|
|||
|
|
@ -91,9 +91,9 @@
|
|||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
|
|
|
|||
|
|
@ -84,7 +84,7 @@
|
|||
|
||||
pcie2: pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
assigned-addresses = <0x82001000 0 0x80000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -592,7 +592,7 @@
|
|||
|
||||
pcie1: pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@
|
|||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -118,7 +118,7 @@
|
|||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -62,11 +62,11 @@
|
|||
};
|
||||
|
||||
&gpio_leds {
|
||||
power {
|
||||
led-power {
|
||||
label = "caiman:white:power";
|
||||
};
|
||||
|
||||
sata {
|
||||
led-sata {
|
||||
label = "caiman:white:sata";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -62,11 +62,11 @@
|
|||
};
|
||||
|
||||
&gpio_leds {
|
||||
power {
|
||||
led-power {
|
||||
label = "cobra:white:power";
|
||||
};
|
||||
|
||||
sata {
|
||||
led-sata {
|
||||
label = "cobra:white:sata";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -54,22 +54,22 @@
|
|||
};
|
||||
|
||||
&gpio_leds {
|
||||
power {
|
||||
led-power {
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
label = "rango:white:power";
|
||||
};
|
||||
|
||||
sata {
|
||||
led-sata {
|
||||
gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
|
||||
label = "rango:white:sata";
|
||||
};
|
||||
|
||||
wlan_2g {
|
||||
led-wlan_2g {
|
||||
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
|
||||
label = "rango:white:wlan_2g";
|
||||
};
|
||||
|
||||
wlan_5g {
|
||||
led-wlan_5g {
|
||||
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
||||
label = "rango:white:wlan_5g";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -62,11 +62,11 @@
|
|||
};
|
||||
|
||||
&gpio_leds {
|
||||
power {
|
||||
led-power {
|
||||
label = "shelby:white:power";
|
||||
};
|
||||
|
||||
sata {
|
||||
led-sata {
|
||||
label = "shelby:white:sata";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -71,12 +71,12 @@
|
|||
pinctrl-0 = <&gpio_leds_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power {
|
||||
led-power {
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
sata {
|
||||
led-sata {
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
linux,default-trigger = "disk-activity";
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@
|
|||
* sata0, and accesses to SATA disk 0 make it blink so it
|
||||
* doesn't need to be declared here.
|
||||
*/
|
||||
orange {
|
||||
led-orange {
|
||||
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
|
||||
label = "ds116:orange:disk";
|
||||
default-state = "off";
|
||||
|
|
|
|||
|
|
@ -23,6 +23,12 @@
|
|||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
ethernet2 = ð2;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1024 MB */
|
||||
|
|
@ -483,7 +489,17 @@
|
|||
};
|
||||
};
|
||||
|
||||
/* port 6 is connected to eth0 */
|
||||
ports@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <ð0>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -93,7 +93,7 @@
|
|||
/* x1 port */
|
||||
pcie2: pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -121,7 +121,7 @@
|
|||
/* x1 port */
|
||||
pcie3: pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -152,7 +152,7 @@
|
|||
*/
|
||||
pcie4: pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
|
|
|||
|
|
@ -304,7 +304,7 @@
|
|||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
compatible = "marvell,armadaxp-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>, <0x181c0 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
|
|
@ -323,7 +323,7 @@
|
|||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,armada-370-gpio",
|
||||
compatible = "marvell,armadaxp-gpio",
|
||||
"marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>, <0x181c8 0x08>;
|
||||
reg-names = "gpio", "pwm";
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue