Merge branch 'icc-qcm2290' into icc-next
Add support for QCM2290 including a few prep changes. * icc-qcm2290 interconnect: icc-rpm: Define ICC device type interconnect: icc-rpm: Add QNOC type QoS support interconnect: icc-rpm: Support child NoC device probe dt-bindings: interconnect: Add Qualcomm QCM2290 NoC support interconnect: qcom: Add QCM2290 driver support Link: https://lore.kernel.org/r/20211215002324.1727-1-shawn.guo@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
This commit is contained in:
Georgi Djakov
commit
01f8938ad0
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@ -0,0 +1,137 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QCM2290 Network-On-Chip interconnect
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maintainers:
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- Shawn Guo <shawn.guo@linaro.org>
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description: |
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The Qualcomm QCM2290 interconnect providers support adjusting the
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bandwidth requirements between the various NoC fabrics.
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properties:
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reg:
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maxItems: 1
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compatible:
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enum:
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- qcom,qcm2290-bimc
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- qcom,qcm2290-cnoc
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- qcom,qcm2290-snoc
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'#interconnect-cells':
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const: 1
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clock-names:
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items:
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- const: bus
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- const: bus_a
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clocks:
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items:
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- description: Bus Clock
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- description: Bus A Clock
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# Child node's properties
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patternProperties:
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'^interconnect-[a-z0-9]+$':
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type: object
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description:
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The interconnect providers do not have a separate QoS register space,
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but share parent's space.
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properties:
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compatible:
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enum:
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- qcom,qcm2290-qup-virt
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- qcom,qcm2290-mmrt-virt
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- qcom,qcm2290-mmnrt-virt
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'#interconnect-cells':
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const: 1
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clock-names:
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items:
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- const: bus
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- const: bus_a
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clocks:
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items:
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- description: Bus Clock
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- description: Bus A Clock
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required:
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- compatible
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- '#interconnect-cells'
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- clock-names
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- clocks
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additionalProperties: false
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required:
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- compatible
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- reg
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- '#interconnect-cells'
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- clock-names
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,rpmcc.h>
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snoc: interconnect@1880000 {
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compatible = "qcom,qcm2290-snoc";
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reg = <0x01880000 0x60200>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
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<&rpmcc RPM_SMD_SNOC_A_CLK>;
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qup_virt: interconnect-qup {
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compatible = "qcom,qcm2290-qup-virt";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_QUP_CLK>,
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<&rpmcc RPM_SMD_QUP_A_CLK>;
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};
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mmnrt_virt: interconnect-mmnrt {
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compatible = "qcom,qcm2290-mmnrt-virt";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_MMNRT_CLK>,
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<&rpmcc RPM_SMD_MMNRT_A_CLK>;
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};
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mmrt_virt: interconnect-mmrt {
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compatible = "qcom,qcm2290-mmrt-virt";
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_MMRT_CLK>,
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<&rpmcc RPM_SMD_MMRT_A_CLK>;
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};
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};
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cnoc: interconnect@1900000 {
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compatible = "qcom,qcm2290-cnoc";
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reg = <0x01900000 0x8200>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
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<&rpmcc RPM_SMD_CNOC_A_CLK>;
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};
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bimc: interconnect@4480000 {
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compatible = "qcom,qcm2290-bimc";
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reg = <0x04480000 0x80000>;
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#interconnect-cells = <1>;
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clock-names = "bus", "bus_a";
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clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
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<&rpmcc RPM_SMD_BIMC_A_CLK>;
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};
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@ -51,6 +51,15 @@ config INTERCONNECT_QCOM_OSM_L3
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Say y here to support the Operating State Manager (OSM) interconnect
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driver which controls the scaling of L3 caches on Qualcomm SoCs.
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config INTERCONNECT_QCOM_QCM2290
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tristate "Qualcomm QCM2290 interconnect driver"
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depends on INTERCONNECT_QCOM
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depends on QCOM_SMD_RPM
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select INTERCONNECT_QCOM_SMD_RPM
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help
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This is a driver for the Qualcomm Network-on-Chip on qcm2290-based
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platforms.
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config INTERCONNECT_QCOM_QCS404
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tristate "Qualcomm QCS404 interconnect driver"
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depends on INTERCONNECT_QCOM
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|
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@ -6,6 +6,7 @@ qnoc-msm8939-objs := msm8939.o
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qnoc-msm8974-objs := msm8974.o
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qnoc-msm8996-objs := msm8996.o
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icc-osm-l3-objs := osm-l3.o
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qnoc-qcm2290-objs := qcm2290.o
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qnoc-qcs404-objs := qcs404.o
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icc-rpmh-obj := icc-rpmh.o
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qnoc-sc7180-objs := sc7180.o
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@ -26,6 +27,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8939) += qnoc-msm8939.o
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
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obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) += qnoc-msm8996.o
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obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
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obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) += qnoc-qcm2290.o
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obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
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obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
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obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
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@ -18,6 +18,13 @@
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#include "smd-rpm.h"
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#include "icc-rpm.h"
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/* QNOC QoS */
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#define QNOC_QOS_MCTL_LOWn_ADDR(n) (0x8 + (n * 0x1000))
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#define QNOC_QOS_MCTL_DFLT_PRIO_MASK 0x70
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#define QNOC_QOS_MCTL_DFLT_PRIO_SHIFT 4
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#define QNOC_QOS_MCTL_URGFWD_EN_MASK 0x8
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#define QNOC_QOS_MCTL_URGFWD_EN_SHIFT 3
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/* BIMC QoS */
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#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n))
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#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n))
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@ -40,6 +47,27 @@
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#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
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#define NOC_QOS_MODEn_MASK 0x3
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static int qcom_icc_set_qnoc_qos(struct icc_node *src, u64 max_bw)
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{
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struct icc_provider *provider = src->provider;
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struct qcom_icc_provider *qp = to_qcom_provider(provider);
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struct qcom_icc_node *qn = src->data;
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struct qcom_icc_qos *qos = &qn->qos;
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int rc;
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rc = regmap_update_bits(qp->regmap,
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qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
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QNOC_QOS_MCTL_DFLT_PRIO_MASK,
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qos->areq_prio << QNOC_QOS_MCTL_DFLT_PRIO_SHIFT);
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if (rc)
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return rc;
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return regmap_update_bits(qp->regmap,
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qp->qos_offset + QNOC_QOS_MCTL_LOWn_ADDR(qos->qos_port),
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QNOC_QOS_MCTL_URGFWD_EN_MASK,
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!!qos->urg_fwd_en << QNOC_QOS_MCTL_URGFWD_EN_SHIFT);
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}
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static int qcom_icc_bimc_set_qos_health(struct qcom_icc_provider *qp,
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struct qcom_icc_qos *qos,
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int regnum)
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@ -164,10 +192,14 @@ static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
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dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
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if (qp->is_bimc_node)
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switch (qp->type) {
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case QCOM_ICC_BIMC:
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return qcom_icc_set_bimc_qos(node, sum_bw);
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return qcom_icc_set_noc_qos(node, sum_bw);
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case QCOM_ICC_QNOC:
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return qcom_icc_set_qnoc_qos(node, sum_bw);
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default:
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return qcom_icc_set_noc_qos(node, sum_bw);
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}
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}
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static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
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@ -309,7 +341,7 @@ int qnoc_probe(struct platform_device *pdev)
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qp->bus_clks[i].id = cds[i];
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qp->num_clks = cd_num;
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qp->is_bimc_node = desc->is_bimc_node;
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qp->type = desc->type;
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qp->qos_offset = desc->qos_offset;
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if (desc->regmap_cfg) {
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@ -317,8 +349,13 @@ int qnoc_probe(struct platform_device *pdev)
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void __iomem *mmio;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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if (!res) {
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/* Try parent's regmap */
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qp->regmap = dev_get_regmap(dev->parent, NULL);
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if (qp->regmap)
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goto regmap_done;
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return -ENODEV;
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}
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mmio = devm_ioremap_resource(dev, res);
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@ -334,6 +371,7 @@ int qnoc_probe(struct platform_device *pdev)
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}
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}
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regmap_done:
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ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
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if (ret)
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return ret;
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@ -385,6 +423,10 @@ int qnoc_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, qp);
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/* Populate child NoC devices if any */
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if (of_get_child_count(dev->of_node) > 0)
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return of_platform_populate(dev->of_node, NULL, NULL, dev);
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return 0;
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err:
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icc_nodes_remove(provider);
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|
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@ -12,19 +12,25 @@
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#define to_qcom_provider(_provider) \
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container_of(_provider, struct qcom_icc_provider, provider)
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enum qcom_icc_type {
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QCOM_ICC_NOC,
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QCOM_ICC_BIMC,
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QCOM_ICC_QNOC,
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};
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/**
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* struct qcom_icc_provider - Qualcomm specific interconnect provider
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* @provider: generic interconnect provider
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* @bus_clks: the clk_bulk_data table of bus clocks
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* @num_clks: the total number of clk_bulk_data entries
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* @is_bimc_node: indicates whether to use bimc specific setting
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* @type: the ICC provider type
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* @qos_offset: offset to QoS registers
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* @regmap: regmap for QoS registers read/write access
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*/
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struct qcom_icc_provider {
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struct icc_provider provider;
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int num_clks;
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bool is_bimc_node;
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enum qcom_icc_type type;
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struct regmap *regmap;
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unsigned int qos_offset;
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struct clk_bulk_data bus_clks[];
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@ -38,6 +44,7 @@ struct qcom_icc_provider {
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* @ap_owned: indicates if the node is owned by the AP or by the RPM
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* @qos_mode: default qos mode for this node
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* @qos_port: qos port number for finding qos registers of this node
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* @urg_fwd_en: enable urgent forwarding
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*/
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struct qcom_icc_qos {
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u32 areq_prio;
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@ -46,6 +53,7 @@ struct qcom_icc_qos {
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bool ap_owned;
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int qos_mode;
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int qos_port;
|
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bool urg_fwd_en;
|
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};
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|
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/**
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|
|
@ -78,7 +86,7 @@ struct qcom_icc_desc {
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const char * const *clocks;
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size_t num_clocks;
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bool has_bus_pd;
|
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bool is_bimc_node;
|
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enum qcom_icc_type type;
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const struct regmap_config *regmap_cfg;
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unsigned int qos_offset;
|
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};
|
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|
|
|
|||
|
|
@ -1229,6 +1229,7 @@ static const struct regmap_config msm8916_snoc_regmap_config = {
|
|||
};
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||||
|
||||
static struct qcom_icc_desc msm8916_snoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = msm8916_snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8916_snoc_nodes),
|
||||
.regmap_cfg = &msm8916_snoc_regmap_config,
|
||||
|
|
@ -1256,9 +1257,9 @@ static const struct regmap_config msm8916_bimc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc msm8916_bimc = {
|
||||
.type = QCOM_ICC_BIMC,
|
||||
.nodes = msm8916_bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8916_bimc_nodes),
|
||||
.is_bimc_node = true,
|
||||
.regmap_cfg = &msm8916_bimc_regmap_config,
|
||||
.qos_offset = 0x8000,
|
||||
};
|
||||
|
|
@ -1325,6 +1326,7 @@ static const struct regmap_config msm8916_pcnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc msm8916_pcnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = msm8916_pcnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes),
|
||||
.regmap_cfg = &msm8916_pcnoc_regmap_config,
|
||||
|
|
|
|||
|
|
@ -1282,6 +1282,7 @@ static const struct regmap_config msm8939_snoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc msm8939_snoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = msm8939_snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8939_snoc_nodes),
|
||||
.regmap_cfg = &msm8939_snoc_regmap_config,
|
||||
|
|
@ -1309,6 +1310,7 @@ static const struct regmap_config msm8939_snoc_mm_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc msm8939_snoc_mm = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = msm8939_snoc_mm_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8939_snoc_mm_nodes),
|
||||
.regmap_cfg = &msm8939_snoc_mm_regmap_config,
|
||||
|
|
@ -1336,9 +1338,9 @@ static const struct regmap_config msm8939_bimc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc msm8939_bimc = {
|
||||
.type = QCOM_ICC_BIMC,
|
||||
.nodes = msm8939_bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8939_bimc_nodes),
|
||||
.is_bimc_node = true,
|
||||
.regmap_cfg = &msm8939_bimc_regmap_config,
|
||||
.qos_offset = 0x8000,
|
||||
};
|
||||
|
|
@ -1407,6 +1409,7 @@ static const struct regmap_config msm8939_pcnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc msm8939_pcnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = msm8939_pcnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(msm8939_pcnoc_nodes),
|
||||
.regmap_cfg = &msm8939_pcnoc_regmap_config,
|
||||
|
|
|
|||
|
|
@ -1811,6 +1811,7 @@ static const struct regmap_config msm8996_a0noc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_a0noc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = a0noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(a0noc_nodes),
|
||||
.clocks = bus_a0noc_clocks,
|
||||
|
|
@ -1834,6 +1835,7 @@ static const struct regmap_config msm8996_a1noc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_a1noc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = a1noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(a1noc_nodes),
|
||||
.regmap_cfg = &msm8996_a1noc_regmap_config
|
||||
|
|
@ -1854,6 +1856,7 @@ static const struct regmap_config msm8996_a2noc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_a2noc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = a2noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(a2noc_nodes),
|
||||
.regmap_cfg = &msm8996_a2noc_regmap_config
|
||||
|
|
@ -1879,9 +1882,9 @@ static const struct regmap_config msm8996_bimc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_bimc = {
|
||||
.type = QCOM_ICC_BIMC,
|
||||
.nodes = bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(bimc_nodes),
|
||||
.is_bimc_node = true,
|
||||
.regmap_cfg = &msm8996_bimc_regmap_config
|
||||
};
|
||||
|
||||
|
|
@ -1937,6 +1940,7 @@ static const struct regmap_config msm8996_cnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_cnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = cnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(cnoc_nodes),
|
||||
.regmap_cfg = &msm8996_cnoc_regmap_config
|
||||
|
|
@ -1989,6 +1993,7 @@ static const struct regmap_config msm8996_mnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_mnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = mnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(mnoc_nodes),
|
||||
.clocks = bus_mm_clocks,
|
||||
|
|
@ -2026,6 +2031,7 @@ static const struct regmap_config msm8996_pnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_pnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = pnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(pnoc_nodes),
|
||||
.regmap_cfg = &msm8996_pnoc_regmap_config
|
||||
|
|
@ -2069,6 +2075,7 @@ static const struct regmap_config msm8996_snoc_regmap_config = {
|
|||
};
|
||||
|
||||
static const struct qcom_icc_desc msm8996_snoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(snoc_nodes),
|
||||
.regmap_cfg = &msm8996_snoc_regmap_config
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1513,6 +1513,7 @@ static const struct regmap_config sdm660_a2noc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_a2noc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = sdm660_a2noc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
|
||||
.clocks = bus_a2noc_clocks,
|
||||
|
|
@ -1540,9 +1541,9 @@ static const struct regmap_config sdm660_bimc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_bimc = {
|
||||
.type = QCOM_ICC_BIMC,
|
||||
.nodes = sdm660_bimc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
|
||||
.is_bimc_node = true,
|
||||
.regmap_cfg = &sdm660_bimc_regmap_config,
|
||||
};
|
||||
|
||||
|
|
@ -1594,6 +1595,7 @@ static const struct regmap_config sdm660_cnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_cnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = sdm660_cnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
|
||||
.regmap_cfg = &sdm660_cnoc_regmap_config,
|
||||
|
|
@ -1614,6 +1616,7 @@ static const struct regmap_config sdm660_gnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_gnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = sdm660_gnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
|
||||
.regmap_cfg = &sdm660_gnoc_regmap_config,
|
||||
|
|
@ -1653,6 +1656,7 @@ static const struct regmap_config sdm660_mnoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_mnoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = sdm660_mnoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
|
||||
.clocks = bus_mm_clocks,
|
||||
|
|
@ -1689,6 +1693,7 @@ static const struct regmap_config sdm660_snoc_regmap_config = {
|
|||
};
|
||||
|
||||
static struct qcom_icc_desc sdm660_snoc = {
|
||||
.type = QCOM_ICC_NOC,
|
||||
.nodes = sdm660_snoc_nodes,
|
||||
.num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
|
||||
.regmap_cfg = &sdm660_snoc_regmap_config,
|
||||
|
|
|
|||
|
|
@ -0,0 +1,94 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* QCM2290 interconnect IDs */
|
||||
|
||||
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H
|
||||
#define __DT_BINDINGS_INTERCONNECT_QCOM_QCM2290_H
|
||||
|
||||
/* BIMC */
|
||||
#define MASTER_APPSS_PROC 0
|
||||
#define MASTER_SNOC_BIMC_RT 1
|
||||
#define MASTER_SNOC_BIMC_NRT 2
|
||||
#define MASTER_SNOC_BIMC 3
|
||||
#define MASTER_TCU_0 4
|
||||
#define MASTER_GFX3D 5
|
||||
#define SLAVE_EBI1 6
|
||||
#define SLAVE_BIMC_SNOC 7
|
||||
|
||||
/* CNOC */
|
||||
#define MASTER_SNOC_CNOC 0
|
||||
#define MASTER_QDSS_DAP 1
|
||||
#define SLAVE_BIMC_CFG 2
|
||||
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 3
|
||||
#define SLAVE_CAMERA_RT_THROTTLE_CFG 4
|
||||
#define SLAVE_CAMERA_CFG 5
|
||||
#define SLAVE_CLK_CTL 6
|
||||
#define SLAVE_CRYPTO_0_CFG 7
|
||||
#define SLAVE_DISPLAY_CFG 8
|
||||
#define SLAVE_DISPLAY_THROTTLE_CFG 9
|
||||
#define SLAVE_GPU_CFG 10
|
||||
#define SLAVE_HWKM 11
|
||||
#define SLAVE_IMEM_CFG 12
|
||||
#define SLAVE_IPA_CFG 13
|
||||
#define SLAVE_LPASS 14
|
||||
#define SLAVE_MESSAGE_RAM 15
|
||||
#define SLAVE_PDM 16
|
||||
#define SLAVE_PIMEM_CFG 17
|
||||
#define SLAVE_PKA_WRAPPER 18
|
||||
#define SLAVE_PMIC_ARB 19
|
||||
#define SLAVE_PRNG 20
|
||||
#define SLAVE_QDSS_CFG 21
|
||||
#define SLAVE_QM_CFG 22
|
||||
#define SLAVE_QM_MPU_CFG 23
|
||||
#define SLAVE_QPIC 24
|
||||
#define SLAVE_QUP_0 25
|
||||
#define SLAVE_SDCC_1 26
|
||||
#define SLAVE_SDCC_2 27
|
||||
#define SLAVE_SNOC_CFG 28
|
||||
#define SLAVE_TCSR 29
|
||||
#define SLAVE_USB3 30
|
||||
#define SLAVE_VENUS_CFG 31
|
||||
#define SLAVE_VENUS_THROTTLE_CFG 32
|
||||
#define SLAVE_VSENSE_CTRL_CFG 33
|
||||
#define SLAVE_SERVICE_CNOC 34
|
||||
|
||||
/* SNOC */
|
||||
#define MASTER_CRYPTO_CORE0 0
|
||||
#define MASTER_SNOC_CFG 1
|
||||
#define MASTER_TIC 2
|
||||
#define MASTER_ANOC_SNOC 3
|
||||
#define MASTER_BIMC_SNOC 4
|
||||
#define MASTER_PIMEM 5
|
||||
#define MASTER_QDSS_BAM 6
|
||||
#define MASTER_QUP_0 7
|
||||
#define MASTER_IPA 8
|
||||
#define MASTER_QDSS_ETR 9
|
||||
#define MASTER_SDCC_1 10
|
||||
#define MASTER_SDCC_2 11
|
||||
#define MASTER_QPIC 12
|
||||
#define MASTER_USB3_0 13
|
||||
#define SLAVE_APPSS 14
|
||||
#define SLAVE_SNOC_CNOC 15
|
||||
#define SLAVE_IMEM 16
|
||||
#define SLAVE_PIMEM 17
|
||||
#define SLAVE_SNOC_BIMC 18
|
||||
#define SLAVE_SERVICE_SNOC 19
|
||||
#define SLAVE_QDSS_STM 20
|
||||
#define SLAVE_TCU 21
|
||||
#define SLAVE_ANOC_SNOC 22
|
||||
|
||||
/* QUP Virtual */
|
||||
#define MASTER_QUP_CORE_0 0
|
||||
#define SLAVE_QUP_CORE_0 1
|
||||
|
||||
/* MMNRT Virtual */
|
||||
#define MASTER_CAMNOC_SF 0
|
||||
#define MASTER_VIDEO_P0 1
|
||||
#define MASTER_VIDEO_PROC 2
|
||||
#define SLAVE_SNOC_BIMC_NRT 3
|
||||
|
||||
/* MMRT Virtual */
|
||||
#define MASTER_CAMNOC_HF 0
|
||||
#define MASTER_MDP0 1
|
||||
#define SLAVE_SNOC_BIMC_RT 2
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue