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x86: Cleanup visws interrupt handling

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Remove the open coded access to irq_desc and convert to the new irq
chip functions. Change the mask function of piix4_virtual_irq_type so
we can use the generic irq handling function for the virtual interrupt
instead of open coding it.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Thomas Gleixner 2010-09-28 14:59:58 +02:00
parent fe25c7fc2e
commit 020dd984d7
1 changed files with 42 additions and 94 deletions
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136
arch/x86/kernel/visws_quirks.c
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@ -66,10 +66,7 @@ static void __init visws_time_init(void)
}
/* Replaces the default init_ISA_irqs in the generic setup */
static void __init visws_pre_intr_init(void)
{
init_VISWS_APIC_irqs();
}
static void __init visws_pre_intr_init(void);
/* Quirk for machine specific memory setup. */
@ -429,67 +426,34 @@ static int is_co_apic(unsigned int irq)
/*
* This is the SGI Cobalt (IO-)APIC:
*/
static void enable_cobalt_irq(unsigned int irq)
static void enable_cobalt_irq(struct irq_data *data)
{
co_apic_set(is_co_apic(irq), irq);
co_apic_set(is_co_apic(data->irq), data->irq);
}
static void disable_cobalt_irq(unsigned int irq)
static void disable_cobalt_irq(struct irq_data *data)
{
int entry = is_co_apic(irq);
int entry = is_co_apic(data->irq);
co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
co_apic_read(CO_APIC_LO(entry));
}
/*
* "irq" really just serves to identify the device. Here is where we
* map this to the Cobalt APIC entry where it's physically wired.
* This is called via request_irq -> setup_irq -> irq_desc->startup()
*/
static unsigned int startup_cobalt_irq(unsigned int irq)
{
unsigned long flags;
struct irq_desc *desc = irq_to_desc(irq);
spin_lock_irqsave(&cobalt_lock, flags);
if ((desc->status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
desc->status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
enable_cobalt_irq(irq);
spin_unlock_irqrestore(&cobalt_lock, flags);
return 0;
}
static void ack_cobalt_irq(unsigned int irq)
static void ack_cobalt_irq(struct irq_data *data)
{
unsigned long flags;
spin_lock_irqsave(&cobalt_lock, flags);
disable_cobalt_irq(irq);
disable_cobalt_irq(data);
apic_write(APIC_EOI, APIC_EIO_ACK);
spin_unlock_irqrestore(&cobalt_lock, flags);
}
static void end_cobalt_irq(unsigned int irq)
{
unsigned long flags;
struct irq_desc *desc = irq_to_desc(irq);
spin_lock_irqsave(&cobalt_lock, flags);
if (!(desc->status & (IRQ_DISABLED | IRQ_INPROGRESS)))
enable_cobalt_irq(irq);
spin_unlock_irqrestore(&cobalt_lock, flags);
}
static struct irq_chip cobalt_irq_type = {
.name = "Cobalt-APIC",
.startup = startup_cobalt_irq,
.shutdown = disable_cobalt_irq,
.enable = enable_cobalt_irq,
.disable = disable_cobalt_irq,
.ack = ack_cobalt_irq,
.end = end_cobalt_irq,
.name = "Cobalt-APIC",
.irq_enable = enable_cobalt_irq,
.irq_disable = disable_cobalt_irq,
.irq_ack = ack_cobalt_irq,
};
@ -503,35 +467,34 @@ static struct irq_chip cobalt_irq_type = {
* interrupt controller type, and through a special virtual interrupt-
* controller. Device drivers only see the virtual interrupt sources.
*/
static unsigned int startup_piix4_master_irq(unsigned int irq)
static unsigned int startup_piix4_master_irq(struct irq_data *data)
{
legacy_pic->init(0);
return startup_cobalt_irq(irq);
enable_cobalt_irq(data);
}
static void end_piix4_master_irq(unsigned int irq)
static void end_piix4_master_irq(struct irq_data *data)
{
unsigned long flags;
spin_lock_irqsave(&cobalt_lock, flags);
enable_cobalt_irq(irq);
enable_cobalt_irq(data);
spin_unlock_irqrestore(&cobalt_lock, flags);
}
static struct irq_chip piix4_master_irq_type = {
.name = "PIIX4-master",
.startup = startup_piix4_master_irq,
.ack = ack_cobalt_irq,
.end = end_piix4_master_irq,
.name = "PIIX4-master",
.irq_startup = startup_piix4_master_irq,
.irq_ack = ack_cobalt_irq,
};
static void pii4_mask(struct irq_data *data) { }
static struct irq_chip piix4_virtual_irq_type = {
.name = "PIIX4-virtual",
.name = "PIIX4-virtual",
.mask = pii4_mask,
};
/*
* PIIX4-8259 master/virtual functions to handle interrupt requests
* from legacy devices: floppy, parallel, serial, rtc.
@ -549,9 +512,8 @@ static struct irq_chip piix4_virtual_irq_type = {
*/
static irqreturn_t piix4_master_intr(int irq, void *dev_id)
{
int realirq;
struct irq_desc *desc;
unsigned long flags;
int realirq;
raw_spin_lock_irqsave(&i8259A_lock, flags);
@ -592,18 +554,10 @@ static irqreturn_t piix4_master_intr(int irq, void *dev_id)
raw_spin_unlock_irqrestore(&i8259A_lock, flags);
desc = irq_to_desc(realirq);
/*
* handle this 'virtual interrupt' as a Cobalt one now.
*/
kstat_incr_irqs_this_cpu(realirq, desc);
if (likely(desc->action != NULL))
handle_IRQ_event(realirq, desc->action);
if (!(desc->status & IRQ_DISABLED))
legacy_pic->chip->unmask(realirq);
generic_handle_irq(realirq);
return IRQ_HANDLED;
@ -624,41 +578,35 @@ static struct irqaction cascade_action = {
static inline void set_piix4_virtual_irq_type(void)
{
piix4_virtual_irq_type.shutdown = i8259A_chip.mask;
piix4_virtual_irq_type.enable = i8259A_chip.unmask;
piix4_virtual_irq_type.disable = i8259A_chip.mask;
piix4_virtual_irq_type.unmask = i8259A_chip.unmask;
}
void init_VISWS_APIC_irqs(void)
static void __init visws_pre_intr_init(void)
{
int i;
set_piix4_virtual_irq_type();
for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
struct irq_desc *desc = irq_to_desc(i);
struct irq_chip *chip = NULL;
desc->status = IRQ_DISABLED;
desc->action = 0;
desc->depth = 1;
if (i == 0)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_IDE0)
chip = &cobalt_irq_type;
else if (i == CO_IRQ_IDE1)
>chip = &cobalt_irq_type;
else if (i == CO_IRQ_8259)
chip = &piix4_master_irq_type;
else if (i < CO_IRQ_APIC0)
chip = &piix4_virtual_irq_type;
else if (IS_CO_APIC(i))
chip = &cobalt_irq_type;
if (i == 0) {
desc->chip = &cobalt_irq_type;
}
else if (i == CO_IRQ_IDE0) {
desc->chip = &cobalt_irq_type;
}
else if (i == CO_IRQ_IDE1) {
desc->chip = &cobalt_irq_type;
}
else if (i == CO_IRQ_8259) {
desc->chip = &piix4_master_irq_type;
}
else if (i < CO_IRQ_APIC0) {
set_piix4_virtual_irq_type();
desc->chip = &piix4_virtual_irq_type;
}
else if (IS_CO_APIC(i)) {
desc->chip = &cobalt_irq_type;
}
if (chip)
set_irq_chip(i, chip);
}
setup_irq(CO_IRQ_8259, &master_action);