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spi: s3c64xx: Add Exynos850 support

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Add SPI port configuration for Exynos850 SoC. It has 3 USI blocks which
can be configured in SPI mode:

  * spi_0: BLK_PERI_SPI_0 (0x13940000)
  * spi_1: BLK_ALIVE_USI_CMGP00 (0x11d00000)
  * spi_2: BLK_ALIVE_USI_CMGP01 (0x11d20000)

SPI FIFO depth is 64 bytes for all those SPI blocks, so the
.fifo_lvl_mask value is set to 0x7f. All blocks have DIV_4 as the
default internal clock divider, and an internal loopback mode to run
a loopback test.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://msgid.link/r/20240120012948.8836-6-semen.protsenko@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Sam Protsenko 2024-01-19 19:29:46 -06:00 committed by Mark Brown
parent 18ab9e9e88
commit 0229278bf3
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1 changed files with 14 additions and 0 deletions
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14
drivers/spi/spi-s3c64xx.c
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@ -1460,6 +1460,17 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
};
static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
.fifo_lvl_mask = { 0x7f, 0x7f, 0x7f },
.rx_lvl_offset = 15,
.tx_st_done = 25,
.clk_div = 4,
.high_speed = true,
.clk_from_cmu = true,
.has_loopback = true,
.quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
};
static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = {
.fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f,
0x7f, 0x7f, 0x7f, 0x7f},
@ -1514,6 +1525,9 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
{ .compatible = "samsung,exynos5433-spi",
.data = (void *)&exynos5433_spi_port_config,
},
{ .compatible = "samsung,exynos850-spi",
.data = (void *)&exynos850_spi_port_config,
},
{ .compatible = "samsung,exynosautov9-spi",
.data = (void *)&exynosautov9_spi_port_config,
},