mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 11:19:37 +00:00
[ARM] S3C64XX: Add UARTdevice definitions
Add resources and information for the UART deviecs on the S3C64XX CPUs. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
parent
e1a2bd1d2f
commit
0241cbb9d6
4 changed files with 213 additions and 1 deletions
|
@ -17,6 +17,7 @@ struct s3c24xx_uart_resources {
|
|||
};
|
||||
|
||||
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
|
||||
extern struct s3c24xx_uart_resources s3c64xx_uart_resources[];
|
||||
|
||||
extern struct platform_device *s3c24xx_uart_devs[];
|
||||
extern struct platform_device *s3c24xx_uart_src[];
|
||||
|
|
|
@ -11,3 +11,5 @@ obj-n := dummy.o
|
|||
obj- :=
|
||||
|
||||
# Core files
|
||||
|
||||
obj-y += dev-uart.o
|
||||
|
|
176
arch/arm/plat-s3c64xx/dev-uart.c
Normal file
176
arch/arm/plat-s3c64xx/dev-uart.c
Normal file
|
@ -0,0 +1,176 @@
|
|||
/* linux/arch/arm/plat-s3c64xx/dev-uart.c
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* Base S3C64XX UART resource and device definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/irq.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
/* Serial port registrations */
|
||||
|
||||
/* 64xx uarts are closer together */
|
||||
|
||||
static struct resource s3c64xx_uart0_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C_PA_UART0,
|
||||
.end = S3C_PA_UART0 + 0x100,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_S3CUART_RX0,
|
||||
.end = IRQ_S3CUART_RX0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_S3CUART_TX0,
|
||||
.end = IRQ_S3CUART_TX0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
||||
},
|
||||
[3] = {
|
||||
.start = IRQ_S3CUART_ERR0,
|
||||
.end = IRQ_S3CUART_ERR0,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
|
||||
static struct resource s3c64xx_uart1_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C_PA_UART1,
|
||||
.end = S3C_PA_UART1 + 0x100,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_S3CUART_RX1,
|
||||
.end = IRQ_S3CUART_RX1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_S3CUART_TX1,
|
||||
.end = IRQ_S3CUART_TX1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
||||
},
|
||||
[3] = {
|
||||
.start = IRQ_S3CUART_ERR1,
|
||||
.end = IRQ_S3CUART_ERR1,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource s3c6xx_uart2_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C_PA_UART2,
|
||||
.end = S3C_PA_UART2 + 0x100,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_S3CUART_RX2,
|
||||
.end = IRQ_S3CUART_RX2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_S3CUART_TX2,
|
||||
.end = IRQ_S3CUART_TX2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
||||
},
|
||||
[3] = {
|
||||
.start = IRQ_S3CUART_ERR2,
|
||||
.end = IRQ_S3CUART_ERR2,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource s3c64xx_uart3_resource[] = {
|
||||
[0] = {
|
||||
.start = S3C_PA_UART3,
|
||||
.end = S3C_PA_UART3 + 0x100,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_S3CUART_RX3,
|
||||
.end = IRQ_S3CUART_RX3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = IRQ_S3CUART_TX3,
|
||||
.end = IRQ_S3CUART_TX3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
|
||||
},
|
||||
[3] = {
|
||||
.start = IRQ_S3CUART_ERR3,
|
||||
.end = IRQ_S3CUART_ERR3,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = {
|
||||
[0] = {
|
||||
.resources = s3c64xx_uart0_resource,
|
||||
.nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource),
|
||||
},
|
||||
[1] = {
|
||||
.resources = s3c64xx_uart1_resource,
|
||||
.nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource),
|
||||
},
|
||||
[2] = {
|
||||
.resources = s3c6xx_uart2_resource,
|
||||
.nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource),
|
||||
},
|
||||
[3] = {
|
||||
.resources = s3c64xx_uart3_resource,
|
||||
.nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource),
|
||||
},
|
||||
};
|
||||
|
||||
/* uart devices */
|
||||
|
||||
static struct platform_device s3c24xx_uart_device0 = {
|
||||
.id = 0,
|
||||
};
|
||||
|
||||
static struct platform_device s3c24xx_uart_device1 = {
|
||||
.id = 1,
|
||||
};
|
||||
|
||||
static struct platform_device s3c24xx_uart_device2 = {
|
||||
.id = 2,
|
||||
};
|
||||
|
||||
static struct platform_device s3c24xx_uart_device3 = {
|
||||
.id = 3,
|
||||
};
|
||||
|
||||
struct platform_device *s3c24xx_uart_src[4] = {
|
||||
&s3c24xx_uart_device0,
|
||||
&s3c24xx_uart_device1,
|
||||
&s3c24xx_uart_device2,
|
||||
&s3c24xx_uart_device3,
|
||||
};
|
||||
|
||||
struct platform_device *s3c24xx_uart_devs[4] = {
|
||||
};
|
||||
|
|
@ -15,12 +15,45 @@
|
|||
* the ISA space, so that the PC104 has them to itself
|
||||
* and we don't end up having to do horrible things to the
|
||||
* standard ISA drivers....
|
||||
*
|
||||
* note, since we're using the VICs, our start must be a
|
||||
* mulitple of 32 to allow the common code to work
|
||||
*/
|
||||
|
||||
#define S3C_IRQ_OFFSET (16)
|
||||
#define S3C_IRQ_OFFSET (32)
|
||||
|
||||
#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
|
||||
|
||||
/* UART interrupts, each UART has 4 intterupts per channel so
|
||||
* use the space between the ISA and S3C main interrupts. Note, these
|
||||
* are not in the same order as the S3C24XX series! */
|
||||
|
||||
#define IRQ_S3CUART_BASE0 (16)
|
||||
#define IRQ_S3CUART_BASE1 (20)
|
||||
#define IRQ_S3CUART_BASE2 (24)
|
||||
#define IRQ_S3CUART_BASE3 (28)
|
||||
|
||||
#define UART_IRQ_RXD (0)
|
||||
#define UART_IRQ_ERR (1)
|
||||
#define UART_IRQ_TXD (2)
|
||||
#define UART_IRQ_MODEM (3)
|
||||
|
||||
#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
|
||||
#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
|
||||
#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
|
||||
|
||||
#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
|
||||
#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
|
||||
#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
|
||||
|
||||
#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
|
||||
#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
|
||||
#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
|
||||
|
||||
#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
|
||||
#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
|
||||
#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
|
||||
|
||||
/* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series
|
||||
* we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE
|
||||
* which we place after the pair of VICs. */
|
||||
|
|
Loading…
Reference in a new issue