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drm: mali-dp: Enable image enhancement when scaling
Apply image enhacement when we are upscaling by a factor of 2 or more in either direction. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
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parent
28ce675b74
commit
0274e6a0ba
4 changed files with 42 additions and 1 deletions
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@ -288,6 +288,9 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
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if (!(h_upscale_factor >> 16) || !(v_upscale_factor >> 16))
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return -EINVAL;
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s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
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(v_upscale_factor >> 16) >= 2);
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s->input_w = pstate->src_w >> 16;
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s->input_h = pstate->src_h >> 16;
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s->output_w = pstate->crtc_w;
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@ -530,9 +533,11 @@ int malidp_crtc_init(struct drm_device *drm)
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drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
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drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
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/* No inverse-gamma: it is per-plane */
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/* No inverse-gamma: it is per-plane. */
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drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
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malidp_se_set_enh_coeffs(malidp->dev);
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return 0;
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crtc_cleanup_planes:
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@ -138,6 +138,9 @@ static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
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val = malidp_hw_read(hwdev, se_control);
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val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
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val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
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val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
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val |= MALIDP_SE_RGBO_IF_EN;
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malidp_hw_write(hwdev, val, se_control);
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@ -71,6 +71,7 @@ enum malidp_scaling_coeff_set {
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struct malidp_se_config {
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u8 scale_enable : 1;
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u8 enhancer_enable : 1;
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u8 hcoeff : 3;
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u8 vcoeff : 3;
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u8 plane_src_id;
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@ -295,6 +296,25 @@ malidp_se_select_coeffs(u32 upscale_factor)
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#undef FP_0_50000
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#undef FP_0_66667
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#undef FP_1_00000
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static inline void malidp_se_set_enh_coeffs(struct malidp_hw_device *hwdev)
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{
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static const s32 enhancer_coeffs[] = {
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-8, -8, -8, -8, 128, -8, -8, -8, -8
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};
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u32 val = MALIDP_SE_SET_ENH_LIMIT_LOW(MALIDP_SE_ENH_LOW_LEVEL) |
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MALIDP_SE_SET_ENH_LIMIT_HIGH(MALIDP_SE_ENH_HIGH_LEVEL);
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u32 image_enh = hwdev->map.se_base +
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((hwdev->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
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0x10 : 0xC) + MALIDP_SE_IMAGE_ENH;
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u32 enh_coeffs = image_enh + MALIDP_SE_ENH_COEFF0;
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int i;
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malidp_hw_write(hwdev, val, image_enh);
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for (i = 0; i < ARRAY_SIZE(enhancer_coeffs); ++i)
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malidp_hw_write(hwdev, enhancer_coeffs[i], enh_coeffs + i * 4);
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}
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/*
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* background color components are defined as 12bits values,
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* they will be shifted right when stored on hardware that
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@ -109,6 +109,8 @@
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/* Scaling engine registers and masks. */
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#define MALIDP_SE_SCALING_EN (1 << 0)
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#define MALIDP_SE_ALPHA_EN (1 << 1)
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#define MALIDP_SE_ENH_MASK 3
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#define MALIDP_SE_ENH(x) (((x) & MALIDP_SE_ENH_MASK) << 2)
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#define MALIDP_SE_RGBO_IF_EN (1 << 4)
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#define MALIDP550_SE_CTL_SEL_MASK 7
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#define MALIDP550_SE_CTL_VCSEL(x) \
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@ -139,6 +141,17 @@
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#define MALIDP_SE_COEFFTAB_DATA_MASK 0x3fff
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#define MALIDP_SE_SET_COEFFTAB_DATA(x) \
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((x) & MALIDP_SE_COEFFTAB_DATA_MASK)
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/* Enhance coeffents reigster offset */
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#define MALIDP_SE_IMAGE_ENH 0x3C
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/* ENH_LIMITS offset 0x0 */
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#define MALIDP_SE_ENH_LOW_LEVEL 24
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#define MALIDP_SE_ENH_HIGH_LEVEL 63
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#define MALIDP_SE_ENH_LIMIT_MASK 0xfff
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#define MALIDP_SE_SET_ENH_LIMIT_LOW(x) \
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((x) & MALIDP_SE_ENH_LIMIT_MASK)
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#define MALIDP_SE_SET_ENH_LIMIT_HIGH(x) \
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(((x) & MALIDP_SE_ENH_LIMIT_MASK) << 16)
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#define MALIDP_SE_ENH_COEFF0 0x04
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/* register offsets and bits specific to DP500 */
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#define MALIDP500_ADDR_SPACE_SIZE 0x01000
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