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arm64: dts: imx8mp: Sort AIPS4 nodes
Sort AIPS4 nodes by node unit-address . No functional change . Suggested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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d8f9d81265
commit
0275a47183
1 changed files with 102 additions and 102 deletions
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@ -1332,6 +1332,108 @@ aips4: bus@32c00000 {
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#size-cells = <1>;
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ranges;
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isi_0: isi@32e00000 {
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compatible = "fsl,imx8mp-isi";
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reg = <0x32e00000 0x4000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
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clock-names = "axi", "apb";
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fsl,blk-ctrl = <&media_blk_ctrl>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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isi_in_0: endpoint {
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remote-endpoint = <&mipi_csi_0_out>;
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};
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};
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port@1 {
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reg = <1>;
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isi_in_1: endpoint {
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remote-endpoint = <&mipi_csi_1_out>;
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};
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};
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};
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};
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mipi_csi_0: csi@32e40000 {
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compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
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reg = <0x32e40000 0x10000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
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clock-names = "pclk", "wrap", "phy", "axi";
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assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
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assigned-clock-rates = <500000000>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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mipi_csi_0_out: endpoint {
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remote-endpoint = <&isi_in_0>;
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};
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};
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};
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};
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mipi_csi_1: csi@32e50000 {
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compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
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reg = <0x32e50000 0x10000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <266000000>;
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
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clock-names = "pclk", "wrap", "phy", "axi";
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assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
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assigned-clock-rates = <266000000>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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mipi_csi_1_out: endpoint {
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remote-endpoint = <&isi_in_1>;
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};
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};
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};
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};
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mipi_dsi: dsi@32e60000 {
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compatible = "fsl,imx8mp-mipi-dsim";
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reg = <0x32e60000 0x400>;
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@ -1500,108 +1602,6 @@ ldb_lvds_ch1: endpoint {
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};
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};
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isi_0: isi@32e00000 {
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compatible = "fsl,imx8mp-isi";
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reg = <0x32e00000 0x4000>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
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clock-names = "axi", "apb";
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fsl,blk-ctrl = <&media_blk_ctrl>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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isi_in_0: endpoint {
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remote-endpoint = <&mipi_csi_0_out>;
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};
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};
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port@1 {
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reg = <1>;
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isi_in_1: endpoint {
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remote-endpoint = <&mipi_csi_1_out>;
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};
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};
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};
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};
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mipi_csi_0: csi@32e40000 {
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compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
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reg = <0x32e40000 0x10000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <500000000>;
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
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clock-names = "pclk", "wrap", "phy", "axi";
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assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
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assigned-clock-rates = <500000000>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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mipi_csi_0_out: endpoint {
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remote-endpoint = <&isi_in_0>;
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};
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};
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};
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};
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mipi_csi_1: csi@32e50000 {
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compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
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reg = <0x32e50000 0x10000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <266000000>;
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clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
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<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
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clock-names = "pclk", "wrap", "phy", "axi";
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assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
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assigned-clock-rates = <266000000>;
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power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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port@1 {
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reg = <1>;
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mipi_csi_1_out: endpoint {
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remote-endpoint = <&isi_in_1>;
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};
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};
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};
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};
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pcie_phy: pcie-phy@32f00000 {
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compatible = "fsl,imx8mp-pcie-phy";
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reg = <0x32f00000 0x10000>;
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