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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-24 17:59:32 +00:00
drm/i915: Stop requiring PLL index == PLL ID
There's no good reason to keep around this PLL index == PLL ID footgun. Get rid of it. Both i915->shared_dplls[] and state->shared_dpll[] are indexed by the same thing now, which is just the index we get at initialization from dpll_mgr->dpll_info[]. The rest is all about PLL IDs now. v2: Add pll->index to mimic drm_crtc & co. Remove the comment saying ID should match the index v3: s/i/pll->index/ in debugfs loop (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231003200620.11633-2-ville.syrjala@linux.intel.com
This commit is contained in:
parent
079d0b01bc
commit
027c570177
4 changed files with 48 additions and 32 deletions
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@ -656,8 +656,8 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
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for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
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struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
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seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
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pll->info->id);
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seq_printf(m, "DPLL%i: %s, id: %i\n", pll->index,
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pll->info->name, pll->info->id);
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seq_printf(m, " pipe_mask: 0x%x, active: 0x%x, on: %s\n",
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pll->state.pipe_mask, pll->active_mask,
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str_yes_no(pll->on));
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@ -115,13 +115,13 @@ static void
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intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
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struct intel_shared_dpll_state *shared_dpll)
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{
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enum intel_dpll_id i;
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int i;
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/* Copy shared dpll state */
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for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
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struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
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shared_dpll[i] = pll->state;
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shared_dpll[pll->index] = pll->state;
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}
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}
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@ -154,7 +154,17 @@ struct intel_shared_dpll *
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intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
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enum intel_dpll_id id)
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{
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return &dev_priv->display.dpll.shared_dplls[id];
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int i;
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for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
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struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
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if (pll->info->id == id)
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return pll;
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}
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MISSING_CASE(id);
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return NULL;
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}
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/* For ILK+ */
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@ -311,32 +321,36 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
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unsigned long dpll_mask)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll, *unused_pll = NULL;
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struct intel_shared_dpll_state *shared_dpll;
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enum intel_dpll_id i;
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struct intel_shared_dpll *unused_pll = NULL;
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enum intel_dpll_id id;
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shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
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drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
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for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
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pll = &dev_priv->display.dpll.shared_dplls[i];
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for_each_set_bit(id, &dpll_mask, I915_NUM_PLLS) {
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struct intel_shared_dpll *pll;
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pll = intel_get_shared_dpll_by_id(dev_priv, id);
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if (!pll)
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continue;
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/* Only want to check enabled timings first */
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if (shared_dpll[i].pipe_mask == 0) {
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if (shared_dpll[pll->index].pipe_mask == 0) {
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if (!unused_pll)
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unused_pll = pll;
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continue;
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}
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if (memcmp(pll_state,
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&shared_dpll[i].hw_state,
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&shared_dpll[pll->index].hw_state,
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sizeof(*pll_state)) == 0) {
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drm_dbg_kms(&dev_priv->drm,
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"[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
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crtc->base.base.id, crtc->base.name,
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pll->info->name,
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shared_dpll[i].pipe_mask,
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shared_dpll[pll->index].pipe_mask,
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pll->active_mask);
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return pll;
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}
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@ -383,14 +397,13 @@ intel_reference_shared_dpll(struct intel_atomic_state *state,
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const struct intel_dpll_hw_state *pll_state)
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{
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struct intel_shared_dpll_state *shared_dpll;
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const enum intel_dpll_id id = pll->info->id;
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shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
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if (shared_dpll[id].pipe_mask == 0)
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shared_dpll[id].hw_state = *pll_state;
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if (shared_dpll[pll->index].pipe_mask == 0)
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shared_dpll[pll->index].hw_state = *pll_state;
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intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]);
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intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
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}
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/**
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@ -421,11 +434,10 @@ static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
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const struct intel_shared_dpll *pll)
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{
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struct intel_shared_dpll_state *shared_dpll;
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const enum intel_dpll_id id = pll->info->id;
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shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
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intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]);
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intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[pll->index]);
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}
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static void intel_put_dpll(struct intel_atomic_state *state,
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@ -459,16 +471,15 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
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enum intel_dpll_id i;
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int i;
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if (!state->dpll_set)
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return;
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for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
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struct intel_shared_dpll *pll =
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&dev_priv->display.dpll.shared_dplls[i];
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struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
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swap(pll->state, shared_dpll[i]);
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swap(pll->state, shared_dpll[pll->index]);
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}
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}
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@ -559,12 +570,12 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
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intel_atomic_get_new_crtc_state(state, crtc);
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struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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struct intel_shared_dpll *pll;
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enum intel_dpll_id i;
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enum intel_dpll_id id;
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if (HAS_PCH_IBX(dev_priv)) {
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/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
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i = (enum intel_dpll_id) crtc->pipe;
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pll = &dev_priv->display.dpll.shared_dplls[i];
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id = (enum intel_dpll_id) crtc->pipe;
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pll = intel_get_shared_dpll_by_id(dev_priv, id);
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drm_dbg_kms(&dev_priv->drm,
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"[CRTC:%d:%s] using pre-allocated %s\n",
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@ -4168,10 +4179,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
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else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
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dpll_mgr = &pch_pll_mgr;
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if (!dpll_mgr) {
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dev_priv->display.dpll.num_shared_dpll = 0;
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if (!dpll_mgr)
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return;
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}
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dpll_info = dpll_mgr->dpll_info;
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@ -4180,8 +4189,8 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
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i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
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break;
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drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
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dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
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dev_priv->display.dpll.shared_dplls[i].index = i;
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}
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dev_priv->display.dpll.mgr = dpll_mgr;
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@ -262,8 +262,7 @@ struct dpll_info {
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const struct intel_shared_dpll_funcs *funcs;
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/**
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* @id: unique indentifier for this DPLL; should match the index in the
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* dev_priv->shared_dplls array
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* @id: unique indentifier for this DPLL
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*/
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enum intel_dpll_id id;
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@ -290,6 +289,11 @@ struct intel_shared_dpll {
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*/
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struct intel_shared_dpll_state state;
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/**
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* @index: index for atomic state
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*/
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u8 index;
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/**
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* @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
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*/
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@ -528,7 +528,10 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
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/* Check if any DPLLs are using the SSC source */
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for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
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u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
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struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
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u32 temp;
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temp = intel_de_read(dev_priv, PCH_DPLL(pll->info->id));
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if (!(temp & DPLL_VCO_ENABLE))
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continue;
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