mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 23:58:05 +00:00
arm64: dts: qcom: sc7280: Fix up GPU SIDs
[ Upstream commit94085049fd
] GPU_SMMU SID 1 is meant for Adreno LPAC (Low Priority Async Compute). On platforms that support it (in firmware), it is necessary to describe that link, or Adreno register access will hang the board. The current settings are functionally identical, *but* due to what is likely hardcoded security policies, the secure firmware rejects them, resulting in the board hanging. To avoid that, alter the settings such that SID 0 and 1 are described separately. Fixes:96c471970b
("arm64: dts: qcom: sc7280: Add gpu support") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230926-topic-a643-v2-2-06fa3d899c0a@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
52fafbe79b
commit
028a26553e
1 changed files with 2 additions and 1 deletions
|
@ -2558,7 +2558,8 @@ gpu: gpu@3d00000 {
|
|||
"cx_mem",
|
||||
"cx_dbgc";
|
||||
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
||||
iommus = <&adreno_smmu 0 0x401>;
|
||||
iommus = <&adreno_smmu 0 0x400>,
|
||||
<&adreno_smmu 1 0x400>;
|
||||
operating-points-v2 = <&gpu_opp_table>;
|
||||
qcom,gmu = <&gmu>;
|
||||
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
|
||||
|
|
Loading…
Reference in a new issue