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cpupower: Do detect IDA (opportunistic processor performance) via cpuid
IA32-Intel Devel guide Volume 3A - 14.3.2.1 ------------------------------------------- ... Opportunistic processor performance operation can be disabled by setting bit 38 of IA32_MISC_ENABLES. This mechanism is intended for BIOS only. If IA32_MISC_ENABLES[38] is set, CPUID.06H:EAX[1] will return 0. Better detect things via cpuid, this cleans up the code a bit and the MSR parts were not working correctly anyway. Signed-off-by: Thomas Renninger <trenn@suse.de> CC: lenb@kernel.org CC: linux@dominikbrodowski.net CC: cpufreq@vger.kernel.org Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
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4 changed files with 9 additions and 41 deletions
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@ -130,6 +130,12 @@ int get_cpu_info(unsigned int cpu, struct cpupower_cpu_info *cpu_info)
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cpu_info->caps |= CPUPOWER_CAP_AMD_CBP;
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}
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if (cpu_info->vendor == X86_VENDOR_INTEL) {
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if (cpuid_level >= 6 &&
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(cpuid_eax(6) & (1 << 1)))
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cpu_info->caps |= CPUPOWER_CAP_INTEL_IDA;
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}
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if (cpu_info->vendor == X86_VENDOR_INTEL) {
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/* Intel's perf-bias MSR support */
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if (cpuid_level >= 6 && (cpuid_ecx(6) & (1 << 3)))
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@ -58,6 +58,7 @@ enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL,
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#define CPUPOWER_CAP_PERF_BIAS 0x00000008
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#define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010
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#define CPUPOWER_CAP_IS_SNB 0x00000011
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#define CPUPOWER_CAP_INTEL_IDA 0x00000012
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#define MAX_HW_PSTATES 10
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@ -115,9 +116,6 @@ extern int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val);
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extern int msr_intel_get_perf_bias(unsigned int cpu);
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extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu);
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extern int msr_intel_has_boost_support(unsigned int cpu);
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extern int msr_intel_boost_is_active(unsigned int cpu);
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/* Read/Write msr ****************************/
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/* PCI stuff ****************************/
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@ -163,11 +161,6 @@ static inline int msr_intel_get_perf_bias(unsigned int cpu)
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static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu)
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{ return 0; };
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static inline int msr_intel_has_boost_support(unsigned int cpu)
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{ return -1; };
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static inline int msr_intel_boost_is_active(unsigned int cpu)
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{ return -1; };
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/* Read/Write msr ****************************/
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static inline int cpufreq_has_boost_support(unsigned int cpu, int *support,
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@ -20,16 +20,8 @@ int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
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if (ret <= 0)
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return ret;
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*support = 1;
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} else if (cpupower_cpu_info.vendor == X86_VENDOR_INTEL) {
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ret = msr_intel_has_boost_support(cpu);
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if (ret <= 0)
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return ret;
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*support = ret;
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ret = msr_intel_boost_is_active(cpu);
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if (ret <= 0)
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return ret;
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*active = ret;
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}
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} else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
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*support = *active = 1;
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return 0;
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}
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#endif /* #if defined(__i386__) || defined(__x86_64__) */
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@ -72,29 +72,6 @@ int write_msr(int cpu, unsigned int idx, unsigned long long val)
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return -1;
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}
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int msr_intel_has_boost_support(unsigned int cpu)
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{
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unsigned long long misc_enables;
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int ret;
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ret = read_msr(cpu, MSR_IA32_MISC_ENABLES, &misc_enables);
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if (ret)
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return ret;
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return (misc_enables >> 38) & 0x1;
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}
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int msr_intel_boost_is_active(unsigned int cpu)
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{
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unsigned long long perf_status;
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int ret;
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ret = read_msr(cpu, MSR_IA32_PERF_STATUS, &perf_status);
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if (ret)
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return ret;
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return (perf_status >> 32) & 0x1;
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}
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int msr_intel_get_perf_bias(unsigned int cpu)
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{
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unsigned long long val;
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