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sh: intc - shared IPR and INTC2 controller
This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
53aba19f82
commit
02ab3f7079
4 changed files with 424 additions and 0 deletions
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@ -178,6 +178,9 @@ config CPU_HAS_PINT_IRQ
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config CPU_HAS_MASKREG_IRQ
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bool
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config CPU_HAS_INTC_IRQ
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bool
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config CPU_HAS_INTC2_IRQ
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bool
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@ -6,4 +6,5 @@ obj-y += imask.o
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obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o
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obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o
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obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o
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obj-$(CONFIG_CPU_HAS_INTC_IRQ) += intc.o
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obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o
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352
arch/sh/kernel/cpu/irq/intc.c
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352
arch/sh/kernel/cpu/irq/intc.c
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@ -0,0 +1,352 @@
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/*
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* Shared interrupt handling code for IPR and INTC2 types of IRQs.
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*
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* Copyright (C) 2007 Magnus Damm
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*
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* Based on intc2.c and ipr.c
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2005, 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#define _INTC_MK(fn, idx, bit, value) \
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((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit))
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#define _INTC_FN(h) (h >> 24)
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#define _INTC_VALUE(h) ((h >> 16) & 0xff)
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#define _INTC_IDX(h) ((h >> 8) & 0xff)
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#define _INTC_BIT(h) (h & 0xff)
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#define _INTC_PTR(desc, member, data) \
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(desc->member + _INTC_IDX(data))
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static inline struct intc_desc *get_intc_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return (void *)((char *)chip - offsetof(struct intc_desc, chip));
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}
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static inline unsigned int set_field(unsigned int value,
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unsigned int field_value,
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unsigned int width,
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unsigned int shift)
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{
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value &= ~(((1 << width) - 1) << shift);
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value |= field_value << shift;
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return value;
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}
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static inline unsigned int set_prio_field(struct intc_desc *desc,
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unsigned int value,
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unsigned int priority,
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unsigned int data)
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{
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unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width;
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return set_field(value, priority, width, _INTC_BIT(data));
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}
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static void disable_prio_16(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
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ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
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}
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static void enable_prio_16(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
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unsigned int prio = _INTC_VALUE(data);
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ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
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}
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static void disable_prio_32(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
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ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
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}
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static void enable_prio_32(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, prio_regs, data)->reg;
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unsigned int prio = _INTC_VALUE(data);
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ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
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}
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static void disable_mask_8(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outb(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->set_reg);
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}
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static void enable_mask_8(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outb(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->clr_reg);
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}
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static void disable_mask_32(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outl(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->set_reg);
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}
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static void enable_mask_32(struct intc_desc *desc, unsigned int data)
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{
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ctrl_outl(1 << _INTC_BIT(data),
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_INTC_PTR(desc, mask_regs, data)->clr_reg);
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}
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enum { REG_FN_ERROR=0,
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REG_FN_MASK_8, REG_FN_MASK_32,
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REG_FN_PRIO_16, REG_FN_PRIO_32 };
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static struct {
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void (*enable)(struct intc_desc *, unsigned int);
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void (*disable)(struct intc_desc *, unsigned int);
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} intc_reg_fns[] = {
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[REG_FN_MASK_8] = { enable_mask_8, disable_mask_8 },
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[REG_FN_MASK_32] = { enable_mask_32, disable_mask_32 },
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[REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
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[REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
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};
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static void intc_enable(unsigned int irq)
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{
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struct intc_desc *desc = get_intc_desc(irq);
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unsigned int data = (unsigned int) get_irq_chip_data(irq);
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intc_reg_fns[_INTC_FN(data)].enable(desc, data);
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}
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static void intc_disable(unsigned int irq)
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{
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struct intc_desc *desc = get_intc_desc(irq);
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unsigned int data = (unsigned int) get_irq_chip_data(irq);
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intc_reg_fns[_INTC_FN(data)].disable(desc, data);
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}
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static void set_sense_16(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
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unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
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unsigned int bit = _INTC_BIT(data);
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unsigned int value = _INTC_VALUE(data);
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ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr);
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}
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static void set_sense_32(struct intc_desc *desc, unsigned int data)
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{
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unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg;
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unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width;
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unsigned int bit = _INTC_BIT(data);
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unsigned int value = _INTC_VALUE(data);
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ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr);
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}
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#define VALID(x) (x | 0x80)
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static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
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[IRQ_TYPE_EDGE_FALLING] = VALID(0),
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[IRQ_TYPE_EDGE_RISING] = VALID(1),
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[IRQ_TYPE_LEVEL_LOW] = VALID(2),
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[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
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};
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static int intc_set_sense(unsigned int irq, unsigned int type)
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{
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struct intc_desc *desc = get_intc_desc(irq);
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unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
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unsigned int i, j, data, bit;
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intc_enum enum_id = 0;
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for (i = 0; i < desc->nr_vectors; i++) {
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struct intc_vect *vect = desc->vectors + i;
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if (evt2irq(vect->vect) != irq)
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continue;
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enum_id = vect->enum_id;
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break;
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}
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if (!enum_id || !value)
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return -EINVAL;
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value ^= VALID(0);
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for (i = 0; i < desc->nr_sense_regs; i++) {
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struct intc_sense_reg *sr = desc->sense_regs + i;
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for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
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if (sr->enum_ids[j] != enum_id)
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continue;
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bit = sr->reg_width - ((j + 1) * sr->field_width);
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data = _INTC_MK(0, i, bit, value);
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switch(sr->reg_width) {
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case 16:
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set_sense_16(desc, data);
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break;
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case 32:
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set_sense_32(desc, data);
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break;
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}
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return 0;
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}
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}
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return -EINVAL;
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}
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static unsigned int __init intc_find_mask_handler(unsigned int width)
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{
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switch (width) {
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case 8:
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return REG_FN_MASK_8;
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case 32:
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return REG_FN_MASK_32;
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}
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BUG();
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return REG_FN_ERROR;
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}
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static unsigned int __init intc_find_prio_handler(unsigned int width)
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{
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switch (width) {
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case 16:
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return REG_FN_PRIO_16;
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case 32:
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return REG_FN_PRIO_32;
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}
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BUG();
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return REG_FN_ERROR;
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}
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static unsigned int __init intc_prio_value(struct intc_desc *desc,
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intc_enum enum_id)
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{
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unsigned int i;
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for (i = 0; i < desc->nr_priorities; i++) {
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struct intc_prio *p = desc->priorities + i;
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if (p->enum_id != enum_id)
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continue;
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return p->priority;
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}
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return 1; /* default to the lowest priority if no priority is set */
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}
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static unsigned int __init intc_mask_data(struct intc_desc *desc,
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intc_enum enum_id)
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{
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unsigned int i, j, fn;
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for (i = 0; i < desc->nr_mask_regs; i++) {
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struct intc_mask_reg *mr = desc->mask_regs + i;
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for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
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if (mr->enum_ids[j] != enum_id)
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continue;
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fn = intc_find_mask_handler(mr->reg_width);
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if (fn == REG_FN_ERROR)
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return 0;
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return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0);
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}
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}
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return 0;
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}
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static unsigned int __init intc_prio_data(struct intc_desc *desc,
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intc_enum enum_id)
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{
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unsigned int i, j, fn, bit, prio;
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for (i = 0; i < desc->nr_prio_regs; i++) {
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struct intc_prio_reg *pr = desc->prio_regs + i;
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for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
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if (pr->enum_ids[j] != enum_id)
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continue;
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fn = intc_find_prio_handler(pr->reg_width);
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if (fn == REG_FN_ERROR)
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return 0;
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prio = intc_prio_value(desc, enum_id);
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bit = pr->reg_width - ((j + 1) * pr->field_width);
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BUG_ON(bit < 0);
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return _INTC_MK(fn, i, bit, prio);
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}
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}
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return 0;
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}
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static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
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unsigned int irq)
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{
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unsigned int mask_data = intc_mask_data(desc, enum_id);
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unsigned int prio_data = intc_prio_data(desc, enum_id);
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unsigned int data = mask_data ? mask_data : prio_data;
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BUG_ON(!data);
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disable_irq_nosync(irq);
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set_irq_chip_and_handler_name(irq, &desc->chip,
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handle_level_irq, "level");
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set_irq_chip_data(irq, (void *)data);
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/* set priority */
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if (prio_data)
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intc_reg_fns[_INTC_FN(prio_data)].enable(desc, prio_data);
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/* irq should be disabled by default */
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desc->chip.mask(irq);
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}
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void __init register_intc_controller(struct intc_desc *desc)
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{
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unsigned int i;
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desc->chip.mask = intc_disable;
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desc->chip.unmask = intc_enable;
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desc->chip.mask_ack = intc_disable;
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desc->chip.set_type = intc_set_sense;
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for (i = 0; i < desc->nr_vectors; i++) {
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struct intc_vect *vect = desc->vectors + i;
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intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect));
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}
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}
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@ -1,6 +1,7 @@
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#ifndef __ASM_SH_HW_IRQ_H
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#define __ASM_SH_HW_IRQ_H
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#include <linux/init.h>
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#include <asm/atomic.h>
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extern atomic_t irq_err_count;
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@ -47,4 +48,71 @@ void init_IRQ_ipr(void);
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*/
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void ipr_irq_enable_irlm(void);
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typedef unsigned char intc_enum;
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struct intc_vect {
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intc_enum enum_id;
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unsigned short vect;
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};
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#define INTC_VECT(enum_id, vect) { enum_id, vect }
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struct intc_prio {
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intc_enum enum_id;
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unsigned char priority;
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};
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#define INTC_PRIO(enum_id, prio) { enum_id, prio }
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struct intc_group {
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intc_enum enum_id;
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intc_enum *enum_ids;
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};
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#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
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struct intc_mask_reg {
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unsigned long set_reg, clr_reg, reg_width;
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intc_enum enum_ids[32];
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};
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struct intc_prio_reg {
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unsigned long reg, reg_width, field_width;
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intc_enum enum_ids[16];
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};
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struct intc_sense_reg {
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unsigned long reg, reg_width, field_width;
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intc_enum enum_ids[16];
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};
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struct intc_desc {
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struct intc_vect *vectors;
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unsigned int nr_vectors;
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struct intc_group *groups;
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unsigned int nr_groups;
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struct intc_prio *priorities;
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unsigned int nr_priorities;
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struct intc_mask_reg *mask_regs;
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unsigned int nr_mask_regs;
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struct intc_prio_reg *prio_regs;
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unsigned int nr_prio_regs;
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struct intc_sense_reg *sense_regs;
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unsigned int nr_sense_regs;
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struct irq_chip chip;
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};
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#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
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#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
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priorities, mask_regs, prio_regs, sense_regs) \
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static struct intc_desc symbol = { \
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_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
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_INTC_ARRAY(priorities), \
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_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
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_INTC_ARRAY(sense_regs), \
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.chip.name = chipname, \
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}
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void __init register_intc_controller(struct intc_desc *desc);
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#endif /* __ASM_SH_HW_IRQ_H */
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