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clk: ti: Fix FAPLL parent enable bit handling

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Commit 163152cbbe ("clk: ti: Add support for FAPLL on dm816x")
added basic support for the FAPLL on dm818x, but has a bug for the
parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3)
but the code is doing a shift on it.

This means the parent PLL won't get disabled even if all it's child
synthesizers are disabled.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
This commit is contained in:
Tony Lindgren 2015-01-28 09:00:49 -08:00 committed by Michael Turquette
parent c517d838eb
commit 03208cc69f
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/ti/fapll.c
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@ -84,7 +84,7 @@ static int ti_fapll_enable(struct clk_hw *hw)
struct fapll_data *fd = to_fapll(hw);
u32 v = readl_relaxed(fd->base);
v |= (1 << FAPLL_MAIN_PLLEN);
v |= FAPLL_MAIN_PLLEN;
writel_relaxed(v, fd->base);
return 0;
@ -95,7 +95,7 @@ static void ti_fapll_disable(struct clk_hw *hw)
struct fapll_data *fd = to_fapll(hw);
u32 v = readl_relaxed(fd->base);
v &= ~(1 << FAPLL_MAIN_PLLEN);
v &= ~FAPLL_MAIN_PLLEN;
writel_relaxed(v, fd->base);
}
@ -104,7 +104,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw)
struct fapll_data *fd = to_fapll(hw);
u32 v = readl_relaxed(fd->base);
return v & (1 << FAPLL_MAIN_PLLEN);
return v & FAPLL_MAIN_PLLEN;
}
static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,