mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 13:55:32 +00:00
ixgbe: cleanup short msleep's (<20ms) to use usleep_range
Since msleep might not sleep for the desired amount when less than 20ms use usleep_range. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Stephen Ko <stephen.s.ko@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
0fa6d83258
commit
032b4325b6
8 changed files with 36 additions and 28 deletions
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@ -1083,7 +1083,7 @@ static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
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sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
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sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
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break;
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break;
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msleep(10);
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usleep_range(10000, 20000);
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}
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}
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
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if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
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@ -130,8 +130,12 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
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/* Release the semaphore */
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/* Release the semaphore */
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ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
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ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
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/* Delay obtaining semaphore again to allow FW access */
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/*
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msleep(hw->eeprom.semaphore_delay);
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* Delay obtaining semaphore again to allow FW access,
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* semaphore_delay is in ms usleep_range needs us.
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*/
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usleep_range(hw->eeprom.semaphore_delay * 1000,
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hw->eeprom.semaphore_delay * 2000);
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/* Now restart DSP by setting Restart_AN and clearing LMS */
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/* Now restart DSP by setting Restart_AN and clearing LMS */
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
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@ -140,7 +144,7 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
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/* Wait for AN to leave state 0 */
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/* Wait for AN to leave state 0 */
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for (i = 0; i < 10; i++) {
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for (i = 0; i < 10; i++) {
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msleep(4);
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usleep_range(4000, 8000);
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reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
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reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
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if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
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if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
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break;
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break;
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@ -1178,7 +1182,7 @@ s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
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if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
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if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
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IXGBE_FDIRCTRL_INIT_DONE)
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IXGBE_FDIRCTRL_INIT_DONE)
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break;
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break;
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msleep(1);
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usleep_range(1000, 2000);
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}
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}
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if (i >= IXGBE_FDIR_INIT_DONE_POLL)
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if (i >= IXGBE_FDIR_INIT_DONE_POLL)
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hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
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hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
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@ -1273,7 +1277,7 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
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if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
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if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
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IXGBE_FDIRCTRL_INIT_DONE)
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IXGBE_FDIRCTRL_INIT_DONE)
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break;
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break;
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msleep(1);
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usleep_range(1000, 2000);
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}
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}
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if (i >= IXGBE_FDIR_INIT_DONE_POLL)
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if (i >= IXGBE_FDIR_INIT_DONE_POLL)
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hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
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hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
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@ -503,7 +503,7 @@ s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
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reg_val &= ~(IXGBE_RXCTRL_RXEN);
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reg_val &= ~(IXGBE_RXCTRL_RXEN);
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IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
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IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
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IXGBE_WRITE_FLUSH(hw);
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IXGBE_WRITE_FLUSH(hw);
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msleep(2);
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usleep_range(2000, 4000);
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/* Clear interrupt mask to stop from interrupts being generated */
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/* Clear interrupt mask to stop from interrupts being generated */
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IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
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IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
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@ -1151,8 +1151,12 @@ static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
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hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
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hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
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/* Delay before attempt to obtain semaphore again to allow FW access */
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/*
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msleep(hw->eeprom.semaphore_delay);
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* Delay before attempt to obtain semaphore again to allow FW
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* access. semaphore_delay is in ms we need us for usleep_range
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*/
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usleep_range(hw->eeprom.semaphore_delay * 1000,
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hw->eeprom.semaphore_delay * 2000);
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}
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}
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/**
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/**
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@ -2228,7 +2232,7 @@ s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
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* thread currently using resource (swmask)
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* thread currently using resource (swmask)
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*/
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*/
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ixgbe_release_eeprom_semaphore(hw);
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ixgbe_release_eeprom_semaphore(hw);
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msleep(5);
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usleep_range(5000, 10000);
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timeout--;
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timeout--;
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}
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}
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@ -2302,7 +2306,7 @@ s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
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autoc_reg |= IXGBE_AUTOC_AN_RESTART;
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autoc_reg |= IXGBE_AUTOC_AN_RESTART;
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autoc_reg |= IXGBE_AUTOC_FLU;
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autoc_reg |= IXGBE_AUTOC_FLU;
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
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msleep(10);
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usleep_range(10000, 20000);
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}
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}
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led_reg &= ~IXGBE_LED_MODE_MASK(index);
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led_reg &= ~IXGBE_LED_MODE_MASK(index);
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@ -376,7 +376,7 @@ static u8 ixgbe_dcbnl_set_all(struct net_device *netdev)
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*/
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*/
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if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
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if (adapter->dcb_set_bitmap & BIT_APP_UPCHG) {
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while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
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while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
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msleep(1);
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usleep_range(1000, 2000);
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ixgbe_fcoe_setapp(adapter, up);
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ixgbe_fcoe_setapp(adapter, up);
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@ -931,7 +931,7 @@ static int ixgbe_set_ringparam(struct net_device *netdev,
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}
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}
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while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
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while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
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msleep(1);
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usleep_range(1000, 2000);
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if (!netif_running(adapter->netdev)) {
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if (!netif_running(adapter->netdev)) {
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for (i = 0; i < adapter->num_tx_queues; i++)
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for (i = 0; i < adapter->num_tx_queues; i++)
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@ -1417,7 +1417,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
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/* Disable all the interrupts */
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/* Disable all the interrupts */
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
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msleep(10);
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usleep_range(10000, 20000);
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/* Test each interrupt */
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/* Test each interrupt */
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for (; i < 10; i++) {
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for (; i < 10; i++) {
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@ -1437,7 +1437,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
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~mask & 0x00007FFF);
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~mask & 0x00007FFF);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
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~mask & 0x00007FFF);
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~mask & 0x00007FFF);
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msleep(10);
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usleep_range(10000, 20000);
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if (adapter->test_icr & mask) {
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if (adapter->test_icr & mask) {
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*data = 3;
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*data = 3;
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@ -1454,7 +1454,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
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adapter->test_icr = 0;
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adapter->test_icr = 0;
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
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msleep(10);
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usleep_range(10000, 20000);
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if (!(adapter->test_icr &mask)) {
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if (!(adapter->test_icr &mask)) {
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*data = 4;
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*data = 4;
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@ -1474,7 +1474,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
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~mask & 0x00007FFF);
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~mask & 0x00007FFF);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
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~mask & 0x00007FFF);
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~mask & 0x00007FFF);
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msleep(10);
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usleep_range(10000, 20000);
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if (adapter->test_icr) {
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if (adapter->test_icr) {
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*data = 5;
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*data = 5;
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@ -1485,7 +1485,7 @@ static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
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/* Disable all the interrupts */
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/* Disable all the interrupts */
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
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msleep(10);
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usleep_range(10000, 20000);
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/* Unhook test interrupt handler */
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/* Unhook test interrupt handler */
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free_irq(irq, netdev);
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free_irq(irq, netdev);
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@ -1613,7 +1613,7 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
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reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
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reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
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IXGBE_WRITE_FLUSH(&adapter->hw);
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IXGBE_WRITE_FLUSH(&adapter->hw);
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msleep(10);
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usleep_range(10000, 20000);
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/* Disable Atlas Tx lanes; re-enabled in reset path */
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/* Disable Atlas Tx lanes; re-enabled in reset path */
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if (hw->mac.type == ixgbe_mac_82598EB) {
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if (hw->mac.type == ixgbe_mac_82598EB) {
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@ -2731,7 +2731,7 @@ void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
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/* poll to verify queue is enabled */
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/* poll to verify queue is enabled */
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do {
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do {
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msleep(1);
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usleep_range(1000, 2000);
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
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txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
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} while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
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} while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
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if (!wait_loop)
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if (!wait_loop)
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@ -3023,7 +3023,7 @@ static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
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return;
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return;
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do {
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do {
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msleep(1);
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usleep_range(1000, 2000);
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rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
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rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
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} while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
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} while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
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@ -3945,7 +3945,7 @@ void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
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{
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{
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WARN_ON(in_interrupt());
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WARN_ON(in_interrupt());
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while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
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while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
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msleep(1);
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usleep_range(1000, 2000);
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ixgbe_down(adapter);
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ixgbe_down(adapter);
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/*
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/*
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* If SR-IOV enabled then wait a bit before bringing the adapter
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* If SR-IOV enabled then wait a bit before bringing the adapter
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@ -4150,7 +4150,7 @@ void ixgbe_down(struct ixgbe_adapter *adapter)
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/* this call also flushes the previous write */
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/* this call also flushes the previous write */
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ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
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ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
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msleep(10);
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usleep_range(10000, 20000);
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netif_tx_stop_all_queues(netdev);
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netif_tx_stop_all_queues(netdev);
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@ -753,7 +753,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
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&phy_data);
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&phy_data);
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if ((phy_data & MDIO_CTRL1_RESET) == 0)
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if ((phy_data & MDIO_CTRL1_RESET) == 0)
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break;
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break;
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msleep(10);
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usleep_range(10000, 20000);
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}
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}
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if ((phy_data & MDIO_CTRL1_RESET) != 0) {
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if ((phy_data & MDIO_CTRL1_RESET) != 0) {
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@ -782,7 +782,7 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
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case IXGBE_DELAY_NL:
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case IXGBE_DELAY_NL:
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data_offset++;
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data_offset++;
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hw_dbg(hw, "DELAY: %d MS\n", edata);
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hw_dbg(hw, "DELAY: %d MS\n", edata);
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msleep(edata);
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usleep_range(edata * 1000, edata * 2000);
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break;
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break;
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case IXGBE_DATA_NL:
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case IXGBE_DATA_NL:
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hw_dbg(hw, "DATA:\n");
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hw_dbg(hw, "DATA:\n");
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@ -563,7 +563,7 @@ static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
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* resource (swmask)
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* resource (swmask)
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*/
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*/
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ixgbe_release_swfw_sync_semaphore(hw);
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ixgbe_release_swfw_sync_semaphore(hw);
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msleep(5);
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usleep_range(5000, 10000);
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}
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}
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}
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}
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@ -585,7 +585,7 @@ static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
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}
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}
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}
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}
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msleep(5);
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usleep_range(5000, 10000);
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return 0;
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return 0;
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}
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}
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@ -609,7 +609,7 @@ static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
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IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
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IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
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ixgbe_release_swfw_sync_semaphore(hw);
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ixgbe_release_swfw_sync_semaphore(hw);
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msleep(5);
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usleep_range(5000, 10000);
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}
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}
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/**
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/**
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