mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-26 04:16:39 +00:00
Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next
- Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
This commit is contained in:
Stephen Boyd
commit
032bcf783e
66 changed files with 5000 additions and 3463 deletions
|
|
@ -1,64 +0,0 @@
|
|||
* Amlogic GXBB AO Clock and Reset Unit
|
||||
|
||||
The Amlogic GXBB AO clock controller generates and supplies clock to various
|
||||
controllers within the Always-On part of the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: value should be different for each SoC family as :
|
||||
- GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
|
||||
- GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
|
||||
- GXM (S912) : "amlogic,meson-gxm-aoclkc"
|
||||
- AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
|
||||
- G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
|
||||
followed by the common "amlogic,meson-gx-aoclkc"
|
||||
- clocks: list of clock phandle, one for each entry clock-names.
|
||||
- clock-names: should contain the following:
|
||||
* "xtal" : the platform xtal
|
||||
* "mpeg-clk" : the main clock controller mother clock (aka clk81)
|
||||
* "ext-32k-0" : external 32kHz reference #0 if any (optional)
|
||||
* "ext-32k-1" : external 32kHz reference #1 if any (optional - gx only)
|
||||
* "ext-32k-2" : external 32kHz reference #2 if any (optional - gx only)
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
- #reset-cells: should be 1.
|
||||
|
||||
Each reset is assigned an identifier and client nodes can use this identifier
|
||||
to specify the reset which they consume. All available resets are defined as
|
||||
preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"
|
||||
- reg: base address and size of the AO system control register space.
|
||||
|
||||
Example: AO Clock controller node:
|
||||
|
||||
ao_sysctrl: sys-ctrl@0 {
|
||||
compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
|
||||
reg = <0x0 0x0 0x0 0x100>;
|
||||
|
||||
clkc_AO: clock-controller {
|
||||
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&xtal>, <&clkc CLKID_CLK81>;
|
||||
clock-names = "xtal", "mpeg-clk";
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock and reset generated
|
||||
by the clock controller:
|
||||
|
||||
uart_AO: serial@4c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0x4c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc_AO CLKID_AO_UART1>;
|
||||
resets = <&clkc_AO RESET_AO_UART1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-aoclkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Always-On Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- amlogic,meson-gxbb-aoclkc
|
||||
- amlogic,meson-gxl-aoclkc
|
||||
- amlogic,meson-gxm-aoclkc
|
||||
- amlogic,meson-axg-aoclkc
|
||||
- const: amlogic,meson-gx-aoclkc
|
||||
- enum:
|
||||
- amlogic,meson-axg-aoclkc
|
||||
- amlogic,meson-g12a-aoclkc
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: xtal
|
||||
- const: mpeg-clk
|
||||
- const: ext-32k-0
|
||||
- const: ext-32k-1
|
||||
- const: ext-32k-2
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-g12a-aoclkc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-gxl-aoclkc
|
||||
- amlogic,meson-gxm-aoclkc
|
||||
- amlogic,meson-axg-aoclkc
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
* Amlogic GXBB Clock and Reset Unit
|
||||
|
||||
The Amlogic GXBB clock controller generates and supplies clock to various
|
||||
controllers within the SoC.
|
||||
|
||||
Required Properties:
|
||||
|
||||
- compatible: should be:
|
||||
"amlogic,gxbb-clkc" for GXBB SoC,
|
||||
"amlogic,gxl-clkc" for GXL and GXM SoC,
|
||||
"amlogic,axg-clkc" for AXG SoC.
|
||||
"amlogic,g12a-clkc" for G12A SoC.
|
||||
"amlogic,g12b-clkc" for G12B SoC.
|
||||
"amlogic,sm1-clkc" for SM1 SoC.
|
||||
- clocks : list of clock phandle, one for each entry clock-names.
|
||||
- clock-names : should contain the following:
|
||||
* "xtal": the platform xtal
|
||||
|
||||
- #clock-cells: should be 1.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All available clocks are defined as
|
||||
preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be
|
||||
used in device tree sources.
|
||||
|
||||
Parent node should have the following properties :
|
||||
- compatible: "syscon", "simple-mfd, and "amlogic,meson-gx-hhi-sysctrl" or
|
||||
"amlogic,meson-axg-hhi-sysctrl"
|
||||
- reg: base address and size of the HHI system control register space.
|
||||
|
||||
Example: Clock controller node:
|
||||
|
||||
sysctrl: system-controller@0 {
|
||||
compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
|
||||
reg = <0 0 0 0x400>;
|
||||
|
||||
clkc: clock-controller {
|
||||
#clock-cells = <1>;
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
};
|
||||
};
|
||||
|
||||
Example: UART controller node that consumes the clock generated by the clock
|
||||
controller:
|
||||
|
||||
uart_AO: serial@c81004c0 {
|
||||
compatible = "amlogic,meson-uart";
|
||||
reg = <0xc81004c0 0x14>;
|
||||
interrupts = <0 90 1>;
|
||||
clocks = <&clkc CLKID_CLK81>;
|
||||
};
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/amlogic,gxbb-clkc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,gxbb-clkc
|
||||
- amlogic,gxl-clkc
|
||||
- amlogic,axg-clkc
|
||||
- amlogic,g12a-clkc
|
||||
- amlogic,g12b-clkc
|
||||
- amlogic,sm1-clkc
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: xtal
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
86
Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
Normal file
86
Documentation/devicetree/bindings/clock/renesas,5p35023.yaml
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
|
||||
|
||||
maintainers:
|
||||
- Biju Das <biju.das.jz@bp.renesas.com>
|
||||
|
||||
description: |
|
||||
The 5P35023 is a VersaClock programmable clock generator and
|
||||
is designed for low-power, consumer, and high-performance PCI
|
||||
express applications. The 5P35023 device is a three PLL
|
||||
architecture design, and each PLL is individually programmable
|
||||
and allowing for up to 6 unique frequency outputs.
|
||||
|
||||
An internal OTP memory allows the user to store the configuration
|
||||
in the device. After power up, the user can change the device register
|
||||
settings through the I2C interface when I2C mode is selected.
|
||||
|
||||
The driver can read a full register map from the DT, and will use that
|
||||
register map to initialize the attached part (via I2C) when the system
|
||||
boots. Any configuration not supported by the common clock framework
|
||||
must be done via the full register map, including optimized settings.
|
||||
|
||||
Link to datasheet:
|
||||
https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- renesas,5p35023
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
renesas,settings:
|
||||
description: Optional, complete register map of the device.
|
||||
Optimized settings for the device must be provided in full
|
||||
and are written during initialization.
|
||||
$ref: /schemas/types.yaml#/definitions/uint8-array
|
||||
maxItems: 37
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
versa3: clock-generator@68 {
|
||||
compatible = "renesas,5p35023";
|
||||
reg = <0x68>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&x1_x2>;
|
||||
|
||||
renesas,settings = [
|
||||
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
|
||||
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
|
||||
80 b0 45 c4 95
|
||||
];
|
||||
|
||||
assigned-clocks = <&versa3 0>, <&versa3 1>,
|
||||
<&versa3 2>, <&versa3 3>,
|
||||
<&versa3 4>, <&versa3 5>;
|
||||
assigned-clock-rates = <12288000>, <25000000>,
|
||||
<12000000>, <11289600>,
|
||||
<11289600>, <24000000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amlogic Meson System Control registers
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- amlogic,meson-gx-hhi-sysctrl
|
||||
- amlogic,meson-gx-ao-sysctrl
|
||||
- amlogic,meson-axg-hhi-sysctrl
|
||||
- amlogic,meson-axg-ao-sysctrl
|
||||
- const: simple-mfd
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clock-controller:
|
||||
type: object
|
||||
|
||||
power-controller:
|
||||
$ref: /schemas/power/amlogic,meson-ee-pwrc.yaml
|
||||
|
||||
pinctrl:
|
||||
type: object
|
||||
|
||||
phy:
|
||||
type: object
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-gx-hhi-sysctrl
|
||||
- amlogic,meson-axg-hhi-sysctrl
|
||||
then:
|
||||
properties:
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/amlogic,gxbb-clkc.yaml#
|
||||
|
||||
required:
|
||||
- power-controller
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-gx-ao-sysctrl
|
||||
- amlogic,meson-axg-ao-sysctrl
|
||||
then:
|
||||
properties:
|
||||
clock-controller:
|
||||
$ref: /schemas/clock/amlogic,gxbb-aoclkc.yaml#
|
||||
|
||||
power-controller: false
|
||||
phy: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-gx-hhi-sysctrl
|
||||
then:
|
||||
properties:
|
||||
phy: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- amlogic,meson-axg-hhi-sysctrl
|
||||
then:
|
||||
properties:
|
||||
phy:
|
||||
oneOf:
|
||||
- $ref: /schemas/phy/amlogic,g12a-mipi-dphy-analog.yaml
|
||||
- $ref: /schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clock-controller
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus@c883c000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0xc883c000 0x2000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xc883c000 0x2000>;
|
||||
|
||||
sysctrl: system-controller@0 {
|
||||
compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon";
|
||||
reg = <0 0x400>;
|
||||
|
||||
clock-controller {
|
||||
compatible = "amlogic,gxbb-clkc";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "xtal";
|
||||
};
|
||||
|
||||
power-controller {
|
||||
compatible = "amlogic,meson-gxbb-pwrc";
|
||||
#power-domain-cells = <1>;
|
||||
amlogic,ao-sysctrl = <&sysctrl_AO>;
|
||||
|
||||
resets = <&reset_viu>,
|
||||
<&reset_venc>,
|
||||
<&reset_vcbus>,
|
||||
<&reset_bt656>,
|
||||
<&reset_dvin>,
|
||||
<&reset_rdma>,
|
||||
<&reset_venci>,
|
||||
<&reset_vencp>,
|
||||
<&reset_vdac>,
|
||||
<&reset_vdi6>,
|
||||
<&reset_vencl>,
|
||||
<&reset_vid_lock>;
|
||||
reset-names = "viu", "venc", "vcbus", "bt656", "dvin",
|
||||
"rdma", "venci", "vencp", "vdac", "vdi6",
|
||||
"vencl", "vid_lock";
|
||||
clocks = <&clk_vpu>, <&clk_vapb>;
|
||||
clock-names = "vpu", "vapb";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bus@c8100000 {
|
||||
compatible = "simple-bus";
|
||||
reg = <0xc8100000 0x100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xc8100000 0x100000>;
|
||||
|
||||
sysctrl_AO: system-controller@0 {
|
||||
compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon";
|
||||
reg = <0 0x100>;
|
||||
|
||||
clock-controller {
|
||||
compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
clocks = <&xtal>, <&clk81>;
|
||||
clock-names = "xtal", "mpeg-clk";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -17,7 +17,6 @@
|
|||
#include <linux/kstrtox.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/notifier.h>
|
||||
#include <linux/of.h>
|
||||
|
|
@ -28,6 +27,7 @@
|
|||
#include <linux/netdevice.h>
|
||||
#include <linux/sched/signal.h>
|
||||
#include <linux/sched/mm.h>
|
||||
#include <linux/string_helpers.h>
|
||||
#include <linux/swiotlb.h>
|
||||
#include <linux/sysfs.h>
|
||||
#include <linux/dma-map-ops.h> /* for dma_default_coherent */
|
||||
|
|
@ -3910,10 +3910,9 @@ const char *device_get_devnode(const struct device *dev,
|
|||
return dev_name(dev);
|
||||
|
||||
/* replace '!' in the name with '/' */
|
||||
s = kstrdup(dev_name(dev), GFP_KERNEL);
|
||||
s = kstrdup_and_replace(dev_name(dev), '!', '/', GFP_KERNEL);
|
||||
if (!s)
|
||||
return NULL;
|
||||
strreplace(s, '!', '/');
|
||||
return *tmp = s;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -378,6 +378,15 @@ config COMMON_CLK_SI521XX
|
|||
This driver supports the SkyWorks Si521xx PCIe clock generator
|
||||
models Si52144/Si52146/Si52147.
|
||||
|
||||
config COMMON_CLK_VC3
|
||||
tristate "Clock driver for Renesas VersaClock 3 devices"
|
||||
depends on I2C
|
||||
depends on OF
|
||||
select REGMAP_I2C
|
||||
help
|
||||
This driver supports the Renesas VersaClock 3 programmable clock
|
||||
generators.
|
||||
|
||||
config COMMON_CLK_VC5
|
||||
tristate "Clock driver for IDT VersaClock 5,6 devices"
|
||||
depends on I2C
|
||||
|
|
|
|||
|
|
@ -75,6 +75,7 @@ obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
|
|||
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
|
||||
obj-$(CONFIG_COMMON_CLK_RS9_PCIE) += clk-renesas-pcie.o
|
||||
obj-$(CONFIG_COMMON_CLK_SI521XX) += clk-si521xx.o
|
||||
obj-$(CONFIG_COMMON_CLK_VC3) += clk-versaclock3.o
|
||||
obj-$(CONFIG_COMMON_CLK_VC5) += clk-versaclock5.o
|
||||
obj-$(CONFIG_COMMON_CLK_VC7) += clk-versaclock7.o
|
||||
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
|
||||
|
|
|
|||
1143
drivers/clk/clk-versaclock3.c
Normal file
1143
drivers/clk/clk-versaclock3.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -955,7 +955,7 @@ static int vc5_probe(struct i2c_client *client)
|
|||
|
||||
i2c_set_clientdata(client, vc5);
|
||||
vc5->client = client;
|
||||
vc5->chip_info = device_get_match_data(&client->dev);
|
||||
vc5->chip_info = i2c_get_match_data(client);
|
||||
|
||||
vc5->pin_xin = devm_clk_get(&client->dev, "xin");
|
||||
if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
|
||||
|
|
|
|||
|
|
@ -1108,7 +1108,7 @@ static int vc7_probe(struct i2c_client *client)
|
|||
|
||||
i2c_set_clientdata(client, vc7);
|
||||
vc7->client = client;
|
||||
vc7->chip_info = device_get_match_data(&client->dev);
|
||||
vc7->chip_info = i2c_get_match_data(client);
|
||||
|
||||
vc7->pin_xin = devm_clk_get(&client->dev, "xin");
|
||||
if (PTR_ERR(vc7->pin_xin) == -EPROBE_DEFER) {
|
||||
|
|
|
|||
|
|
@ -30,14 +30,19 @@ config COMMON_CLK_MESON_VID_PLL_DIV
|
|||
tristate
|
||||
select COMMON_CLK_MESON_REGMAP
|
||||
|
||||
config COMMON_CLK_MESON_CLKC_UTILS
|
||||
tristate
|
||||
|
||||
config COMMON_CLK_MESON_AO_CLKC
|
||||
tristate
|
||||
select COMMON_CLK_MESON_REGMAP
|
||||
select COMMON_CLK_MESON_CLKC_UTILS
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config COMMON_CLK_MESON_EE_CLKC
|
||||
tristate
|
||||
select COMMON_CLK_MESON_REGMAP
|
||||
select COMMON_CLK_MESON_CLKC_UTILS
|
||||
|
||||
config COMMON_CLK_MESON_CPU_DYNDIV
|
||||
tristate
|
||||
|
|
@ -48,6 +53,7 @@ config COMMON_CLK_MESON8B
|
|||
depends on ARM
|
||||
default y
|
||||
select COMMON_CLK_MESON_REGMAP
|
||||
select COMMON_CLK_MESON_CLKC_UTILS
|
||||
select COMMON_CLK_MESON_MPLL
|
||||
select COMMON_CLK_MESON_PLL
|
||||
select MFD_SYSCON
|
||||
|
|
@ -94,6 +100,7 @@ config COMMON_CLK_AXG_AUDIO
|
|||
select COMMON_CLK_MESON_REGMAP
|
||||
select COMMON_CLK_MESON_PHASE
|
||||
select COMMON_CLK_MESON_SCLK_DIV
|
||||
select COMMON_CLK_MESON_CLKC_UTILS
|
||||
select REGMAP_MMIO
|
||||
help
|
||||
Support for the audio clock controller on AmLogic A113D devices,
|
||||
|
|
@ -103,6 +110,7 @@ config COMMON_CLK_A1_PLL
|
|||
tristate "Amlogic A1 SoC PLL controller support"
|
||||
depends on ARM64
|
||||
select COMMON_CLK_MESON_REGMAP
|
||||
select COMMON_CLK_MESON_CLKC_UTILS
|
||||
select COMMON_CLK_MESON_PLL
|
||||
help
|
||||
Support for the PLL clock controller on Amlogic A113L based
|
||||
|
|
@ -114,6 +122,7 @@ config COMMON_CLK_A1_PERIPHERALS
|
|||
depends on ARM64
|
||||
select COMMON_CLK_MESON_DUALDIV
|
||||
select COMMON_CLK_MESON_REGMAP
|
||||
select COMMON_CLK_MESON_CLKC_UTILS
|
||||
help
|
||||
Support for the Peripherals clock controller on Amlogic A113L based
|
||||
device, A1 SoC Family. Say Y if you want A1 Peripherals clock
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
# Amlogic clock drivers
|
||||
|
||||
obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) += meson-clkc-utils.o
|
||||
obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
|
||||
obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
|
||||
obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
|
||||
|
|
|
|||
|
|
@ -13,6 +13,9 @@
|
|||
#include "a1-peripherals.h"
|
||||
#include "clk-dualdiv.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "meson-clkc-utils.h"
|
||||
|
||||
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
|
||||
|
||||
static struct clk_regmap xtal_in = {
|
||||
.data = &(struct clk_regmap_gate_data){
|
||||
|
|
@ -1866,165 +1869,161 @@ static MESON_GATE(rom, AXI_CLK_EN, 11);
|
|||
static MESON_GATE(prod_i2c, AXI_CLK_EN, 12);
|
||||
|
||||
/* Array of all clocks registered by this provider */
|
||||
static struct clk_hw_onecell_data a1_periphs_clks = {
|
||||
.hws = {
|
||||
[CLKID_XTAL_IN] = &xtal_in.hw,
|
||||
[CLKID_FIXPLL_IN] = &fixpll_in.hw,
|
||||
[CLKID_USB_PHY_IN] = &usb_phy_in.hw,
|
||||
[CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
|
||||
[CLKID_HIFIPLL_IN] = &hifipll_in.hw,
|
||||
[CLKID_SYSPLL_IN] = &syspll_in.hw,
|
||||
[CLKID_DDS_IN] = &dds_in.hw,
|
||||
[CLKID_SYS] = &sys.hw,
|
||||
[CLKID_CLKTREE] = &clktree.hw,
|
||||
[CLKID_RESET_CTRL] = &reset_ctrl.hw,
|
||||
[CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
|
||||
[CLKID_PWR_CTRL] = &pwr_ctrl.hw,
|
||||
[CLKID_PAD_CTRL] = &pad_ctrl.hw,
|
||||
[CLKID_SYS_CTRL] = &sys_ctrl.hw,
|
||||
[CLKID_TEMP_SENSOR] = &temp_sensor.hw,
|
||||
[CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
|
||||
[CLKID_SPICC_B] = &spicc_b.hw,
|
||||
[CLKID_SPICC_A] = &spicc_a.hw,
|
||||
[CLKID_MSR] = &msr.hw,
|
||||
[CLKID_AUDIO] = &audio.hw,
|
||||
[CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
|
||||
[CLKID_SARADC_EN] = &saradc_en.hw,
|
||||
[CLKID_PWM_EF] = &pwm_ef.hw,
|
||||
[CLKID_PWM_CD] = &pwm_cd.hw,
|
||||
[CLKID_PWM_AB] = &pwm_ab.hw,
|
||||
[CLKID_CEC] = &cec.hw,
|
||||
[CLKID_I2C_S] = &i2c_s.hw,
|
||||
[CLKID_IR_CTRL] = &ir_ctrl.hw,
|
||||
[CLKID_I2C_M_D] = &i2c_m_d.hw,
|
||||
[CLKID_I2C_M_C] = &i2c_m_c.hw,
|
||||
[CLKID_I2C_M_B] = &i2c_m_b.hw,
|
||||
[CLKID_I2C_M_A] = &i2c_m_a.hw,
|
||||
[CLKID_ACODEC] = &acodec.hw,
|
||||
[CLKID_OTP] = &otp.hw,
|
||||
[CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
|
||||
[CLKID_USB_PHY] = &usb_phy.hw,
|
||||
[CLKID_USB_CTRL] = &usb_ctrl.hw,
|
||||
[CLKID_SYS_DSPB] = &sys_dspb.hw,
|
||||
[CLKID_SYS_DSPA] = &sys_dspa.hw,
|
||||
[CLKID_DMA] = &dma.hw,
|
||||
[CLKID_IRQ_CTRL] = &irq_ctrl.hw,
|
||||
[CLKID_NIC] = &nic.hw,
|
||||
[CLKID_GIC] = &gic.hw,
|
||||
[CLKID_UART_C] = &uart_c.hw,
|
||||
[CLKID_UART_B] = &uart_b.hw,
|
||||
[CLKID_UART_A] = &uart_a.hw,
|
||||
[CLKID_SYS_PSRAM] = &sys_psram.hw,
|
||||
[CLKID_RSA] = &rsa.hw,
|
||||
[CLKID_CORESIGHT] = &coresight.hw,
|
||||
[CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
|
||||
[CLKID_AUDIO_VAD] = &audio_vad.hw,
|
||||
[CLKID_AXI_DMC] = &axi_dmc.hw,
|
||||
[CLKID_AXI_PSRAM] = &axi_psram.hw,
|
||||
[CLKID_RAMB] = &ramb.hw,
|
||||
[CLKID_RAMA] = &rama.hw,
|
||||
[CLKID_AXI_SPIFC] = &axi_spifc.hw,
|
||||
[CLKID_AXI_NIC] = &axi_nic.hw,
|
||||
[CLKID_AXI_DMA] = &axi_dma.hw,
|
||||
[CLKID_CPU_CTRL] = &cpu_ctrl.hw,
|
||||
[CLKID_ROM] = &rom.hw,
|
||||
[CLKID_PROC_I2C] = &prod_i2c.hw,
|
||||
[CLKID_DSPA_SEL] = &dspa_sel.hw,
|
||||
[CLKID_DSPB_SEL] = &dspb_sel.hw,
|
||||
[CLKID_DSPA_EN] = &dspa_en.hw,
|
||||
[CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
|
||||
[CLKID_DSPB_EN] = &dspb_en.hw,
|
||||
[CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
|
||||
[CLKID_RTC] = &rtc.hw,
|
||||
[CLKID_CECA_32K] = &ceca_32k_out.hw,
|
||||
[CLKID_CECB_32K] = &cecb_32k_out.hw,
|
||||
[CLKID_24M] = &clk_24m.hw,
|
||||
[CLKID_12M] = &clk_12m.hw,
|
||||
[CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
|
||||
[CLKID_GEN] = &gen.hw,
|
||||
[CLKID_SARADC_SEL] = &saradc_sel.hw,
|
||||
[CLKID_SARADC] = &saradc.hw,
|
||||
[CLKID_PWM_A] = &pwm_a.hw,
|
||||
[CLKID_PWM_B] = &pwm_b.hw,
|
||||
[CLKID_PWM_C] = &pwm_c.hw,
|
||||
[CLKID_PWM_D] = &pwm_d.hw,
|
||||
[CLKID_PWM_E] = &pwm_e.hw,
|
||||
[CLKID_PWM_F] = &pwm_f.hw,
|
||||
[CLKID_SPICC] = &spicc.hw,
|
||||
[CLKID_TS] = &ts.hw,
|
||||
[CLKID_SPIFC] = &spifc.hw,
|
||||
[CLKID_USB_BUS] = &usb_bus.hw,
|
||||
[CLKID_SD_EMMC] = &sd_emmc.hw,
|
||||
[CLKID_PSRAM] = &psram.hw,
|
||||
[CLKID_DMC] = &dmc.hw,
|
||||
[CLKID_SYS_A_SEL] = &sys_a_sel.hw,
|
||||
[CLKID_SYS_A_DIV] = &sys_a_div.hw,
|
||||
[CLKID_SYS_A] = &sys_a.hw,
|
||||
[CLKID_SYS_B_SEL] = &sys_b_sel.hw,
|
||||
[CLKID_SYS_B_DIV] = &sys_b_div.hw,
|
||||
[CLKID_SYS_B] = &sys_b.hw,
|
||||
[CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
|
||||
[CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
|
||||
[CLKID_DSPA_A] = &dspa_a.hw,
|
||||
[CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
|
||||
[CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
|
||||
[CLKID_DSPA_B] = &dspa_b.hw,
|
||||
[CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
|
||||
[CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
|
||||
[CLKID_DSPB_A] = &dspb_a.hw,
|
||||
[CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
|
||||
[CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
|
||||
[CLKID_DSPB_B] = &dspb_b.hw,
|
||||
[CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
|
||||
[CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
|
||||
[CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
|
||||
[CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
|
||||
[CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
|
||||
[CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
|
||||
[CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
|
||||
[CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
|
||||
[CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
|
||||
[CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
|
||||
[CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
|
||||
[CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
|
||||
[CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
|
||||
[CLKID_24M_DIV2] = &clk_24m_div2.hw,
|
||||
[CLKID_GEN_SEL] = &gen_sel.hw,
|
||||
[CLKID_GEN_DIV] = &gen_div.hw,
|
||||
[CLKID_SARADC_DIV] = &saradc_div.hw,
|
||||
[CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
|
||||
[CLKID_PWM_A_DIV] = &pwm_a_div.hw,
|
||||
[CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
|
||||
[CLKID_PWM_B_DIV] = &pwm_b_div.hw,
|
||||
[CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
|
||||
[CLKID_PWM_C_DIV] = &pwm_c_div.hw,
|
||||
[CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
|
||||
[CLKID_PWM_D_DIV] = &pwm_d_div.hw,
|
||||
[CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
|
||||
[CLKID_PWM_E_DIV] = &pwm_e_div.hw,
|
||||
[CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
|
||||
[CLKID_PWM_F_DIV] = &pwm_f_div.hw,
|
||||
[CLKID_SPICC_SEL] = &spicc_sel.hw,
|
||||
[CLKID_SPICC_DIV] = &spicc_div.hw,
|
||||
[CLKID_SPICC_SEL2] = &spicc_sel2.hw,
|
||||
[CLKID_TS_DIV] = &ts_div.hw,
|
||||
[CLKID_SPIFC_SEL] = &spifc_sel.hw,
|
||||
[CLKID_SPIFC_DIV] = &spifc_div.hw,
|
||||
[CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
|
||||
[CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
|
||||
[CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
|
||||
[CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
|
||||
[CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
|
||||
[CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
|
||||
[CLKID_PSRAM_SEL] = &psram_sel.hw,
|
||||
[CLKID_PSRAM_DIV] = &psram_div.hw,
|
||||
[CLKID_PSRAM_SEL2] = &psram_sel2.hw,
|
||||
[CLKID_DMC_SEL] = &dmc_sel.hw,
|
||||
[CLKID_DMC_DIV] = &dmc_div.hw,
|
||||
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *a1_periphs_hw_clks[] = {
|
||||
[CLKID_XTAL_IN] = &xtal_in.hw,
|
||||
[CLKID_FIXPLL_IN] = &fixpll_in.hw,
|
||||
[CLKID_USB_PHY_IN] = &usb_phy_in.hw,
|
||||
[CLKID_USB_CTRL_IN] = &usb_ctrl_in.hw,
|
||||
[CLKID_HIFIPLL_IN] = &hifipll_in.hw,
|
||||
[CLKID_SYSPLL_IN] = &syspll_in.hw,
|
||||
[CLKID_DDS_IN] = &dds_in.hw,
|
||||
[CLKID_SYS] = &sys.hw,
|
||||
[CLKID_CLKTREE] = &clktree.hw,
|
||||
[CLKID_RESET_CTRL] = &reset_ctrl.hw,
|
||||
[CLKID_ANALOG_CTRL] = &analog_ctrl.hw,
|
||||
[CLKID_PWR_CTRL] = &pwr_ctrl.hw,
|
||||
[CLKID_PAD_CTRL] = &pad_ctrl.hw,
|
||||
[CLKID_SYS_CTRL] = &sys_ctrl.hw,
|
||||
[CLKID_TEMP_SENSOR] = &temp_sensor.hw,
|
||||
[CLKID_AM2AXI_DIV] = &am2axi_dev.hw,
|
||||
[CLKID_SPICC_B] = &spicc_b.hw,
|
||||
[CLKID_SPICC_A] = &spicc_a.hw,
|
||||
[CLKID_MSR] = &msr.hw,
|
||||
[CLKID_AUDIO] = &audio.hw,
|
||||
[CLKID_JTAG_CTRL] = &jtag_ctrl.hw,
|
||||
[CLKID_SARADC_EN] = &saradc_en.hw,
|
||||
[CLKID_PWM_EF] = &pwm_ef.hw,
|
||||
[CLKID_PWM_CD] = &pwm_cd.hw,
|
||||
[CLKID_PWM_AB] = &pwm_ab.hw,
|
||||
[CLKID_CEC] = &cec.hw,
|
||||
[CLKID_I2C_S] = &i2c_s.hw,
|
||||
[CLKID_IR_CTRL] = &ir_ctrl.hw,
|
||||
[CLKID_I2C_M_D] = &i2c_m_d.hw,
|
||||
[CLKID_I2C_M_C] = &i2c_m_c.hw,
|
||||
[CLKID_I2C_M_B] = &i2c_m_b.hw,
|
||||
[CLKID_I2C_M_A] = &i2c_m_a.hw,
|
||||
[CLKID_ACODEC] = &acodec.hw,
|
||||
[CLKID_OTP] = &otp.hw,
|
||||
[CLKID_SD_EMMC_A] = &sd_emmc_a.hw,
|
||||
[CLKID_USB_PHY] = &usb_phy.hw,
|
||||
[CLKID_USB_CTRL] = &usb_ctrl.hw,
|
||||
[CLKID_SYS_DSPB] = &sys_dspb.hw,
|
||||
[CLKID_SYS_DSPA] = &sys_dspa.hw,
|
||||
[CLKID_DMA] = &dma.hw,
|
||||
[CLKID_IRQ_CTRL] = &irq_ctrl.hw,
|
||||
[CLKID_NIC] = &nic.hw,
|
||||
[CLKID_GIC] = &gic.hw,
|
||||
[CLKID_UART_C] = &uart_c.hw,
|
||||
[CLKID_UART_B] = &uart_b.hw,
|
||||
[CLKID_UART_A] = &uart_a.hw,
|
||||
[CLKID_SYS_PSRAM] = &sys_psram.hw,
|
||||
[CLKID_RSA] = &rsa.hw,
|
||||
[CLKID_CORESIGHT] = &coresight.hw,
|
||||
[CLKID_AM2AXI_VAD] = &am2axi_vad.hw,
|
||||
[CLKID_AUDIO_VAD] = &audio_vad.hw,
|
||||
[CLKID_AXI_DMC] = &axi_dmc.hw,
|
||||
[CLKID_AXI_PSRAM] = &axi_psram.hw,
|
||||
[CLKID_RAMB] = &ramb.hw,
|
||||
[CLKID_RAMA] = &rama.hw,
|
||||
[CLKID_AXI_SPIFC] = &axi_spifc.hw,
|
||||
[CLKID_AXI_NIC] = &axi_nic.hw,
|
||||
[CLKID_AXI_DMA] = &axi_dma.hw,
|
||||
[CLKID_CPU_CTRL] = &cpu_ctrl.hw,
|
||||
[CLKID_ROM] = &rom.hw,
|
||||
[CLKID_PROC_I2C] = &prod_i2c.hw,
|
||||
[CLKID_DSPA_SEL] = &dspa_sel.hw,
|
||||
[CLKID_DSPB_SEL] = &dspb_sel.hw,
|
||||
[CLKID_DSPA_EN] = &dspa_en.hw,
|
||||
[CLKID_DSPA_EN_NIC] = &dspa_en_nic.hw,
|
||||
[CLKID_DSPB_EN] = &dspb_en.hw,
|
||||
[CLKID_DSPB_EN_NIC] = &dspb_en_nic.hw,
|
||||
[CLKID_RTC] = &rtc.hw,
|
||||
[CLKID_CECA_32K] = &ceca_32k_out.hw,
|
||||
[CLKID_CECB_32K] = &cecb_32k_out.hw,
|
||||
[CLKID_24M] = &clk_24m.hw,
|
||||
[CLKID_12M] = &clk_12m.hw,
|
||||
[CLKID_FCLK_DIV2_DIVN] = &fclk_div2_divn.hw,
|
||||
[CLKID_GEN] = &gen.hw,
|
||||
[CLKID_SARADC_SEL] = &saradc_sel.hw,
|
||||
[CLKID_SARADC] = &saradc.hw,
|
||||
[CLKID_PWM_A] = &pwm_a.hw,
|
||||
[CLKID_PWM_B] = &pwm_b.hw,
|
||||
[CLKID_PWM_C] = &pwm_c.hw,
|
||||
[CLKID_PWM_D] = &pwm_d.hw,
|
||||
[CLKID_PWM_E] = &pwm_e.hw,
|
||||
[CLKID_PWM_F] = &pwm_f.hw,
|
||||
[CLKID_SPICC] = &spicc.hw,
|
||||
[CLKID_TS] = &ts.hw,
|
||||
[CLKID_SPIFC] = &spifc.hw,
|
||||
[CLKID_USB_BUS] = &usb_bus.hw,
|
||||
[CLKID_SD_EMMC] = &sd_emmc.hw,
|
||||
[CLKID_PSRAM] = &psram.hw,
|
||||
[CLKID_DMC] = &dmc.hw,
|
||||
[CLKID_SYS_A_SEL] = &sys_a_sel.hw,
|
||||
[CLKID_SYS_A_DIV] = &sys_a_div.hw,
|
||||
[CLKID_SYS_A] = &sys_a.hw,
|
||||
[CLKID_SYS_B_SEL] = &sys_b_sel.hw,
|
||||
[CLKID_SYS_B_DIV] = &sys_b_div.hw,
|
||||
[CLKID_SYS_B] = &sys_b.hw,
|
||||
[CLKID_DSPA_A_SEL] = &dspa_a_sel.hw,
|
||||
[CLKID_DSPA_A_DIV] = &dspa_a_div.hw,
|
||||
[CLKID_DSPA_A] = &dspa_a.hw,
|
||||
[CLKID_DSPA_B_SEL] = &dspa_b_sel.hw,
|
||||
[CLKID_DSPA_B_DIV] = &dspa_b_div.hw,
|
||||
[CLKID_DSPA_B] = &dspa_b.hw,
|
||||
[CLKID_DSPB_A_SEL] = &dspb_a_sel.hw,
|
||||
[CLKID_DSPB_A_DIV] = &dspb_a_div.hw,
|
||||
[CLKID_DSPB_A] = &dspb_a.hw,
|
||||
[CLKID_DSPB_B_SEL] = &dspb_b_sel.hw,
|
||||
[CLKID_DSPB_B_DIV] = &dspb_b_div.hw,
|
||||
[CLKID_DSPB_B] = &dspb_b.hw,
|
||||
[CLKID_RTC_32K_IN] = &rtc_32k_in.hw,
|
||||
[CLKID_RTC_32K_DIV] = &rtc_32k_div.hw,
|
||||
[CLKID_RTC_32K_XTAL] = &rtc_32k_xtal.hw,
|
||||
[CLKID_RTC_32K_SEL] = &rtc_32k_sel.hw,
|
||||
[CLKID_CECB_32K_IN] = &cecb_32k_in.hw,
|
||||
[CLKID_CECB_32K_DIV] = &cecb_32k_div.hw,
|
||||
[CLKID_CECB_32K_SEL_PRE] = &cecb_32k_sel_pre.hw,
|
||||
[CLKID_CECB_32K_SEL] = &cecb_32k_sel.hw,
|
||||
[CLKID_CECA_32K_IN] = &ceca_32k_in.hw,
|
||||
[CLKID_CECA_32K_DIV] = &ceca_32k_div.hw,
|
||||
[CLKID_CECA_32K_SEL_PRE] = &ceca_32k_sel_pre.hw,
|
||||
[CLKID_CECA_32K_SEL] = &ceca_32k_sel.hw,
|
||||
[CLKID_DIV2_PRE] = &fclk_div2_divn_pre.hw,
|
||||
[CLKID_24M_DIV2] = &clk_24m_div2.hw,
|
||||
[CLKID_GEN_SEL] = &gen_sel.hw,
|
||||
[CLKID_GEN_DIV] = &gen_div.hw,
|
||||
[CLKID_SARADC_DIV] = &saradc_div.hw,
|
||||
[CLKID_PWM_A_SEL] = &pwm_a_sel.hw,
|
||||
[CLKID_PWM_A_DIV] = &pwm_a_div.hw,
|
||||
[CLKID_PWM_B_SEL] = &pwm_b_sel.hw,
|
||||
[CLKID_PWM_B_DIV] = &pwm_b_div.hw,
|
||||
[CLKID_PWM_C_SEL] = &pwm_c_sel.hw,
|
||||
[CLKID_PWM_C_DIV] = &pwm_c_div.hw,
|
||||
[CLKID_PWM_D_SEL] = &pwm_d_sel.hw,
|
||||
[CLKID_PWM_D_DIV] = &pwm_d_div.hw,
|
||||
[CLKID_PWM_E_SEL] = &pwm_e_sel.hw,
|
||||
[CLKID_PWM_E_DIV] = &pwm_e_div.hw,
|
||||
[CLKID_PWM_F_SEL] = &pwm_f_sel.hw,
|
||||
[CLKID_PWM_F_DIV] = &pwm_f_div.hw,
|
||||
[CLKID_SPICC_SEL] = &spicc_sel.hw,
|
||||
[CLKID_SPICC_DIV] = &spicc_div.hw,
|
||||
[CLKID_SPICC_SEL2] = &spicc_sel2.hw,
|
||||
[CLKID_TS_DIV] = &ts_div.hw,
|
||||
[CLKID_SPIFC_SEL] = &spifc_sel.hw,
|
||||
[CLKID_SPIFC_DIV] = &spifc_div.hw,
|
||||
[CLKID_SPIFC_SEL2] = &spifc_sel2.hw,
|
||||
[CLKID_USB_BUS_SEL] = &usb_bus_sel.hw,
|
||||
[CLKID_USB_BUS_DIV] = &usb_bus_div.hw,
|
||||
[CLKID_SD_EMMC_SEL] = &sd_emmc_sel.hw,
|
||||
[CLKID_SD_EMMC_DIV] = &sd_emmc_div.hw,
|
||||
[CLKID_SD_EMMC_SEL2] = &sd_emmc_sel2.hw,
|
||||
[CLKID_PSRAM_SEL] = &psram_sel.hw,
|
||||
[CLKID_PSRAM_DIV] = &psram_div.hw,
|
||||
[CLKID_PSRAM_SEL2] = &psram_sel2.hw,
|
||||
[CLKID_DMC_SEL] = &dmc_sel.hw,
|
||||
[CLKID_DMC_DIV] = &dmc_div.hw,
|
||||
[CLKID_DMC_SEL2] = &dmc_sel2.hw,
|
||||
};
|
||||
|
||||
/* Convenience table to populate regmap in .probe */
|
||||
|
|
@ -2190,6 +2189,11 @@ static struct regmap_config a1_periphs_regmap_cfg = {
|
|||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static struct meson_clk_hw_data a1_periphs_clks = {
|
||||
.hws = a1_periphs_hw_clks,
|
||||
.num = ARRAY_SIZE(a1_periphs_hw_clks),
|
||||
};
|
||||
|
||||
static int meson_a1_periphs_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -2219,8 +2223,7 @@ static int meson_a1_periphs_probe(struct platform_device *pdev)
|
|||
clkid);
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
&a1_periphs_clks);
|
||||
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_periphs_clks);
|
||||
}
|
||||
|
||||
static const struct of_device_id a1_periphs_clkc_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -43,71 +43,4 @@
|
|||
#define PSRAM_CLK_CTRL 0xf4
|
||||
#define DMC_CLK_CTRL 0xf8
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h>
|
||||
|
||||
/*
|
||||
* CLKID index values for internal clocks
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/a1-peripherals-clkc.h.
|
||||
* Only the clocks ids we don't want to expose, such as the internal muxes and
|
||||
* dividers of composite clocks, will remain defined here.
|
||||
*/
|
||||
#define CLKID_XTAL_IN 0
|
||||
#define CLKID_DSPA_SEL 61
|
||||
#define CLKID_DSPB_SEL 62
|
||||
#define CLKID_SARADC_SEL 74
|
||||
#define CLKID_SYS_A_SEL 89
|
||||
#define CLKID_SYS_A_DIV 90
|
||||
#define CLKID_SYS_A 91
|
||||
#define CLKID_SYS_B_SEL 92
|
||||
#define CLKID_SYS_B_DIV 93
|
||||
#define CLKID_SYS_B 94
|
||||
#define CLKID_DSPA_A_DIV 96
|
||||
#define CLKID_DSPA_A 97
|
||||
#define CLKID_DSPA_B_DIV 99
|
||||
#define CLKID_DSPA_B 100
|
||||
#define CLKID_DSPB_A_DIV 102
|
||||
#define CLKID_DSPB_A 103
|
||||
#define CLKID_DSPB_B_DIV 105
|
||||
#define CLKID_DSPB_B 106
|
||||
#define CLKID_RTC_32K_IN 107
|
||||
#define CLKID_RTC_32K_DIV 108
|
||||
#define CLKID_RTC_32K_XTAL 109
|
||||
#define CLKID_RTC_32K_SEL 110
|
||||
#define CLKID_CECB_32K_IN 111
|
||||
#define CLKID_CECB_32K_DIV 112
|
||||
#define CLKID_CECA_32K_IN 115
|
||||
#define CLKID_CECA_32K_DIV 116
|
||||
#define CLKID_DIV2_PRE 119
|
||||
#define CLKID_24M_DIV2 120
|
||||
#define CLKID_GEN_DIV 122
|
||||
#define CLKID_SARADC_DIV 123
|
||||
#define CLKID_PWM_A_DIV 125
|
||||
#define CLKID_PWM_B_DIV 127
|
||||
#define CLKID_PWM_C_DIV 129
|
||||
#define CLKID_PWM_D_DIV 131
|
||||
#define CLKID_PWM_E_DIV 133
|
||||
#define CLKID_PWM_F_DIV 135
|
||||
#define CLKID_SPICC_SEL 136
|
||||
#define CLKID_SPICC_DIV 137
|
||||
#define CLKID_SPICC_SEL2 138
|
||||
#define CLKID_TS_DIV 139
|
||||
#define CLKID_SPIFC_SEL 140
|
||||
#define CLKID_SPIFC_DIV 141
|
||||
#define CLKID_SPIFC_SEL2 142
|
||||
#define CLKID_USB_BUS_SEL 143
|
||||
#define CLKID_USB_BUS_DIV 144
|
||||
#define CLKID_SD_EMMC_SEL 145
|
||||
#define CLKID_SD_EMMC_DIV 146
|
||||
#define CLKID_PSRAM_SEL 148
|
||||
#define CLKID_PSRAM_DIV 149
|
||||
#define CLKID_PSRAM_SEL2 150
|
||||
#define CLKID_DMC_SEL 151
|
||||
#define CLKID_DMC_DIV 152
|
||||
#define CLKID_DMC_SEL2 153
|
||||
#define NR_CLKS 154
|
||||
|
||||
#endif /* __A1_PERIPHERALS_H */
|
||||
|
|
|
|||
|
|
@ -12,6 +12,9 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include "a1-pll.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "meson-clkc-utils.h"
|
||||
|
||||
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
|
||||
|
||||
static struct clk_regmap fixed_pll_dco = {
|
||||
.data = &(struct meson_clk_pll_data){
|
||||
|
|
@ -268,22 +271,18 @@ static struct clk_regmap fclk_div7 = {
|
|||
};
|
||||
|
||||
/* Array of all clocks registered by this provider */
|
||||
static struct clk_hw_onecell_data a1_pll_clks = {
|
||||
.hws = {
|
||||
[CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
|
||||
[CLKID_FIXED_PLL] = &fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
|
||||
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
|
||||
[CLKID_HIFI_PLL] = &hifi_pll.hw,
|
||||
[NR_PLL_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_PLL_CLKS,
|
||||
static struct clk_hw *a1_pll_hw_clks[] = {
|
||||
[CLKID_FIXED_PLL_DCO] = &fixed_pll_dco.hw,
|
||||
[CLKID_FIXED_PLL] = &fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
|
||||
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
|
||||
[CLKID_HIFI_PLL] = &hifi_pll.hw,
|
||||
};
|
||||
|
||||
static struct clk_regmap *const a1_pll_regmaps[] = {
|
||||
|
|
@ -302,6 +301,11 @@ static struct regmap_config a1_pll_regmap_cfg = {
|
|||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static struct meson_clk_hw_data a1_pll_clks = {
|
||||
.hws = a1_pll_hw_clks,
|
||||
.num = ARRAY_SIZE(a1_pll_hw_clks),
|
||||
};
|
||||
|
||||
static int meson_a1_pll_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -332,7 +336,7 @@ static int meson_a1_pll_probe(struct platform_device *pdev)
|
|||
clkid);
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
|
||||
&a1_pll_clks);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,23 +25,4 @@
|
|||
#define ANACTRL_HIFIPLL_CTRL4 0xd0
|
||||
#define ANACTRL_HIFIPLL_STS 0xd4
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
|
||||
|
||||
/*
|
||||
* CLKID index values for internal clocks
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/a1-pll-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_FIXED_PLL_DCO 0
|
||||
#define CLKID_FCLK_DIV2_DIV 2
|
||||
#define CLKID_FCLK_DIV3_DIV 3
|
||||
#define CLKID_FCLK_DIV5_DIV 4
|
||||
#define CLKID_FCLK_DIV7_DIV 5
|
||||
#define NR_PLL_CLKS 11
|
||||
|
||||
#endif /* __A1_PLL_H */
|
||||
|
|
|
|||
|
|
@ -14,11 +14,13 @@
|
|||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include "meson-aoclk.h"
|
||||
#include "axg-aoclk.h"
|
||||
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-dualdiv.h"
|
||||
|
||||
#include <dt-bindings/clock/axg-aoclkc.h>
|
||||
#include <dt-bindings/reset/axg-aoclkc.h>
|
||||
|
||||
/*
|
||||
* AO Configuration Clock registers offsets
|
||||
* Register offsets from the data sheet must be multiplied by 4.
|
||||
|
|
@ -288,27 +290,24 @@ static struct clk_regmap *axg_aoclk_regmap[] = {
|
|||
&axg_aoclk_saradc_gate,
|
||||
};
|
||||
|
||||
static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
|
||||
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
|
||||
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
|
||||
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
|
||||
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
|
||||
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
|
||||
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
|
||||
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
|
||||
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
|
||||
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
|
||||
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
|
||||
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
|
||||
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
|
||||
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
|
||||
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
|
||||
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *axg_aoclk_hw_clks[] = {
|
||||
[CLKID_AO_REMOTE] = &axg_aoclk_remote.hw,
|
||||
[CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master.hw,
|
||||
[CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave.hw,
|
||||
[CLKID_AO_UART1] = &axg_aoclk_uart1.hw,
|
||||
[CLKID_AO_UART2] = &axg_aoclk_uart2.hw,
|
||||
[CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster.hw,
|
||||
[CLKID_AO_SAR_ADC] = &axg_aoclk_saradc.hw,
|
||||
[CLKID_AO_CLK81] = &axg_aoclk_clk81.hw,
|
||||
[CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw,
|
||||
[CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw,
|
||||
[CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw,
|
||||
[CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw,
|
||||
[CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw,
|
||||
[CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw,
|
||||
[CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw,
|
||||
[CLKID_AO_32K] = &axg_aoclk_32k.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw,
|
||||
};
|
||||
|
||||
static const struct meson_aoclk_data axg_aoclkc_data = {
|
||||
|
|
@ -317,7 +316,10 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
|
|||
.reset = axg_aoclk_reset,
|
||||
.num_clks = ARRAY_SIZE(axg_aoclk_regmap),
|
||||
.clks = axg_aoclk_regmap,
|
||||
.hw_data = &axg_aoclk_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = axg_aoclk_hw_clks,
|
||||
.num = ARRAY_SIZE(axg_aoclk_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id axg_aoclkc_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -1,18 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2017 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* Copyright (c) 2018 Amlogic, inc.
|
||||
* Author: Qiufang Dai <qiufang.dai@amlogic.com>
|
||||
*/
|
||||
|
||||
#ifndef __AXG_AOCLKC_H
|
||||
#define __AXG_AOCLKC_H
|
||||
|
||||
#define NR_CLKS 17
|
||||
|
||||
#include <dt-bindings/clock/axg-aoclkc.h>
|
||||
#include <dt-bindings/reset/axg-aoclkc.h>
|
||||
|
||||
#endif /* __AXG_AOCLKC_H */
|
||||
|
|
@ -15,11 +15,14 @@
|
|||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "meson-clkc-utils.h"
|
||||
#include "axg-audio.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-phase.h"
|
||||
#include "sclk-div.h"
|
||||
|
||||
#include <dt-bindings/clock/axg-audio-clkc.h>
|
||||
|
||||
#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) { \
|
||||
.data = &(struct clk_regmap_gate_data){ \
|
||||
.offset = (_reg), \
|
||||
|
|
@ -811,436 +814,424 @@ static struct clk_regmap sm1_tdm_sclk_pad_2 = AUD_TDM_PAD_CTRL(
|
|||
* Array of all clocks provided by this provider
|
||||
* The input clocks of the controller will be populated at runtime
|
||||
*/
|
||||
static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
|
||||
.hws = {
|
||||
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
|
||||
[AUD_CLKID_PDM] = &pdm.hw,
|
||||
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
|
||||
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
|
||||
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
|
||||
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
|
||||
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
|
||||
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
|
||||
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
|
||||
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
|
||||
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
|
||||
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
|
||||
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
|
||||
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
|
||||
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
|
||||
[AUD_CLKID_LOOPBACK] = &loopback.hw,
|
||||
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
|
||||
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
|
||||
[AUD_CLKID_RESAMPLE] = &resample.hw,
|
||||
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
|
||||
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
|
||||
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
|
||||
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
|
||||
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
|
||||
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
|
||||
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
|
||||
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
|
||||
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
|
||||
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
|
||||
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
|
||||
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
|
||||
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
|
||||
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
|
||||
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
|
||||
[AUD_CLKID_TOP] = &axg_aud_top,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *axg_audio_hw_clks[] = {
|
||||
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
|
||||
[AUD_CLKID_PDM] = &pdm.hw,
|
||||
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
|
||||
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
|
||||
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
|
||||
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
|
||||
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
|
||||
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
|
||||
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
|
||||
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
|
||||
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
|
||||
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
|
||||
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
|
||||
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
|
||||
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
|
||||
[AUD_CLKID_LOOPBACK] = &loopback.hw,
|
||||
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
|
||||
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
|
||||
[AUD_CLKID_RESAMPLE] = &resample.hw,
|
||||
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
|
||||
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
|
||||
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
|
||||
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
|
||||
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
|
||||
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
|
||||
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
|
||||
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
|
||||
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
|
||||
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
|
||||
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
|
||||
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
|
||||
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
|
||||
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
|
||||
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &axg_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &axg_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &axg_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
|
||||
[AUD_CLKID_TOP] = &axg_aud_top,
|
||||
};
|
||||
|
||||
/*
|
||||
* Array of all G12A clocks provided by this provider
|
||||
* The input clocks of the controller will be populated at runtime
|
||||
*/
|
||||
static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
|
||||
.hws = {
|
||||
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
|
||||
[AUD_CLKID_PDM] = &pdm.hw,
|
||||
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
|
||||
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
|
||||
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
|
||||
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
|
||||
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
|
||||
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
|
||||
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
|
||||
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
|
||||
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
|
||||
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
|
||||
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
|
||||
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
|
||||
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
|
||||
[AUD_CLKID_LOOPBACK] = &loopback.hw,
|
||||
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
|
||||
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
|
||||
[AUD_CLKID_RESAMPLE] = &resample.hw,
|
||||
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
|
||||
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
|
||||
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
|
||||
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
|
||||
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
|
||||
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
|
||||
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
|
||||
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
|
||||
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
|
||||
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
|
||||
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
|
||||
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
|
||||
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
|
||||
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
|
||||
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
|
||||
[AUD_CLKID_TOP] = &axg_aud_top,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *g12a_audio_hw_clks[] = {
|
||||
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
|
||||
[AUD_CLKID_PDM] = &pdm.hw,
|
||||
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
|
||||
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
|
||||
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
|
||||
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
|
||||
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
|
||||
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
|
||||
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
|
||||
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
|
||||
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
|
||||
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
|
||||
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
|
||||
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
|
||||
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
|
||||
[AUD_CLKID_LOOPBACK] = &loopback.hw,
|
||||
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
|
||||
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
|
||||
[AUD_CLKID_RESAMPLE] = &resample.hw,
|
||||
[AUD_CLKID_POWER_DETECT] = &power_detect.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_SEL] = &mst_a_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_SEL] = &mst_b_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_SEL] = &mst_c_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_SEL] = &mst_d_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_SEL] = &mst_e_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_SEL] = &mst_f_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_DIV] = &mst_a_mclk_div.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_DIV] = &mst_b_mclk_div.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_DIV] = &mst_c_mclk_div.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_DIV] = &mst_d_mclk_div.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_DIV] = &mst_e_mclk_div.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_DIV] = &mst_f_mclk_div.hw,
|
||||
[AUD_CLKID_MST_A_MCLK] = &mst_a_mclk.hw,
|
||||
[AUD_CLKID_MST_B_MCLK] = &mst_b_mclk.hw,
|
||||
[AUD_CLKID_MST_C_MCLK] = &mst_c_mclk.hw,
|
||||
[AUD_CLKID_MST_D_MCLK] = &mst_d_mclk.hw,
|
||||
[AUD_CLKID_MST_E_MCLK] = &mst_e_mclk.hw,
|
||||
[AUD_CLKID_MST_F_MCLK] = &mst_f_mclk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
|
||||
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
|
||||
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
|
||||
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
|
||||
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
|
||||
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
|
||||
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
|
||||
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
|
||||
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD0] = &g12a_tdm_mclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD1] = &g12a_tdm_mclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD0] = &g12a_tdm_lrclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD1] = &g12a_tdm_lrclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD2] = &g12a_tdm_lrclk_pad_2.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD0] = &g12a_tdm_sclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD1] = &g12a_tdm_sclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD2] = &g12a_tdm_sclk_pad_2.hw,
|
||||
[AUD_CLKID_TOP] = &axg_aud_top,
|
||||
};
|
||||
|
||||
/*
|
||||
* Array of all SM1 clocks provided by this provider
|
||||
* The input clocks of the controller will be populated at runtime
|
||||
*/
|
||||
static struct clk_hw_onecell_data sm1_audio_hw_onecell_data = {
|
||||
.hws = {
|
||||
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
|
||||
[AUD_CLKID_PDM] = &pdm.hw,
|
||||
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
|
||||
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
|
||||
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
|
||||
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
|
||||
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
|
||||
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
|
||||
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
|
||||
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
|
||||
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
|
||||
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
|
||||
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
|
||||
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
|
||||
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
|
||||
[AUD_CLKID_LOOPBACK] = &loopback.hw,
|
||||
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
|
||||
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
|
||||
[AUD_CLKID_RESAMPLE] = &resample.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
|
||||
[AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
|
||||
[AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
|
||||
[AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
|
||||
[AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
|
||||
[AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
|
||||
[AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
|
||||
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
|
||||
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
|
||||
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
|
||||
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
|
||||
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
|
||||
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
|
||||
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
|
||||
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
|
||||
[AUD_CLKID_TOP] = &sm1_aud_top.hw,
|
||||
[AUD_CLKID_TORAM] = &toram.hw,
|
||||
[AUD_CLKID_EQDRC] = &eqdrc.hw,
|
||||
[AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
|
||||
[AUD_CLKID_TOVAD] = &tovad.hw,
|
||||
[AUD_CLKID_LOCKER] = &locker.hw,
|
||||
[AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
|
||||
[AUD_CLKID_FRDDR_D] = &frddr_d.hw,
|
||||
[AUD_CLKID_TODDR_D] = &toddr_d.hw,
|
||||
[AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
|
||||
[AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
|
||||
[AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
|
||||
[AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
|
||||
[AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
|
||||
[AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *sm1_audio_hw_clks[] = {
|
||||
[AUD_CLKID_DDR_ARB] = &ddr_arb.hw,
|
||||
[AUD_CLKID_PDM] = &pdm.hw,
|
||||
[AUD_CLKID_TDMIN_A] = &tdmin_a.hw,
|
||||
[AUD_CLKID_TDMIN_B] = &tdmin_b.hw,
|
||||
[AUD_CLKID_TDMIN_C] = &tdmin_c.hw,
|
||||
[AUD_CLKID_TDMIN_LB] = &tdmin_lb.hw,
|
||||
[AUD_CLKID_TDMOUT_A] = &tdmout_a.hw,
|
||||
[AUD_CLKID_TDMOUT_B] = &tdmout_b.hw,
|
||||
[AUD_CLKID_TDMOUT_C] = &tdmout_c.hw,
|
||||
[AUD_CLKID_FRDDR_A] = &frddr_a.hw,
|
||||
[AUD_CLKID_FRDDR_B] = &frddr_b.hw,
|
||||
[AUD_CLKID_FRDDR_C] = &frddr_c.hw,
|
||||
[AUD_CLKID_TODDR_A] = &toddr_a.hw,
|
||||
[AUD_CLKID_TODDR_B] = &toddr_b.hw,
|
||||
[AUD_CLKID_TODDR_C] = &toddr_c.hw,
|
||||
[AUD_CLKID_LOOPBACK] = &loopback.hw,
|
||||
[AUD_CLKID_SPDIFIN] = &spdifin.hw,
|
||||
[AUD_CLKID_SPDIFOUT] = &spdifout.hw,
|
||||
[AUD_CLKID_RESAMPLE] = &resample.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B] = &spdifout_b.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_SEL] = &sm1_mst_a_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_SEL] = &sm1_mst_b_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_SEL] = &sm1_mst_c_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_SEL] = &sm1_mst_d_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_SEL] = &sm1_mst_e_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_SEL] = &sm1_mst_f_mclk_sel.hw,
|
||||
[AUD_CLKID_MST_A_MCLK_DIV] = &sm1_mst_a_mclk_div.hw,
|
||||
[AUD_CLKID_MST_B_MCLK_DIV] = &sm1_mst_b_mclk_div.hw,
|
||||
[AUD_CLKID_MST_C_MCLK_DIV] = &sm1_mst_c_mclk_div.hw,
|
||||
[AUD_CLKID_MST_D_MCLK_DIV] = &sm1_mst_d_mclk_div.hw,
|
||||
[AUD_CLKID_MST_E_MCLK_DIV] = &sm1_mst_e_mclk_div.hw,
|
||||
[AUD_CLKID_MST_F_MCLK_DIV] = &sm1_mst_f_mclk_div.hw,
|
||||
[AUD_CLKID_MST_A_MCLK] = &sm1_mst_a_mclk.hw,
|
||||
[AUD_CLKID_MST_B_MCLK] = &sm1_mst_b_mclk.hw,
|
||||
[AUD_CLKID_MST_C_MCLK] = &sm1_mst_c_mclk.hw,
|
||||
[AUD_CLKID_MST_D_MCLK] = &sm1_mst_d_mclk.hw,
|
||||
[AUD_CLKID_MST_E_MCLK] = &sm1_mst_e_mclk.hw,
|
||||
[AUD_CLKID_MST_F_MCLK] = &sm1_mst_f_mclk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_SEL] = &spdifout_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK_DIV] = &spdifout_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_CLK] = &spdifout_clk.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_SEL] = &spdifout_b_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK_DIV] = &spdifout_b_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFOUT_B_CLK] = &spdifout_b_clk.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_SEL] = &spdifin_clk_sel.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK_DIV] = &spdifin_clk_div.hw,
|
||||
[AUD_CLKID_SPDIFIN_CLK] = &spdifin_clk.hw,
|
||||
[AUD_CLKID_PDM_DCLK_SEL] = &pdm_dclk_sel.hw,
|
||||
[AUD_CLKID_PDM_DCLK_DIV] = &pdm_dclk_div.hw,
|
||||
[AUD_CLKID_PDM_DCLK] = &pdm_dclk.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_SEL] = &pdm_sysclk_sel.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK_DIV] = &pdm_sysclk_div.hw,
|
||||
[AUD_CLKID_PDM_SYSCLK] = &pdm_sysclk.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_PRE_EN] = &mst_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_PRE_EN] = &mst_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_PRE_EN] = &mst_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_PRE_EN] = &mst_d_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_PRE_EN] = &mst_e_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_PRE_EN] = &mst_f_sclk_pre_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_DIV] = &mst_a_sclk_div.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_DIV] = &mst_b_sclk_div.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_DIV] = &mst_c_sclk_div.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_DIV] = &mst_d_sclk_div.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_DIV] = &mst_e_sclk_div.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_DIV] = &mst_f_sclk_div.hw,
|
||||
[AUD_CLKID_MST_A_SCLK_POST_EN] = &mst_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_B_SCLK_POST_EN] = &mst_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_C_SCLK_POST_EN] = &mst_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_D_SCLK_POST_EN] = &mst_d_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_E_SCLK_POST_EN] = &mst_e_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_F_SCLK_POST_EN] = &mst_f_sclk_post_en.hw,
|
||||
[AUD_CLKID_MST_A_SCLK] = &mst_a_sclk.hw,
|
||||
[AUD_CLKID_MST_B_SCLK] = &mst_b_sclk.hw,
|
||||
[AUD_CLKID_MST_C_SCLK] = &mst_c_sclk.hw,
|
||||
[AUD_CLKID_MST_D_SCLK] = &mst_d_sclk.hw,
|
||||
[AUD_CLKID_MST_E_SCLK] = &mst_e_sclk.hw,
|
||||
[AUD_CLKID_MST_F_SCLK] = &mst_f_sclk.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK_DIV] = &mst_a_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK_DIV] = &mst_b_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK_DIV] = &mst_c_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK_DIV] = &mst_d_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK_DIV] = &mst_e_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK_DIV] = &mst_f_lrclk_div.hw,
|
||||
[AUD_CLKID_MST_A_LRCLK] = &mst_a_lrclk.hw,
|
||||
[AUD_CLKID_MST_B_LRCLK] = &mst_b_lrclk.hw,
|
||||
[AUD_CLKID_MST_C_LRCLK] = &mst_c_lrclk.hw,
|
||||
[AUD_CLKID_MST_D_LRCLK] = &mst_d_lrclk.hw,
|
||||
[AUD_CLKID_MST_E_LRCLK] = &mst_e_lrclk.hw,
|
||||
[AUD_CLKID_MST_F_LRCLK] = &mst_f_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_SEL] = &tdmin_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_SEL] = &tdmin_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_SEL] = &tdmin_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_SEL] = &tdmin_lb_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_SEL] = &tdmout_a_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_SEL] = &tdmout_b_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_SEL] = &tdmout_c_sclk_sel.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &tdmin_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &tdmin_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &tdmin_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &tdmin_lb_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &tdmout_a_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &tdmout_b_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &tdmout_c_sclk_pre_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &tdmin_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &tdmin_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &tdmin_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &tdmin_lb_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &tdmout_a_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &tdmout_b_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &tdmout_c_sclk_post_en.hw,
|
||||
[AUD_CLKID_TDMIN_A_SCLK] = &tdmin_a_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_SCLK] = &tdmin_b_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_SCLK] = &tdmin_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_SCLK] = &tdmin_lb_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_SCLK] = &g12a_tdmout_a_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_SCLK] = &g12a_tdmout_b_sclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_SCLK] = &g12a_tdmout_c_sclk.hw,
|
||||
[AUD_CLKID_TDMIN_A_LRCLK] = &tdmin_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_B_LRCLK] = &tdmin_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_C_LRCLK] = &tdmin_c_lrclk.hw,
|
||||
[AUD_CLKID_TDMIN_LB_LRCLK] = &tdmin_lb_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_A_LRCLK] = &tdmout_a_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_B_LRCLK] = &tdmout_b_lrclk.hw,
|
||||
[AUD_CLKID_TDMOUT_C_LRCLK] = &tdmout_c_lrclk.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD0] = &sm1_tdm_mclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_MCLK_PAD1] = &sm1_tdm_mclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD0] = &sm1_tdm_lrclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD1] = &sm1_tdm_lrclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_LRCLK_PAD2] = &sm1_tdm_lrclk_pad_2.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD0] = &sm1_tdm_sclk_pad_0.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD1] = &sm1_tdm_sclk_pad_1.hw,
|
||||
[AUD_CLKID_TDM_SCLK_PAD2] = &sm1_tdm_sclk_pad_2.hw,
|
||||
[AUD_CLKID_TOP] = &sm1_aud_top.hw,
|
||||
[AUD_CLKID_TORAM] = &toram.hw,
|
||||
[AUD_CLKID_EQDRC] = &eqdrc.hw,
|
||||
[AUD_CLKID_RESAMPLE_B] = &resample_b.hw,
|
||||
[AUD_CLKID_TOVAD] = &tovad.hw,
|
||||
[AUD_CLKID_LOCKER] = &locker.hw,
|
||||
[AUD_CLKID_SPDIFIN_LB] = &spdifin_lb.hw,
|
||||
[AUD_CLKID_FRDDR_D] = &frddr_d.hw,
|
||||
[AUD_CLKID_TODDR_D] = &toddr_d.hw,
|
||||
[AUD_CLKID_LOOPBACK_B] = &loopback_b.hw,
|
||||
[AUD_CLKID_CLK81_EN] = &sm1_clk81_en.hw,
|
||||
[AUD_CLKID_SYSCLK_A_DIV] = &sm1_sysclk_a_div.hw,
|
||||
[AUD_CLKID_SYSCLK_A_EN] = &sm1_sysclk_a_en.hw,
|
||||
[AUD_CLKID_SYSCLK_B_DIV] = &sm1_sysclk_b_div.hw,
|
||||
[AUD_CLKID_SYSCLK_B_EN] = &sm1_sysclk_b_en.hw,
|
||||
};
|
||||
|
||||
|
||||
|
|
@ -1745,7 +1736,7 @@ static const struct regmap_config axg_audio_regmap_cfg = {
|
|||
struct audioclk_data {
|
||||
struct clk_regmap *const *regmap_clks;
|
||||
unsigned int regmap_clk_num;
|
||||
struct clk_hw_onecell_data *hw_onecell_data;
|
||||
struct meson_clk_hw_data hw_clks;
|
||||
unsigned int reset_offset;
|
||||
unsigned int reset_num;
|
||||
};
|
||||
|
|
@ -1791,10 +1782,10 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
|
|||
data->regmap_clks[i]->map = map;
|
||||
|
||||
/* Take care to skip the registered input clocks */
|
||||
for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
|
||||
for (i = AUD_CLKID_DDR_ARB; i < data->hw_clks.num; i++) {
|
||||
const char *name;
|
||||
|
||||
hw = data->hw_onecell_data->hws[i];
|
||||
hw = data->hw_clks.hws[i];
|
||||
/* array might be sparse */
|
||||
if (!hw)
|
||||
continue;
|
||||
|
|
@ -1808,8 +1799,7 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
data->hw_onecell_data);
|
||||
ret = devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -1834,13 +1824,19 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
|
|||
static const struct audioclk_data axg_audioclk_data = {
|
||||
.regmap_clks = axg_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
|
||||
.hw_onecell_data = &axg_audio_hw_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = axg_audio_hw_clks,
|
||||
.num = ARRAY_SIZE(axg_audio_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct audioclk_data g12a_audioclk_data = {
|
||||
.regmap_clks = g12a_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
|
||||
.hw_onecell_data = &g12a_audio_hw_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = g12a_audio_hw_clks,
|
||||
.num = ARRAY_SIZE(g12a_audio_hw_clks),
|
||||
},
|
||||
.reset_offset = AUDIO_SW_RESET,
|
||||
.reset_num = 26,
|
||||
};
|
||||
|
|
@ -1848,7 +1844,10 @@ static const struct audioclk_data g12a_audioclk_data = {
|
|||
static const struct audioclk_data sm1_audioclk_data = {
|
||||
.regmap_clks = sm1_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(sm1_clk_regmaps),
|
||||
.hw_onecell_data = &sm1_audio_hw_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = sm1_audio_hw_clks,
|
||||
.num = ARRAY_SIZE(sm1_audio_hw_clks),
|
||||
},
|
||||
.reset_offset = AUDIO_SM1_SW_RESET0,
|
||||
.reset_num = 39,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -64,80 +64,5 @@
|
|||
#define AUDIO_SM1_SW_RESET1 0x02C
|
||||
#define AUDIO_CLK81_CTRL 0x030
|
||||
#define AUDIO_CLK81_EN 0x034
|
||||
/*
|
||||
* CLKID index values
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
*/
|
||||
|
||||
#define AUD_CLKID_MST_A_MCLK_SEL 59
|
||||
#define AUD_CLKID_MST_B_MCLK_SEL 60
|
||||
#define AUD_CLKID_MST_C_MCLK_SEL 61
|
||||
#define AUD_CLKID_MST_D_MCLK_SEL 62
|
||||
#define AUD_CLKID_MST_E_MCLK_SEL 63
|
||||
#define AUD_CLKID_MST_F_MCLK_SEL 64
|
||||
#define AUD_CLKID_MST_A_MCLK_DIV 65
|
||||
#define AUD_CLKID_MST_B_MCLK_DIV 66
|
||||
#define AUD_CLKID_MST_C_MCLK_DIV 67
|
||||
#define AUD_CLKID_MST_D_MCLK_DIV 68
|
||||
#define AUD_CLKID_MST_E_MCLK_DIV 69
|
||||
#define AUD_CLKID_MST_F_MCLK_DIV 70
|
||||
#define AUD_CLKID_SPDIFOUT_CLK_SEL 71
|
||||
#define AUD_CLKID_SPDIFOUT_CLK_DIV 72
|
||||
#define AUD_CLKID_SPDIFIN_CLK_SEL 73
|
||||
#define AUD_CLKID_SPDIFIN_CLK_DIV 74
|
||||
#define AUD_CLKID_PDM_DCLK_SEL 75
|
||||
#define AUD_CLKID_PDM_DCLK_DIV 76
|
||||
#define AUD_CLKID_PDM_SYSCLK_SEL 77
|
||||
#define AUD_CLKID_PDM_SYSCLK_DIV 78
|
||||
#define AUD_CLKID_MST_A_SCLK_PRE_EN 92
|
||||
#define AUD_CLKID_MST_B_SCLK_PRE_EN 93
|
||||
#define AUD_CLKID_MST_C_SCLK_PRE_EN 94
|
||||
#define AUD_CLKID_MST_D_SCLK_PRE_EN 95
|
||||
#define AUD_CLKID_MST_E_SCLK_PRE_EN 96
|
||||
#define AUD_CLKID_MST_F_SCLK_PRE_EN 97
|
||||
#define AUD_CLKID_MST_A_SCLK_DIV 98
|
||||
#define AUD_CLKID_MST_B_SCLK_DIV 99
|
||||
#define AUD_CLKID_MST_C_SCLK_DIV 100
|
||||
#define AUD_CLKID_MST_D_SCLK_DIV 101
|
||||
#define AUD_CLKID_MST_E_SCLK_DIV 102
|
||||
#define AUD_CLKID_MST_F_SCLK_DIV 103
|
||||
#define AUD_CLKID_MST_A_SCLK_POST_EN 104
|
||||
#define AUD_CLKID_MST_B_SCLK_POST_EN 105
|
||||
#define AUD_CLKID_MST_C_SCLK_POST_EN 106
|
||||
#define AUD_CLKID_MST_D_SCLK_POST_EN 107
|
||||
#define AUD_CLKID_MST_E_SCLK_POST_EN 108
|
||||
#define AUD_CLKID_MST_F_SCLK_POST_EN 109
|
||||
#define AUD_CLKID_MST_A_LRCLK_DIV 110
|
||||
#define AUD_CLKID_MST_B_LRCLK_DIV 111
|
||||
#define AUD_CLKID_MST_C_LRCLK_DIV 112
|
||||
#define AUD_CLKID_MST_D_LRCLK_DIV 113
|
||||
#define AUD_CLKID_MST_E_LRCLK_DIV 114
|
||||
#define AUD_CLKID_MST_F_LRCLK_DIV 115
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
|
||||
#define AUD_CLKID_CLK81_EN 173
|
||||
#define AUD_CLKID_SYSCLK_A_DIV 174
|
||||
#define AUD_CLKID_SYSCLK_B_DIV 175
|
||||
#define AUD_CLKID_SYSCLK_A_EN 176
|
||||
#define AUD_CLKID_SYSCLK_B_EN 177
|
||||
|
||||
/* include the CLKIDs which are part of the DT bindings */
|
||||
#include <dt-bindings/clock/axg-audio-clkc.h>
|
||||
|
||||
#define NR_CLKS 178
|
||||
|
||||
#endif /*__AXG_AUDIO_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -21,6 +21,8 @@
|
|||
#include "axg.h"
|
||||
#include "meson-eeclk.h"
|
||||
|
||||
#include <dt-bindings/clock/axg-clkc.h>
|
||||
|
||||
static DEFINE_SPINLOCK(meson_clk_lock);
|
||||
|
||||
static struct clk_regmap axg_fixed_pll_dco = {
|
||||
|
|
@ -1890,147 +1892,143 @@ static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
|
|||
|
||||
/* Array of all clocks provided by this provider */
|
||||
|
||||
static struct clk_hw_onecell_data axg_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_SYS_PLL] = &axg_sys_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &axg_clk81.hw,
|
||||
[CLKID_MPLL0] = &axg_mpll0.hw,
|
||||
[CLKID_MPLL1] = &axg_mpll1.hw,
|
||||
[CLKID_MPLL2] = &axg_mpll2.hw,
|
||||
[CLKID_MPLL3] = &axg_mpll3.hw,
|
||||
[CLKID_DDR] = &axg_ddr.hw,
|
||||
[CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
|
||||
[CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
|
||||
[CLKID_ISA] = &axg_isa.hw,
|
||||
[CLKID_PL301] = &axg_pl301.hw,
|
||||
[CLKID_PERIPHS] = &axg_periphs.hw,
|
||||
[CLKID_SPICC0] = &axg_spicc_0.hw,
|
||||
[CLKID_I2C] = &axg_i2c.hw,
|
||||
[CLKID_RNG0] = &axg_rng0.hw,
|
||||
[CLKID_UART0] = &axg_uart0.hw,
|
||||
[CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
|
||||
[CLKID_SPICC1] = &axg_spicc_1.hw,
|
||||
[CLKID_PCIE_A] = &axg_pcie_a.hw,
|
||||
[CLKID_PCIE_B] = &axg_pcie_b.hw,
|
||||
[CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
|
||||
[CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
|
||||
[CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
|
||||
[CLKID_DMA] = &axg_dma.hw,
|
||||
[CLKID_SPI] = &axg_spi.hw,
|
||||
[CLKID_AUDIO] = &axg_audio.hw,
|
||||
[CLKID_ETH] = &axg_eth_core.hw,
|
||||
[CLKID_UART1] = &axg_uart1.hw,
|
||||
[CLKID_G2D] = &axg_g2d.hw,
|
||||
[CLKID_USB0] = &axg_usb0.hw,
|
||||
[CLKID_USB1] = &axg_usb1.hw,
|
||||
[CLKID_RESET] = &axg_reset.hw,
|
||||
[CLKID_USB] = &axg_usb_general.hw,
|
||||
[CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &axg_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &axg_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
|
||||
[CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
|
||||
[CLKID_VPU_INTR] = &axg_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_GIC] = &axg_gic.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &axg_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &axg_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
|
||||
[CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
|
||||
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
|
||||
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
|
||||
[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
|
||||
[CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
|
||||
[CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
|
||||
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
|
||||
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
|
||||
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
|
||||
[CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
|
||||
[CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
|
||||
[CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
|
||||
[CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
|
||||
[CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0] = &axg_vpu_0.hw,
|
||||
[CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
|
||||
[CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1] = &axg_vpu_1.hw,
|
||||
[CLKID_VPU] = &axg_vpu.hw,
|
||||
[CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0] = &axg_vapb_0.hw,
|
||||
[CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1] = &axg_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &axg_vapb.hw,
|
||||
[CLKID_VCLK] = &axg_vclk.hw,
|
||||
[CLKID_VCLK2] = &axg_vclk2.hw,
|
||||
[CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &axg_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
|
||||
[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
|
||||
[CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
|
||||
[CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
|
||||
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *axg_hw_clks[] = {
|
||||
[CLKID_SYS_PLL] = &axg_sys_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &axg_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &axg_clk81.hw,
|
||||
[CLKID_MPLL0] = &axg_mpll0.hw,
|
||||
[CLKID_MPLL1] = &axg_mpll1.hw,
|
||||
[CLKID_MPLL2] = &axg_mpll2.hw,
|
||||
[CLKID_MPLL3] = &axg_mpll3.hw,
|
||||
[CLKID_DDR] = &axg_ddr.hw,
|
||||
[CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
|
||||
[CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
|
||||
[CLKID_ISA] = &axg_isa.hw,
|
||||
[CLKID_PL301] = &axg_pl301.hw,
|
||||
[CLKID_PERIPHS] = &axg_periphs.hw,
|
||||
[CLKID_SPICC0] = &axg_spicc_0.hw,
|
||||
[CLKID_I2C] = &axg_i2c.hw,
|
||||
[CLKID_RNG0] = &axg_rng0.hw,
|
||||
[CLKID_UART0] = &axg_uart0.hw,
|
||||
[CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
|
||||
[CLKID_SPICC1] = &axg_spicc_1.hw,
|
||||
[CLKID_PCIE_A] = &axg_pcie_a.hw,
|
||||
[CLKID_PCIE_B] = &axg_pcie_b.hw,
|
||||
[CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
|
||||
[CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
|
||||
[CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
|
||||
[CLKID_DMA] = &axg_dma.hw,
|
||||
[CLKID_SPI] = &axg_spi.hw,
|
||||
[CLKID_AUDIO] = &axg_audio.hw,
|
||||
[CLKID_ETH] = &axg_eth_core.hw,
|
||||
[CLKID_UART1] = &axg_uart1.hw,
|
||||
[CLKID_G2D] = &axg_g2d.hw,
|
||||
[CLKID_USB0] = &axg_usb0.hw,
|
||||
[CLKID_USB1] = &axg_usb1.hw,
|
||||
[CLKID_RESET] = &axg_reset.hw,
|
||||
[CLKID_USB] = &axg_usb_general.hw,
|
||||
[CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &axg_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &axg_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
|
||||
[CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
|
||||
[CLKID_VPU_INTR] = &axg_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_GIC] = &axg_gic.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &axg_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &axg_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
|
||||
[CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
|
||||
[CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
|
||||
[CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
|
||||
[CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
|
||||
[CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
|
||||
[CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
|
||||
[CLKID_PCIE_REF] = &axg_pcie_ref.hw,
|
||||
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
|
||||
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &axg_gen_clk.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
|
||||
[CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
|
||||
[CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
|
||||
[CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
|
||||
[CLKID_VPU_0_DIV] = &axg_vpu_0_div.hw,
|
||||
[CLKID_VPU_0_SEL] = &axg_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0] = &axg_vpu_0.hw,
|
||||
[CLKID_VPU_1_DIV] = &axg_vpu_1_div.hw,
|
||||
[CLKID_VPU_1_SEL] = &axg_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1] = &axg_vpu_1.hw,
|
||||
[CLKID_VPU] = &axg_vpu.hw,
|
||||
[CLKID_VAPB_0_DIV] = &axg_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0_SEL] = &axg_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0] = &axg_vapb_0.hw,
|
||||
[CLKID_VAPB_1_DIV] = &axg_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1_SEL] = &axg_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1] = &axg_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &axg_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &axg_vapb.hw,
|
||||
[CLKID_VCLK] = &axg_vclk.hw,
|
||||
[CLKID_VCLK2] = &axg_vclk2.hw,
|
||||
[CLKID_VCLK_SEL] = &axg_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &axg_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &axg_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &axg_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &axg_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &axg_vclk2_div.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &axg_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &axg_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &axg_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &axg_vclk_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &axg_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &axg_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &axg_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &axg_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK_DIV1] = &axg_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2] = &axg_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4] = &axg_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6] = &axg_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12] = &axg_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &axg_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2] = &axg_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4] = &axg_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6] = &axg_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
|
||||
[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
|
||||
[CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
|
||||
[CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
|
||||
[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
|
||||
};
|
||||
|
||||
/* Convenience table to populate regmap in .probe */
|
||||
|
|
@ -2163,7 +2161,10 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
|
|||
static const struct meson_eeclkc_data axg_clkc_data = {
|
||||
.regmap_clks = axg_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
|
||||
.hw_onecell_data = &axg_hw_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = axg_hw_clks,
|
||||
.num = ARRAY_SIZE(axg_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -102,67 +102,4 @@
|
|||
#define HHI_DPLL_TOP_I 0x318
|
||||
#define HHI_DPLL_TOP2_I 0x31C
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_MPEG_SEL 8
|
||||
#define CLKID_MPEG_DIV 9
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 61
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 62
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 63
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 64
|
||||
#define CLKID_MPLL0_DIV 65
|
||||
#define CLKID_MPLL1_DIV 66
|
||||
#define CLKID_MPLL2_DIV 67
|
||||
#define CLKID_MPLL3_DIV 68
|
||||
#define CLKID_MPLL_PREDIV 70
|
||||
#define CLKID_FCLK_DIV2_DIV 71
|
||||
#define CLKID_FCLK_DIV3_DIV 72
|
||||
#define CLKID_FCLK_DIV4_DIV 73
|
||||
#define CLKID_FCLK_DIV5_DIV 74
|
||||
#define CLKID_FCLK_DIV7_DIV 75
|
||||
#define CLKID_PCIE_PLL 76
|
||||
#define CLKID_PCIE_MUX 77
|
||||
#define CLKID_PCIE_REF 78
|
||||
#define CLKID_GEN_CLK_SEL 82
|
||||
#define CLKID_GEN_CLK_DIV 83
|
||||
#define CLKID_SYS_PLL_DCO 85
|
||||
#define CLKID_FIXED_PLL_DCO 86
|
||||
#define CLKID_GP0_PLL_DCO 87
|
||||
#define CLKID_HIFI_PLL_DCO 88
|
||||
#define CLKID_PCIE_PLL_DCO 89
|
||||
#define CLKID_PCIE_PLL_OD 90
|
||||
#define CLKID_VPU_0_DIV 91
|
||||
#define CLKID_VPU_1_DIV 94
|
||||
#define CLKID_VAPB_0_DIV 98
|
||||
#define CLKID_VAPB_1_DIV 101
|
||||
#define CLKID_VCLK_SEL 108
|
||||
#define CLKID_VCLK2_SEL 109
|
||||
#define CLKID_VCLK_INPUT 110
|
||||
#define CLKID_VCLK2_INPUT 111
|
||||
#define CLKID_VCLK_DIV 112
|
||||
#define CLKID_VCLK2_DIV 113
|
||||
#define CLKID_VCLK_DIV2_EN 114
|
||||
#define CLKID_VCLK_DIV4_EN 115
|
||||
#define CLKID_VCLK_DIV6_EN 116
|
||||
#define CLKID_VCLK_DIV12_EN 117
|
||||
#define CLKID_VCLK2_DIV2_EN 118
|
||||
#define CLKID_VCLK2_DIV4_EN 119
|
||||
#define CLKID_VCLK2_DIV6_EN 120
|
||||
#define CLKID_VCLK2_DIV12_EN 121
|
||||
#define CLKID_CTS_ENCL_SEL 132
|
||||
#define CLKID_VDIN_MEAS_SEL 134
|
||||
#define CLKID_VDIN_MEAS_DIV 135
|
||||
|
||||
#define NR_CLKS 137
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/axg-clkc.h>
|
||||
|
||||
#endif /* __AXG_H */
|
||||
|
|
|
|||
|
|
@ -14,11 +14,13 @@
|
|||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include "meson-aoclk.h"
|
||||
#include "g12a-aoclk.h"
|
||||
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-dualdiv.h"
|
||||
|
||||
#include <dt-bindings/clock/g12a-aoclkc.h>
|
||||
#include <dt-bindings/reset/g12a-aoclkc.h>
|
||||
|
||||
/*
|
||||
* AO Configuration Clock registers offsets
|
||||
* Register offsets from the data sheet must be multiplied by 4.
|
||||
|
|
@ -411,39 +413,36 @@ static struct clk_regmap *g12a_aoclk_regmap[] = {
|
|||
&g12a_aoclk_saradc_gate,
|
||||
};
|
||||
|
||||
static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
|
||||
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
|
||||
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
|
||||
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
|
||||
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
|
||||
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
|
||||
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
|
||||
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
|
||||
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
|
||||
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
|
||||
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
|
||||
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
|
||||
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
|
||||
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
|
||||
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
|
||||
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
|
||||
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
|
||||
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
|
||||
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
|
||||
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
|
||||
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
|
||||
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
|
||||
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
|
||||
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
|
||||
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
|
||||
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
|
||||
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *g12a_aoclk_hw_clks[] = {
|
||||
[CLKID_AO_AHB] = &g12a_aoclk_ahb.hw,
|
||||
[CLKID_AO_IR_IN] = &g12a_aoclk_ir_in.hw,
|
||||
[CLKID_AO_I2C_M0] = &g12a_aoclk_i2c_m0.hw,
|
||||
[CLKID_AO_I2C_S0] = &g12a_aoclk_i2c_s0.hw,
|
||||
[CLKID_AO_UART] = &g12a_aoclk_uart.hw,
|
||||
[CLKID_AO_PROD_I2C] = &g12a_aoclk_prod_i2c.hw,
|
||||
[CLKID_AO_UART2] = &g12a_aoclk_uart2.hw,
|
||||
[CLKID_AO_IR_OUT] = &g12a_aoclk_ir_out.hw,
|
||||
[CLKID_AO_SAR_ADC] = &g12a_aoclk_saradc.hw,
|
||||
[CLKID_AO_MAILBOX] = &g12a_aoclk_mailbox.hw,
|
||||
[CLKID_AO_M3] = &g12a_aoclk_m3.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &g12a_aoclk_ahb_sram.hw,
|
||||
[CLKID_AO_RTI] = &g12a_aoclk_rti.hw,
|
||||
[CLKID_AO_M4_FCLK] = &g12a_aoclk_m4_fclk.hw,
|
||||
[CLKID_AO_M4_HCLK] = &g12a_aoclk_m4_hclk.hw,
|
||||
[CLKID_AO_CLK81] = &g12a_aoclk_clk81.hw,
|
||||
[CLKID_AO_SAR_ADC_SEL] = &g12a_aoclk_saradc_mux.hw,
|
||||
[CLKID_AO_SAR_ADC_DIV] = &g12a_aoclk_saradc_div.hw,
|
||||
[CLKID_AO_SAR_ADC_CLK] = &g12a_aoclk_saradc_gate.hw,
|
||||
[CLKID_AO_CTS_OSCIN] = &g12a_aoclk_cts_oscin.hw,
|
||||
[CLKID_AO_32K_PRE] = &g12a_aoclk_32k_by_oscin_pre.hw,
|
||||
[CLKID_AO_32K_DIV] = &g12a_aoclk_32k_by_oscin_div.hw,
|
||||
[CLKID_AO_32K_SEL] = &g12a_aoclk_32k_by_oscin_sel.hw,
|
||||
[CLKID_AO_32K] = &g12a_aoclk_32k_by_oscin.hw,
|
||||
[CLKID_AO_CEC_PRE] = &g12a_aoclk_cec_pre.hw,
|
||||
[CLKID_AO_CEC_DIV] = &g12a_aoclk_cec_div.hw,
|
||||
[CLKID_AO_CEC_SEL] = &g12a_aoclk_cec_sel.hw,
|
||||
[CLKID_AO_CEC] = &g12a_aoclk_cec.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &g12a_aoclk_cts_rtc_oscin.hw,
|
||||
};
|
||||
|
||||
static const struct meson_aoclk_data g12a_aoclkc_data = {
|
||||
|
|
@ -452,7 +451,10 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
|
|||
.reset = g12a_aoclk_reset,
|
||||
.num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
|
||||
.clks = g12a_aoclk_regmap,
|
||||
.hw_data = &g12a_aoclk_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = g12a_aoclk_hw_clks,
|
||||
.num = ARRAY_SIZE(g12a_aoclk_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id g12a_aoclkc_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2019 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __G12A_AOCLKC_H
|
||||
#define __G12A_AOCLKC_H
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/g12a-aoclkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_AO_SAR_ADC_DIV 17
|
||||
#define CLKID_AO_32K_PRE 20
|
||||
#define CLKID_AO_32K_DIV 21
|
||||
#define CLKID_AO_32K_SEL 22
|
||||
#define CLKID_AO_CEC_PRE 24
|
||||
#define CLKID_AO_CEC_DIV 25
|
||||
#define CLKID_AO_CEC_SEL 26
|
||||
|
||||
#define NR_CLKS 29
|
||||
|
||||
#include <dt-bindings/clock/g12a-aoclkc.h>
|
||||
#include <dt-bindings/reset/g12a-aoclkc.h>
|
||||
|
||||
#endif /* __G12A_AOCLKC_H */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -126,149 +126,4 @@
|
|||
#define HHI_SYS1_PLL_CNTL5 0x394
|
||||
#define HHI_SYS1_PLL_CNTL6 0x398
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/g12a-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
#define CLKID_MPEG_SEL 8
|
||||
#define CLKID_MPEG_DIV 9
|
||||
#define CLKID_SD_EMMC_A_CLK0_SEL 63
|
||||
#define CLKID_SD_EMMC_A_CLK0_DIV 64
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 65
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 66
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 67
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 68
|
||||
#define CLKID_MPLL0_DIV 69
|
||||
#define CLKID_MPLL1_DIV 70
|
||||
#define CLKID_MPLL2_DIV 71
|
||||
#define CLKID_MPLL3_DIV 72
|
||||
#define CLKID_MPLL_PREDIV 73
|
||||
#define CLKID_FCLK_DIV2_DIV 75
|
||||
#define CLKID_FCLK_DIV3_DIV 76
|
||||
#define CLKID_FCLK_DIV4_DIV 77
|
||||
#define CLKID_FCLK_DIV5_DIV 78
|
||||
#define CLKID_FCLK_DIV7_DIV 79
|
||||
#define CLKID_FCLK_DIV2P5_DIV 100
|
||||
#define CLKID_FIXED_PLL_DCO 101
|
||||
#define CLKID_SYS_PLL_DCO 102
|
||||
#define CLKID_GP0_PLL_DCO 103
|
||||
#define CLKID_HIFI_PLL_DCO 104
|
||||
#define CLKID_VPU_0_DIV 111
|
||||
#define CLKID_VPU_1_DIV 114
|
||||
#define CLKID_VAPB_0_DIV 118
|
||||
#define CLKID_VAPB_1_DIV 121
|
||||
#define CLKID_HDMI_PLL_DCO 125
|
||||
#define CLKID_HDMI_PLL_OD 126
|
||||
#define CLKID_HDMI_PLL_OD2 127
|
||||
#define CLKID_VID_PLL_SEL 130
|
||||
#define CLKID_VID_PLL_DIV 131
|
||||
#define CLKID_VCLK_SEL 132
|
||||
#define CLKID_VCLK2_SEL 133
|
||||
#define CLKID_VCLK_INPUT 134
|
||||
#define CLKID_VCLK2_INPUT 135
|
||||
#define CLKID_VCLK_DIV 136
|
||||
#define CLKID_VCLK2_DIV 137
|
||||
#define CLKID_VCLK_DIV2_EN 140
|
||||
#define CLKID_VCLK_DIV4_EN 141
|
||||
#define CLKID_VCLK_DIV6_EN 142
|
||||
#define CLKID_VCLK_DIV12_EN 143
|
||||
#define CLKID_VCLK2_DIV2_EN 144
|
||||
#define CLKID_VCLK2_DIV4_EN 145
|
||||
#define CLKID_VCLK2_DIV6_EN 146
|
||||
#define CLKID_VCLK2_DIV12_EN 147
|
||||
#define CLKID_CTS_ENCI_SEL 158
|
||||
#define CLKID_CTS_ENCP_SEL 159
|
||||
#define CLKID_CTS_VDAC_SEL 160
|
||||
#define CLKID_HDMI_TX_SEL 161
|
||||
#define CLKID_HDMI_SEL 166
|
||||
#define CLKID_HDMI_DIV 167
|
||||
#define CLKID_MALI_0_DIV 170
|
||||
#define CLKID_MALI_1_DIV 173
|
||||
#define CLKID_MPLL_50M_DIV 176
|
||||
#define CLKID_SYS_PLL_DIV16_EN 178
|
||||
#define CLKID_SYS_PLL_DIV16 179
|
||||
#define CLKID_CPU_CLK_DYN0_SEL 180
|
||||
#define CLKID_CPU_CLK_DYN0_DIV 181
|
||||
#define CLKID_CPU_CLK_DYN0 182
|
||||
#define CLKID_CPU_CLK_DYN1_SEL 183
|
||||
#define CLKID_CPU_CLK_DYN1_DIV 184
|
||||
#define CLKID_CPU_CLK_DYN1 185
|
||||
#define CLKID_CPU_CLK_DYN 186
|
||||
#define CLKID_CPU_CLK_DIV16_EN 188
|
||||
#define CLKID_CPU_CLK_DIV16 189
|
||||
#define CLKID_CPU_CLK_APB_DIV 190
|
||||
#define CLKID_CPU_CLK_APB 191
|
||||
#define CLKID_CPU_CLK_ATB_DIV 192
|
||||
#define CLKID_CPU_CLK_ATB 193
|
||||
#define CLKID_CPU_CLK_AXI_DIV 194
|
||||
#define CLKID_CPU_CLK_AXI 195
|
||||
#define CLKID_CPU_CLK_TRACE_DIV 196
|
||||
#define CLKID_CPU_CLK_TRACE 197
|
||||
#define CLKID_PCIE_PLL_DCO 198
|
||||
#define CLKID_PCIE_PLL_DCO_DIV2 199
|
||||
#define CLKID_PCIE_PLL_OD 200
|
||||
#define CLKID_VDEC_1_SEL 202
|
||||
#define CLKID_VDEC_1_DIV 203
|
||||
#define CLKID_VDEC_HEVC_SEL 205
|
||||
#define CLKID_VDEC_HEVC_DIV 206
|
||||
#define CLKID_VDEC_HEVCF_SEL 208
|
||||
#define CLKID_VDEC_HEVCF_DIV 209
|
||||
#define CLKID_TS_DIV 211
|
||||
#define CLKID_SYS1_PLL_DCO 213
|
||||
#define CLKID_SYS1_PLL 214
|
||||
#define CLKID_SYS1_PLL_DIV16_EN 215
|
||||
#define CLKID_SYS1_PLL_DIV16 216
|
||||
#define CLKID_CPUB_CLK_DYN0_SEL 217
|
||||
#define CLKID_CPUB_CLK_DYN0_DIV 218
|
||||
#define CLKID_CPUB_CLK_DYN0 219
|
||||
#define CLKID_CPUB_CLK_DYN1_SEL 220
|
||||
#define CLKID_CPUB_CLK_DYN1_DIV 221
|
||||
#define CLKID_CPUB_CLK_DYN1 222
|
||||
#define CLKID_CPUB_CLK_DYN 223
|
||||
#define CLKID_CPUB_CLK_DIV16_EN 225
|
||||
#define CLKID_CPUB_CLK_DIV16 226
|
||||
#define CLKID_CPUB_CLK_DIV2 227
|
||||
#define CLKID_CPUB_CLK_DIV3 228
|
||||
#define CLKID_CPUB_CLK_DIV4 229
|
||||
#define CLKID_CPUB_CLK_DIV5 230
|
||||
#define CLKID_CPUB_CLK_DIV6 231
|
||||
#define CLKID_CPUB_CLK_DIV7 232
|
||||
#define CLKID_CPUB_CLK_DIV8 233
|
||||
#define CLKID_CPUB_CLK_APB_SEL 234
|
||||
#define CLKID_CPUB_CLK_APB 235
|
||||
#define CLKID_CPUB_CLK_ATB_SEL 236
|
||||
#define CLKID_CPUB_CLK_ATB 237
|
||||
#define CLKID_CPUB_CLK_AXI_SEL 238
|
||||
#define CLKID_CPUB_CLK_AXI 239
|
||||
#define CLKID_CPUB_CLK_TRACE_SEL 240
|
||||
#define CLKID_CPUB_CLK_TRACE 241
|
||||
#define CLKID_GP1_PLL_DCO 242
|
||||
#define CLKID_DSU_CLK_DYN0_SEL 244
|
||||
#define CLKID_DSU_CLK_DYN0_DIV 245
|
||||
#define CLKID_DSU_CLK_DYN0 246
|
||||
#define CLKID_DSU_CLK_DYN1_SEL 247
|
||||
#define CLKID_DSU_CLK_DYN1_DIV 248
|
||||
#define CLKID_DSU_CLK_DYN1 249
|
||||
#define CLKID_DSU_CLK_DYN 250
|
||||
#define CLKID_DSU_CLK_FINAL 251
|
||||
#define CLKID_SPICC0_SCLK_SEL 256
|
||||
#define CLKID_SPICC0_SCLK_DIV 257
|
||||
#define CLKID_SPICC1_SCLK_SEL 259
|
||||
#define CLKID_SPICC1_SCLK_DIV 260
|
||||
#define CLKID_NNA_AXI_CLK_SEL 262
|
||||
#define CLKID_NNA_AXI_CLK_DIV 263
|
||||
#define CLKID_NNA_CORE_CLK_SEL 265
|
||||
#define CLKID_NNA_CORE_CLK_DIV 266
|
||||
#define CLKID_MIPI_DSI_PXCLK_DIV 268
|
||||
|
||||
#define NR_CLKS 271
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/g12a-clkc.h>
|
||||
|
||||
#endif /* __G12A_H */
|
||||
|
|
|
|||
|
|
@ -7,11 +7,13 @@
|
|||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include "meson-aoclk.h"
|
||||
#include "gxbb-aoclk.h"
|
||||
|
||||
#include "clk-regmap.h"
|
||||
#include "clk-dualdiv.h"
|
||||
|
||||
#include <dt-bindings/clock/gxbb-aoclkc.h>
|
||||
#include <dt-bindings/reset/gxbb-aoclkc.h>
|
||||
|
||||
/* AO Configuration Clock registers offsets */
|
||||
#define AO_RTI_PWR_CNTL_REG1 0x0c
|
||||
#define AO_RTI_PWR_CNTL_REG0 0x10
|
||||
|
|
@ -252,8 +254,7 @@ static struct clk_regmap *gxbb_aoclk[] = {
|
|||
&ao_cts_cec,
|
||||
};
|
||||
|
||||
static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
|
||||
.hws = {
|
||||
static struct clk_hw *gxbb_aoclk_hw_clks[] = {
|
||||
[CLKID_AO_REMOTE] = &remote_ao.hw,
|
||||
[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,
|
||||
[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,
|
||||
|
|
@ -268,8 +269,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
|
|||
[CLKID_AO_32K] = &ao_32k.hw,
|
||||
[CLKID_AO_CTS_RTC_OSCIN] = &ao_cts_rtc_oscin.hw,
|
||||
[CLKID_AO_CLK81] = &ao_clk81.hw,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
};
|
||||
|
||||
static const struct meson_aoclk_data gxbb_aoclkc_data = {
|
||||
|
|
@ -278,7 +277,10 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
|
|||
.reset = gxbb_aoclk_reset,
|
||||
.num_clks = ARRAY_SIZE(gxbb_aoclk),
|
||||
.clks = gxbb_aoclk,
|
||||
.hw_data = &gxbb_aoclk_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = gxbb_aoclk_hw_clks,
|
||||
.num = ARRAY_SIZE(gxbb_aoclk_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id gxbb_aoclkc_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -1,15 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (c) 2017 BayLibre, SAS
|
||||
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
||||
*/
|
||||
|
||||
#ifndef __GXBB_AOCLKC_H
|
||||
#define __GXBB_AOCLKC_H
|
||||
|
||||
#define NR_CLKS 14
|
||||
|
||||
#include <dt-bindings/clock/gxbb-aoclkc.h>
|
||||
#include <dt-bindings/reset/gxbb-aoclkc.h>
|
||||
|
||||
#endif /* __GXBB_AOCLKC_H */
|
||||
|
|
@ -17,6 +17,8 @@
|
|||
#include "meson-eeclk.h"
|
||||
#include "vid-pll-div.h"
|
||||
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
||||
static DEFINE_SPINLOCK(meson_clk_lock);
|
||||
|
||||
static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
|
||||
|
|
@ -2728,428 +2730,420 @@ static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
|
|||
|
||||
/* Array of all clocks provided by this provider */
|
||||
|
||||
static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
|
||||
[CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &gxbb_clk81.hw,
|
||||
[CLKID_MPLL0] = &gxbb_mpll0.hw,
|
||||
[CLKID_MPLL1] = &gxbb_mpll1.hw,
|
||||
[CLKID_MPLL2] = &gxbb_mpll2.hw,
|
||||
[CLKID_DDR] = &gxbb_ddr.hw,
|
||||
[CLKID_DOS] = &gxbb_dos.hw,
|
||||
[CLKID_ISA] = &gxbb_isa.hw,
|
||||
[CLKID_PL301] = &gxbb_pl301.hw,
|
||||
[CLKID_PERIPHS] = &gxbb_periphs.hw,
|
||||
[CLKID_SPICC] = &gxbb_spicc.hw,
|
||||
[CLKID_I2C] = &gxbb_i2c.hw,
|
||||
[CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
|
||||
[CLKID_SMART_CARD] = &gxbb_smart_card.hw,
|
||||
[CLKID_RNG0] = &gxbb_rng0.hw,
|
||||
[CLKID_UART0] = &gxbb_uart0.hw,
|
||||
[CLKID_SDHC] = &gxbb_sdhc.hw,
|
||||
[CLKID_STREAM] = &gxbb_stream.hw,
|
||||
[CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
|
||||
[CLKID_SDIO] = &gxbb_sdio.hw,
|
||||
[CLKID_ABUF] = &gxbb_abuf.hw,
|
||||
[CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
|
||||
[CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
|
||||
[CLKID_SPI] = &gxbb_spi.hw,
|
||||
[CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
|
||||
[CLKID_ETH] = &gxbb_eth.hw,
|
||||
[CLKID_DEMUX] = &gxbb_demux.hw,
|
||||
[CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
|
||||
[CLKID_IEC958] = &gxbb_iec958.hw,
|
||||
[CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
|
||||
[CLKID_AMCLK] = &gxbb_amclk.hw,
|
||||
[CLKID_AIFIFO2] = &gxbb_aififo2.hw,
|
||||
[CLKID_MIXER] = &gxbb_mixer.hw,
|
||||
[CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
|
||||
[CLKID_ADC] = &gxbb_adc.hw,
|
||||
[CLKID_BLKMV] = &gxbb_blkmv.hw,
|
||||
[CLKID_AIU] = &gxbb_aiu.hw,
|
||||
[CLKID_UART1] = &gxbb_uart1.hw,
|
||||
[CLKID_G2D] = &gxbb_g2d.hw,
|
||||
[CLKID_USB0] = &gxbb_usb0.hw,
|
||||
[CLKID_USB1] = &gxbb_usb1.hw,
|
||||
[CLKID_RESET] = &gxbb_reset.hw,
|
||||
[CLKID_NAND] = &gxbb_nand.hw,
|
||||
[CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
|
||||
[CLKID_USB] = &gxbb_usb.hw,
|
||||
[CLKID_VDIN1] = &gxbb_vdin1.hw,
|
||||
[CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &gxbb_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
|
||||
[CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
|
||||
[CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
|
||||
[CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
|
||||
[CLKID_DVIN] = &gxbb_dvin.hw,
|
||||
[CLKID_UART2] = &gxbb_uart2.hw,
|
||||
[CLKID_SANA] = &gxbb_sana.hw,
|
||||
[CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
|
||||
[CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
|
||||
[CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
|
||||
[CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
|
||||
[CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &gxbb_enc480p.hw,
|
||||
[CLKID_RNG1] = &gxbb_rng1.hw,
|
||||
[CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
|
||||
[CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
|
||||
[CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
|
||||
[CLKID_EDP] = &gxbb_edp.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
|
||||
[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
|
||||
[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
|
||||
[CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
|
||||
[CLKID_MALI_0] = &gxbb_mali_0.hw,
|
||||
[CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
|
||||
[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &gxbb_mali_1.hw,
|
||||
[CLKID_MALI] = &gxbb_mali.hw,
|
||||
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
|
||||
[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
|
||||
[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
|
||||
[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
|
||||
[CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &gxbb_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &gxbb_vpu_1.hw,
|
||||
[CLKID_VPU] = &gxbb_vpu.hw,
|
||||
[CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0] = &gxbb_vapb_0.hw,
|
||||
[CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &gxbb_vapb.hw,
|
||||
[CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
|
||||
[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
|
||||
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
|
||||
[CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
|
||||
[CLKID_VDEC_1] = &gxbb_vdec_1.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
|
||||
[CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
|
||||
[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &gxbb_vclk.hw,
|
||||
[CLKID_VCLK2] = &gxbb_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
|
||||
[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *gxbb_hw_clks[] = {
|
||||
[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
|
||||
[CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &gxbb_clk81.hw,
|
||||
[CLKID_MPLL0] = &gxbb_mpll0.hw,
|
||||
[CLKID_MPLL1] = &gxbb_mpll1.hw,
|
||||
[CLKID_MPLL2] = &gxbb_mpll2.hw,
|
||||
[CLKID_DDR] = &gxbb_ddr.hw,
|
||||
[CLKID_DOS] = &gxbb_dos.hw,
|
||||
[CLKID_ISA] = &gxbb_isa.hw,
|
||||
[CLKID_PL301] = &gxbb_pl301.hw,
|
||||
[CLKID_PERIPHS] = &gxbb_periphs.hw,
|
||||
[CLKID_SPICC] = &gxbb_spicc.hw,
|
||||
[CLKID_I2C] = &gxbb_i2c.hw,
|
||||
[CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
|
||||
[CLKID_SMART_CARD] = &gxbb_smart_card.hw,
|
||||
[CLKID_RNG0] = &gxbb_rng0.hw,
|
||||
[CLKID_UART0] = &gxbb_uart0.hw,
|
||||
[CLKID_SDHC] = &gxbb_sdhc.hw,
|
||||
[CLKID_STREAM] = &gxbb_stream.hw,
|
||||
[CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
|
||||
[CLKID_SDIO] = &gxbb_sdio.hw,
|
||||
[CLKID_ABUF] = &gxbb_abuf.hw,
|
||||
[CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
|
||||
[CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
|
||||
[CLKID_SPI] = &gxbb_spi.hw,
|
||||
[CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
|
||||
[CLKID_ETH] = &gxbb_eth.hw,
|
||||
[CLKID_DEMUX] = &gxbb_demux.hw,
|
||||
[CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
|
||||
[CLKID_IEC958] = &gxbb_iec958.hw,
|
||||
[CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
|
||||
[CLKID_AMCLK] = &gxbb_amclk.hw,
|
||||
[CLKID_AIFIFO2] = &gxbb_aififo2.hw,
|
||||
[CLKID_MIXER] = &gxbb_mixer.hw,
|
||||
[CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
|
||||
[CLKID_ADC] = &gxbb_adc.hw,
|
||||
[CLKID_BLKMV] = &gxbb_blkmv.hw,
|
||||
[CLKID_AIU] = &gxbb_aiu.hw,
|
||||
[CLKID_UART1] = &gxbb_uart1.hw,
|
||||
[CLKID_G2D] = &gxbb_g2d.hw,
|
||||
[CLKID_USB0] = &gxbb_usb0.hw,
|
||||
[CLKID_USB1] = &gxbb_usb1.hw,
|
||||
[CLKID_RESET] = &gxbb_reset.hw,
|
||||
[CLKID_NAND] = &gxbb_nand.hw,
|
||||
[CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
|
||||
[CLKID_USB] = &gxbb_usb.hw,
|
||||
[CLKID_VDIN1] = &gxbb_vdin1.hw,
|
||||
[CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &gxbb_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
|
||||
[CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
|
||||
[CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
|
||||
[CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
|
||||
[CLKID_DVIN] = &gxbb_dvin.hw,
|
||||
[CLKID_UART2] = &gxbb_uart2.hw,
|
||||
[CLKID_SANA] = &gxbb_sana.hw,
|
||||
[CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
|
||||
[CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
|
||||
[CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
|
||||
[CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
|
||||
[CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &gxbb_enc480p.hw,
|
||||
[CLKID_RNG1] = &gxbb_rng1.hw,
|
||||
[CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
|
||||
[CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
|
||||
[CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
|
||||
[CLKID_EDP] = &gxbb_edp.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
|
||||
[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
|
||||
[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
|
||||
[CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
|
||||
[CLKID_MALI_0] = &gxbb_mali_0.hw,
|
||||
[CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
|
||||
[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &gxbb_mali_1.hw,
|
||||
[CLKID_MALI] = &gxbb_mali.hw,
|
||||
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
|
||||
[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
|
||||
[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
|
||||
[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
|
||||
[CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &gxbb_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &gxbb_vpu_1.hw,
|
||||
[CLKID_VPU] = &gxbb_vpu.hw,
|
||||
[CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0] = &gxbb_vapb_0.hw,
|
||||
[CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &gxbb_vapb.hw,
|
||||
[CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
|
||||
[CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
|
||||
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
|
||||
[CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
|
||||
[CLKID_VDEC_1] = &gxbb_vdec_1.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
|
||||
[CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
|
||||
[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &gxbb_vclk.hw,
|
||||
[CLKID_VCLK2] = &gxbb_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
|
||||
[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
};
|
||||
|
||||
static struct clk_hw_onecell_data gxl_hw_onecell_data = {
|
||||
.hws = {
|
||||
[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
|
||||
[CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &gxbb_clk81.hw,
|
||||
[CLKID_MPLL0] = &gxbb_mpll0.hw,
|
||||
[CLKID_MPLL1] = &gxbb_mpll1.hw,
|
||||
[CLKID_MPLL2] = &gxbb_mpll2.hw,
|
||||
[CLKID_DDR] = &gxbb_ddr.hw,
|
||||
[CLKID_DOS] = &gxbb_dos.hw,
|
||||
[CLKID_ISA] = &gxbb_isa.hw,
|
||||
[CLKID_PL301] = &gxbb_pl301.hw,
|
||||
[CLKID_PERIPHS] = &gxbb_periphs.hw,
|
||||
[CLKID_SPICC] = &gxbb_spicc.hw,
|
||||
[CLKID_I2C] = &gxbb_i2c.hw,
|
||||
[CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
|
||||
[CLKID_SMART_CARD] = &gxbb_smart_card.hw,
|
||||
[CLKID_RNG0] = &gxbb_rng0.hw,
|
||||
[CLKID_UART0] = &gxbb_uart0.hw,
|
||||
[CLKID_SDHC] = &gxbb_sdhc.hw,
|
||||
[CLKID_STREAM] = &gxbb_stream.hw,
|
||||
[CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
|
||||
[CLKID_SDIO] = &gxbb_sdio.hw,
|
||||
[CLKID_ABUF] = &gxbb_abuf.hw,
|
||||
[CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
|
||||
[CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
|
||||
[CLKID_SPI] = &gxbb_spi.hw,
|
||||
[CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
|
||||
[CLKID_ETH] = &gxbb_eth.hw,
|
||||
[CLKID_DEMUX] = &gxbb_demux.hw,
|
||||
[CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
|
||||
[CLKID_IEC958] = &gxbb_iec958.hw,
|
||||
[CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
|
||||
[CLKID_AMCLK] = &gxbb_amclk.hw,
|
||||
[CLKID_AIFIFO2] = &gxbb_aififo2.hw,
|
||||
[CLKID_MIXER] = &gxbb_mixer.hw,
|
||||
[CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
|
||||
[CLKID_ADC] = &gxbb_adc.hw,
|
||||
[CLKID_BLKMV] = &gxbb_blkmv.hw,
|
||||
[CLKID_AIU] = &gxbb_aiu.hw,
|
||||
[CLKID_UART1] = &gxbb_uart1.hw,
|
||||
[CLKID_G2D] = &gxbb_g2d.hw,
|
||||
[CLKID_USB0] = &gxbb_usb0.hw,
|
||||
[CLKID_USB1] = &gxbb_usb1.hw,
|
||||
[CLKID_RESET] = &gxbb_reset.hw,
|
||||
[CLKID_NAND] = &gxbb_nand.hw,
|
||||
[CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
|
||||
[CLKID_USB] = &gxbb_usb.hw,
|
||||
[CLKID_VDIN1] = &gxbb_vdin1.hw,
|
||||
[CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &gxbb_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
|
||||
[CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
|
||||
[CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
|
||||
[CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
|
||||
[CLKID_DVIN] = &gxbb_dvin.hw,
|
||||
[CLKID_UART2] = &gxbb_uart2.hw,
|
||||
[CLKID_SANA] = &gxbb_sana.hw,
|
||||
[CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
|
||||
[CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
|
||||
[CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
|
||||
[CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
|
||||
[CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &gxbb_enc480p.hw,
|
||||
[CLKID_RNG1] = &gxbb_rng1.hw,
|
||||
[CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
|
||||
[CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
|
||||
[CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
|
||||
[CLKID_EDP] = &gxbb_edp.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
|
||||
[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
|
||||
[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
|
||||
[CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
|
||||
[CLKID_MALI_0] = &gxbb_mali_0.hw,
|
||||
[CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
|
||||
[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &gxbb_mali_1.hw,
|
||||
[CLKID_MALI] = &gxbb_mali.hw,
|
||||
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
|
||||
[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
|
||||
[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
|
||||
[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
|
||||
[CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &gxbb_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &gxbb_vpu_1.hw,
|
||||
[CLKID_VPU] = &gxbb_vpu.hw,
|
||||
[CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0] = &gxbb_vapb_0.hw,
|
||||
[CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &gxbb_vapb.hw,
|
||||
[CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
|
||||
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
|
||||
[CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
|
||||
[CLKID_VDEC_1] = &gxbb_vdec_1.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
|
||||
[CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
|
||||
[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &gxbb_vclk.hw,
|
||||
[CLKID_VCLK2] = &gxbb_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
|
||||
[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
[CLKID_ACODEC] = &gxl_acodec.hw,
|
||||
[NR_CLKS] = NULL,
|
||||
},
|
||||
.num = NR_CLKS,
|
||||
static struct clk_hw *gxl_hw_clks[] = {
|
||||
[CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
|
||||
[CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
|
||||
[CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
|
||||
[CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
|
||||
[CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
|
||||
[CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
|
||||
[CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
|
||||
[CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
|
||||
[CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
|
||||
[CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
|
||||
[CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
|
||||
[CLKID_CLK81] = &gxbb_clk81.hw,
|
||||
[CLKID_MPLL0] = &gxbb_mpll0.hw,
|
||||
[CLKID_MPLL1] = &gxbb_mpll1.hw,
|
||||
[CLKID_MPLL2] = &gxbb_mpll2.hw,
|
||||
[CLKID_DDR] = &gxbb_ddr.hw,
|
||||
[CLKID_DOS] = &gxbb_dos.hw,
|
||||
[CLKID_ISA] = &gxbb_isa.hw,
|
||||
[CLKID_PL301] = &gxbb_pl301.hw,
|
||||
[CLKID_PERIPHS] = &gxbb_periphs.hw,
|
||||
[CLKID_SPICC] = &gxbb_spicc.hw,
|
||||
[CLKID_I2C] = &gxbb_i2c.hw,
|
||||
[CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
|
||||
[CLKID_SMART_CARD] = &gxbb_smart_card.hw,
|
||||
[CLKID_RNG0] = &gxbb_rng0.hw,
|
||||
[CLKID_UART0] = &gxbb_uart0.hw,
|
||||
[CLKID_SDHC] = &gxbb_sdhc.hw,
|
||||
[CLKID_STREAM] = &gxbb_stream.hw,
|
||||
[CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
|
||||
[CLKID_SDIO] = &gxbb_sdio.hw,
|
||||
[CLKID_ABUF] = &gxbb_abuf.hw,
|
||||
[CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
|
||||
[CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
|
||||
[CLKID_SPI] = &gxbb_spi.hw,
|
||||
[CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
|
||||
[CLKID_ETH] = &gxbb_eth.hw,
|
||||
[CLKID_DEMUX] = &gxbb_demux.hw,
|
||||
[CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
|
||||
[CLKID_IEC958] = &gxbb_iec958.hw,
|
||||
[CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
|
||||
[CLKID_AMCLK] = &gxbb_amclk.hw,
|
||||
[CLKID_AIFIFO2] = &gxbb_aififo2.hw,
|
||||
[CLKID_MIXER] = &gxbb_mixer.hw,
|
||||
[CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
|
||||
[CLKID_ADC] = &gxbb_adc.hw,
|
||||
[CLKID_BLKMV] = &gxbb_blkmv.hw,
|
||||
[CLKID_AIU] = &gxbb_aiu.hw,
|
||||
[CLKID_UART1] = &gxbb_uart1.hw,
|
||||
[CLKID_G2D] = &gxbb_g2d.hw,
|
||||
[CLKID_USB0] = &gxbb_usb0.hw,
|
||||
[CLKID_USB1] = &gxbb_usb1.hw,
|
||||
[CLKID_RESET] = &gxbb_reset.hw,
|
||||
[CLKID_NAND] = &gxbb_nand.hw,
|
||||
[CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
|
||||
[CLKID_USB] = &gxbb_usb.hw,
|
||||
[CLKID_VDIN1] = &gxbb_vdin1.hw,
|
||||
[CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
|
||||
[CLKID_EFUSE] = &gxbb_efuse.hw,
|
||||
[CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
|
||||
[CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
|
||||
[CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
|
||||
[CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
|
||||
[CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
|
||||
[CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
|
||||
[CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
|
||||
[CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
|
||||
[CLKID_DVIN] = &gxbb_dvin.hw,
|
||||
[CLKID_UART2] = &gxbb_uart2.hw,
|
||||
[CLKID_SANA] = &gxbb_sana.hw,
|
||||
[CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
|
||||
[CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
|
||||
[CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
|
||||
[CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
|
||||
[CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
|
||||
[CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
|
||||
[CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
|
||||
[CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
|
||||
[CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
|
||||
[CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
|
||||
[CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
|
||||
[CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
|
||||
[CLKID_ENC480P] = &gxbb_enc480p.hw,
|
||||
[CLKID_RNG1] = &gxbb_rng1.hw,
|
||||
[CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
|
||||
[CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
|
||||
[CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
|
||||
[CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
|
||||
[CLKID_EDP] = &gxbb_edp.hw,
|
||||
[CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
|
||||
[CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
|
||||
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
|
||||
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
|
||||
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
|
||||
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
|
||||
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
|
||||
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
|
||||
[CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
|
||||
[CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
|
||||
[CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
|
||||
[CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
|
||||
[CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
|
||||
[CLKID_MALI_0] = &gxbb_mali_0.hw,
|
||||
[CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
|
||||
[CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
|
||||
[CLKID_MALI_1] = &gxbb_mali_1.hw,
|
||||
[CLKID_MALI] = &gxbb_mali.hw,
|
||||
[CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
|
||||
[CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
|
||||
[CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
|
||||
[CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
|
||||
[CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
|
||||
[CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
|
||||
[CLKID_CTS_I958] = &gxbb_cts_i958.hw,
|
||||
[CLKID_32K_CLK] = &gxbb_32k_clk.hw,
|
||||
[CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
|
||||
[CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
|
||||
[CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
|
||||
[CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
|
||||
[CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
|
||||
[CLKID_VPU_0] = &gxbb_vpu_0.hw,
|
||||
[CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
|
||||
[CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
|
||||
[CLKID_VPU_1] = &gxbb_vpu_1.hw,
|
||||
[CLKID_VPU] = &gxbb_vpu.hw,
|
||||
[CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
|
||||
[CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
|
||||
[CLKID_VAPB_0] = &gxbb_vapb_0.hw,
|
||||
[CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
|
||||
[CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
|
||||
[CLKID_VAPB_1] = &gxbb_vapb_1.hw,
|
||||
[CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
|
||||
[CLKID_VAPB] = &gxbb_vapb.hw,
|
||||
[CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
|
||||
[CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
|
||||
[CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
|
||||
[CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
|
||||
[CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
|
||||
[CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
|
||||
[CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
|
||||
[CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
|
||||
[CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
|
||||
[CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
|
||||
[CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
|
||||
[CLKID_VDEC_1] = &gxbb_vdec_1.hw,
|
||||
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
|
||||
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
|
||||
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
|
||||
[CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
|
||||
[CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
|
||||
[CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
|
||||
[CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
|
||||
[CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
|
||||
[CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
|
||||
[CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
|
||||
[CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
|
||||
[CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
|
||||
[CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
|
||||
[CLKID_VID_PLL] = &gxbb_vid_pll.hw,
|
||||
[CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
|
||||
[CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
|
||||
[CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
|
||||
[CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
|
||||
[CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
|
||||
[CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
|
||||
[CLKID_VCLK] = &gxbb_vclk.hw,
|
||||
[CLKID_VCLK2] = &gxbb_vclk2.hw,
|
||||
[CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
|
||||
[CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
|
||||
[CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
|
||||
[CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
|
||||
[CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
|
||||
[CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
|
||||
[CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
|
||||
[CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
|
||||
[CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
|
||||
[CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
|
||||
[CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
|
||||
[CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
|
||||
[CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
|
||||
[CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
|
||||
[CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
|
||||
[CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
|
||||
[CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
|
||||
[CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
|
||||
[CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
|
||||
[CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
|
||||
[CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
|
||||
[CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
|
||||
[CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
|
||||
[CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
|
||||
[CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
|
||||
[CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
|
||||
[CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
|
||||
[CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
|
||||
[CLKID_HDMI] = &gxbb_hdmi.hw,
|
||||
[CLKID_ACODEC] = &gxl_acodec.hw,
|
||||
};
|
||||
|
||||
static struct clk_regmap *const gxbb_clk_regmaps[] = {
|
||||
|
|
@ -3544,13 +3538,19 @@ static struct clk_regmap *const gxl_clk_regmaps[] = {
|
|||
static const struct meson_eeclkc_data gxbb_clkc_data = {
|
||||
.regmap_clks = gxbb_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
|
||||
.hw_onecell_data = &gxbb_hw_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = gxbb_hw_clks,
|
||||
.num = ARRAY_SIZE(gxbb_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct meson_eeclkc_data gxl_clkc_data = {
|
||||
.regmap_clks = gxl_clk_regmaps,
|
||||
.regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
|
||||
.hw_onecell_data = &gxl_hw_onecell_data,
|
||||
.hw_clks = {
|
||||
.hws = gxl_hw_clks,
|
||||
.num = ARRAY_SIZE(gxl_hw_clks),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct of_device_id clkc_match_table[] = {
|
||||
|
|
|
|||
|
|
@ -112,85 +112,4 @@
|
|||
#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
|
||||
#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
|
||||
#define CLKID_MPEG_SEL 10
|
||||
#define CLKID_MPEG_DIV 11
|
||||
#define CLKID_SAR_ADC_DIV 99
|
||||
#define CLKID_MALI_0_DIV 101
|
||||
#define CLKID_MALI_1_DIV 104
|
||||
#define CLKID_CTS_AMCLK_SEL 108
|
||||
#define CLKID_CTS_AMCLK_DIV 109
|
||||
#define CLKID_CTS_MCLK_I958_SEL 111
|
||||
#define CLKID_CTS_MCLK_I958_DIV 112
|
||||
#define CLKID_32K_CLK_SEL 115
|
||||
#define CLKID_32K_CLK_DIV 116
|
||||
#define CLKID_SD_EMMC_A_CLK0_SEL 117
|
||||
#define CLKID_SD_EMMC_A_CLK0_DIV 118
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 120
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 121
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 123
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 124
|
||||
#define CLKID_VPU_0_DIV 127
|
||||
#define CLKID_VPU_1_DIV 130
|
||||
#define CLKID_VAPB_0_DIV 134
|
||||
#define CLKID_VAPB_1_DIV 137
|
||||
#define CLKID_HDMI_PLL_PRE_MULT 141
|
||||
#define CLKID_MPLL0_DIV 142
|
||||
#define CLKID_MPLL1_DIV 143
|
||||
#define CLKID_MPLL2_DIV 144
|
||||
#define CLKID_MPLL_PREDIV 145
|
||||
#define CLKID_FCLK_DIV2_DIV 146
|
||||
#define CLKID_FCLK_DIV3_DIV 147
|
||||
#define CLKID_FCLK_DIV4_DIV 148
|
||||
#define CLKID_FCLK_DIV5_DIV 149
|
||||
#define CLKID_FCLK_DIV7_DIV 150
|
||||
#define CLKID_VDEC_1_SEL 151
|
||||
#define CLKID_VDEC_1_DIV 152
|
||||
#define CLKID_VDEC_HEVC_SEL 154
|
||||
#define CLKID_VDEC_HEVC_DIV 155
|
||||
#define CLKID_GEN_CLK_SEL 157
|
||||
#define CLKID_GEN_CLK_DIV 158
|
||||
#define CLKID_FIXED_PLL_DCO 160
|
||||
#define CLKID_HDMI_PLL_DCO 161
|
||||
#define CLKID_HDMI_PLL_OD 162
|
||||
#define CLKID_HDMI_PLL_OD2 163
|
||||
#define CLKID_SYS_PLL_DCO 164
|
||||
#define CLKID_GP0_PLL_DCO 165
|
||||
#define CLKID_VID_PLL_SEL 167
|
||||
#define CLKID_VID_PLL_DIV 168
|
||||
#define CLKID_VCLK_SEL 169
|
||||
#define CLKID_VCLK2_SEL 170
|
||||
#define CLKID_VCLK_INPUT 171
|
||||
#define CLKID_VCLK2_INPUT 172
|
||||
#define CLKID_VCLK_DIV 173
|
||||
#define CLKID_VCLK2_DIV 174
|
||||
#define CLKID_VCLK_DIV2_EN 177
|
||||
#define CLKID_VCLK_DIV4_EN 178
|
||||
#define CLKID_VCLK_DIV6_EN 179
|
||||
#define CLKID_VCLK_DIV12_EN 180
|
||||
#define CLKID_VCLK2_DIV2_EN 181
|
||||
#define CLKID_VCLK2_DIV4_EN 182
|
||||
#define CLKID_VCLK2_DIV6_EN 183
|
||||
#define CLKID_VCLK2_DIV12_EN 184
|
||||
#define CLKID_CTS_ENCI_SEL 195
|
||||
#define CLKID_CTS_ENCP_SEL 196
|
||||
#define CLKID_CTS_VDAC_SEL 197
|
||||
#define CLKID_HDMI_TX_SEL 198
|
||||
#define CLKID_HDMI_SEL 203
|
||||
#define CLKID_HDMI_DIV 204
|
||||
|
||||
#define NR_CLKS 207
|
||||
|
||||
/* include the CLKIDs that have been made part of the DT binding */
|
||||
#include <dt-bindings/clock/gxbb-clkc.h>
|
||||
|
||||
#endif /* __GXBB_H */
|
||||
|
|
|
|||
|
|
@ -75,19 +75,18 @@ int meson_aoclkc_probe(struct platform_device *pdev)
|
|||
data->clks[clkid]->map = regmap;
|
||||
|
||||
/* Register all clks */
|
||||
for (clkid = 0; clkid < data->hw_data->num; clkid++) {
|
||||
if (!data->hw_data->hws[clkid])
|
||||
for (clkid = 0; clkid < data->hw_clks.num; clkid++) {
|
||||
if (!data->hw_clks.hws[clkid])
|
||||
continue;
|
||||
|
||||
ret = devm_clk_hw_register(dev, data->hw_data->hws[clkid]);
|
||||
ret = devm_clk_hw_register(dev, data->hw_clks.hws[clkid]);
|
||||
if (ret) {
|
||||
dev_err(dev, "Clock registration failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
(void *) data->hw_data);
|
||||
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/reset-controller.h>
|
||||
|
||||
#include "clk-regmap.h"
|
||||
#include "meson-clkc-utils.h"
|
||||
|
||||
struct meson_aoclk_data {
|
||||
const unsigned int reset_reg;
|
||||
|
|
@ -24,7 +25,7 @@ struct meson_aoclk_data {
|
|||
const unsigned int *reset;
|
||||
const int num_clks;
|
||||
struct clk_regmap **clks;
|
||||
const struct clk_hw_onecell_data *hw_data;
|
||||
struct meson_clk_hw_data hw_clks;
|
||||
};
|
||||
|
||||
struct meson_aoclk_reset_controller {
|
||||
|
|
|
|||
25
drivers/clk/meson/meson-clkc-utils.c
Normal file
25
drivers/clk/meson/meson-clkc-utils.c
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
|
||||
*/
|
||||
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/module.h>
|
||||
#include "meson-clkc-utils.h"
|
||||
|
||||
struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data)
|
||||
{
|
||||
const struct meson_clk_hw_data *data = clk_hw_data;
|
||||
unsigned int idx = clkspec->args[0];
|
||||
|
||||
if (idx >= data->num) {
|
||||
pr_err("%s: invalid index %u\n", __func__, idx);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
return data->hws[idx];
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(meson_clk_hw_get);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
19
drivers/clk/meson/meson-clkc-utils.h
Normal file
19
drivers/clk/meson/meson-clkc-utils.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
|
||||
/*
|
||||
* Copyright (c) 2023 Neil Armstrong <neil.armstrong@linaro.org>
|
||||
*/
|
||||
|
||||
#ifndef __MESON_CLKC_UTILS_H__
|
||||
#define __MESON_CLKC_UTILS_H__
|
||||
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk-provider.h>
|
||||
|
||||
struct meson_clk_hw_data {
|
||||
struct clk_hw **hws;
|
||||
unsigned int num;
|
||||
};
|
||||
|
||||
struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
|
||||
|
||||
#endif
|
||||
|
|
@ -43,20 +43,19 @@ int meson_eeclkc_probe(struct platform_device *pdev)
|
|||
for (i = 0; i < data->regmap_clk_num; i++)
|
||||
data->regmap_clks[i]->map = map;
|
||||
|
||||
for (i = 0; i < data->hw_onecell_data->num; i++) {
|
||||
for (i = 0; i < data->hw_clks.num; i++) {
|
||||
/* array might be sparse */
|
||||
if (!data->hw_onecell_data->hws[i])
|
||||
if (!data->hw_clks.hws[i])
|
||||
continue;
|
||||
|
||||
ret = devm_clk_hw_register(dev, data->hw_onecell_data->hws[i]);
|
||||
ret = devm_clk_hw_register(dev, data->hw_clks.hws[i]);
|
||||
if (ret) {
|
||||
dev_err(dev, "Clock registration failed\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
||||
data->hw_onecell_data);
|
||||
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -9,6 +9,7 @@
|
|||
|
||||
#include <linux/clk-provider.h>
|
||||
#include "clk-regmap.h"
|
||||
#include "meson-clkc-utils.h"
|
||||
|
||||
struct platform_device;
|
||||
|
||||
|
|
@ -17,7 +18,7 @@ struct meson_eeclkc_data {
|
|||
unsigned int regmap_clk_num;
|
||||
const struct reg_sequence *init_regs;
|
||||
unsigned int init_count;
|
||||
struct clk_hw_onecell_data *hw_onecell_data;
|
||||
struct meson_clk_hw_data hw_clks;
|
||||
};
|
||||
|
||||
int meson_eeclkc_probe(struct platform_device *pdev);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -77,121 +77,4 @@
|
|||
#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
|
||||
#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
|
||||
|
||||
/*
|
||||
* CLKID index values
|
||||
*
|
||||
* These indices are entirely contrived and do not map onto the hardware.
|
||||
* It has now been decided to expose everything by default in the DT header:
|
||||
* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
|
||||
* to expose, such as the internal muxes and dividers of composite clocks,
|
||||
* will remain defined here.
|
||||
*/
|
||||
|
||||
#define CLKID_MPLL0_DIV 96
|
||||
#define CLKID_MPLL1_DIV 97
|
||||
#define CLKID_MPLL2_DIV 98
|
||||
#define CLKID_CPU_IN_SEL 99
|
||||
#define CLKID_CPU_IN_DIV2 100
|
||||
#define CLKID_CPU_IN_DIV3 101
|
||||
#define CLKID_CPU_SCALE_DIV 102
|
||||
#define CLKID_CPU_SCALE_OUT_SEL 103
|
||||
#define CLKID_MPLL_PREDIV 104
|
||||
#define CLKID_FCLK_DIV2_DIV 105
|
||||
#define CLKID_FCLK_DIV3_DIV 106
|
||||
#define CLKID_FCLK_DIV4_DIV 107
|
||||
#define CLKID_FCLK_DIV5_DIV 108
|
||||
#define CLKID_FCLK_DIV7_DIV 109
|
||||
#define CLKID_NAND_SEL 110
|
||||
#define CLKID_NAND_DIV 111
|
||||
#define CLKID_PLL_FIXED_DCO 113
|
||||
#define CLKID_HDMI_PLL_DCO 114
|
||||
#define CLKID_PLL_SYS_DCO 115
|
||||
#define CLKID_CPU_CLK_DIV2 116
|
||||
#define CLKID_CPU_CLK_DIV3 117
|
||||
#define CLKID_CPU_CLK_DIV4 118
|
||||
#define CLKID_CPU_CLK_DIV5 119
|
||||
#define CLKID_CPU_CLK_DIV6 120
|
||||
#define CLKID_CPU_CLK_DIV7 121
|
||||
#define CLKID_CPU_CLK_DIV8 122
|
||||
#define CLKID_APB_SEL 123
|
||||
#define CLKID_PERIPH_SEL 125
|
||||
#define CLKID_AXI_SEL 127
|
||||
#define CLKID_L2_DRAM_SEL 129
|
||||
#define CLKID_HDMI_PLL_LVDS_OUT 131
|
||||
#define CLKID_VID_PLL_IN_SEL 133
|
||||
#define CLKID_VID_PLL_IN_EN 134
|
||||
#define CLKID_VID_PLL_PRE_DIV 135
|
||||
#define CLKID_VID_PLL_POST_DIV 136
|
||||
#define CLKID_VCLK_IN_EN 139
|
||||
#define CLKID_VCLK_DIV1 140
|
||||
#define CLKID_VCLK_DIV2_DIV 141
|
||||
#define CLKID_VCLK_DIV2 142
|
||||
#define CLKID_VCLK_DIV4_DIV 143
|
||||
#define CLKID_VCLK_DIV4 144
|
||||
#define CLKID_VCLK_DIV6_DIV 145
|
||||
#define CLKID_VCLK_DIV6 146
|
||||
#define CLKID_VCLK_DIV12_DIV 147
|
||||
#define CLKID_VCLK_DIV12 148
|
||||
#define CLKID_VCLK2_IN_EN 150
|
||||
#define CLKID_VCLK2_DIV1 151
|
||||
#define CLKID_VCLK2_DIV2_DIV 152
|
||||
#define CLKID_VCLK2_DIV2 153
|
||||
#define CLKID_VCLK2_DIV4_DIV 154
|
||||
#define CLKID_VCLK2_DIV4 155
|
||||
#define CLKID_VCLK2_DIV6_DIV 156
|
||||
#define CLKID_VCLK2_DIV6 157
|
||||
#define CLKID_VCLK2_DIV12_DIV 158
|
||||
#define CLKID_VCLK2_DIV12 159
|
||||
#define CLKID_CTS_ENCT_SEL 160
|
||||
#define CLKID_CTS_ENCP_SEL 162
|
||||
#define CLKID_CTS_ENCI_SEL 164
|
||||
#define CLKID_HDMI_TX_PIXEL_SEL 166
|
||||
#define CLKID_CTS_ENCL_SEL 168
|
||||
#define CLKID_CTS_VDAC0_SEL 170
|
||||
#define CLKID_HDMI_SYS_SEL 172
|
||||
#define CLKID_HDMI_SYS_DIV 173
|
||||
#define CLKID_MALI_0_SEL 175
|
||||
#define CLKID_MALI_0_DIV 176
|
||||
#define CLKID_MALI_0 177
|
||||
#define CLKID_MALI_1_SEL 178
|
||||
#define CLKID_MALI_1_DIV 179
|
||||
#define CLKID_MALI_1 180
|
||||
#define CLKID_GP_PLL_DCO 181
|
||||
#define CLKID_GP_PLL 182
|
||||
#define CLKID_VPU_0_SEL 183
|
||||
#define CLKID_VPU_0_DIV 184
|
||||
#define CLKID_VPU_0 185
|
||||
#define CLKID_VPU_1_SEL 186
|
||||
#define CLKID_VPU_1_DIV 187
|
||||
#define CLKID_VPU_1 189
|
||||
#define CLKID_VDEC_1_SEL 191
|
||||
#define CLKID_VDEC_1_1_DIV 192
|
||||
#define CLKID_VDEC_1_1 193
|
||||
#define CLKID_VDEC_1_2_DIV 194
|
||||
#define CLKID_VDEC_1_2 195
|
||||
#define CLKID_VDEC_HCODEC_SEL 197
|
||||
#define CLKID_VDEC_HCODEC_DIV 198
|
||||
#define CLKID_VDEC_2_SEL 200
|
||||
#define CLKID_VDEC_2_DIV 201
|
||||
#define CLKID_VDEC_HEVC_SEL 203
|
||||
#define CLKID_VDEC_HEVC_DIV 204
|
||||
#define CLKID_VDEC_HEVC_EN 205
|
||||
#define CLKID_CTS_AMCLK_SEL 207
|
||||
#define CLKID_CTS_AMCLK_DIV 208
|
||||
#define CLKID_CTS_MCLK_I958_SEL 210
|
||||
#define CLKID_CTS_MCLK_I958_DIV 211
|
||||
#define CLKID_VCLK_EN 214
|
||||
#define CLKID_VCLK2_EN 215
|
||||
#define CLKID_VID_PLL_LVDS_EN 216
|
||||
#define CLKID_HDMI_PLL_DCO_IN 217
|
||||
|
||||
#define CLK_NR_CLKS 218
|
||||
|
||||
/*
|
||||
* include the CLKID and RESETID that have
|
||||
* been made part of the stable DT binding
|
||||
*/
|
||||
#include <dt-bindings/clock/meson8b-clkc.h>
|
||||
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
|
||||
|
||||
#endif /* __MESON8B_H */
|
||||
|
|
|
|||
|
|
@ -79,9 +79,10 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
|
|||
RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
|
||||
RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
|
||||
RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
|
||||
RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
|
||||
RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
|
||||
RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
|
||||
RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),
|
||||
RK3036_PLL_RATE(78750000, 4, 315, 6, 4, 1, 0),
|
||||
RK3036_PLL_RATE(74250000, 2, 99, 4, 4, 1, 0),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
|
|
|||
|
|
@ -175,6 +175,7 @@ PNAME(mux_i2s2_p) = { "mclk_i2s2_div", "mclk_i2s2_fracdiv", "i2s2_mclkin", "xi
|
|||
PNAME(mux_i2s2_out2io_p) = { "mclk_i2s2", "xin12m" };
|
||||
PNAME(mux_gpll_cpll_xin24m_p) = { "gpll", "cpll", "xin24m" };
|
||||
PNAME(mux_audpwm_p) = { "sclk_audpwm_div", "sclk_audpwm_fracdiv", "xin24m" };
|
||||
PNAME(mux_dclk_vop_p) = { "dclk_vop_div", "dclk_vop_fracdiv", "xin24m" };
|
||||
PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
|
||||
PNAME(clk_gmac_src_m0_p) = { "clk_gmac_div", "clk_gmac_rgmii_m0" };
|
||||
PNAME(clk_gmac_src_m1_p) = { "clk_gmac_div", "clk_gmac_rgmii_m1" };
|
||||
|
|
@ -259,6 +260,10 @@ static struct rockchip_clk_branch rv1126_audpwm_fracmux __initdata =
|
|||
MUX(SCLK_AUDPWM_MUX, "mclk_audpwm_mux", mux_audpwm_p, CLK_SET_RATE_PARENT,
|
||||
RV1126_CLKSEL_CON(36), 8, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rv1126_dclk_vop_fracmux __initdata =
|
||||
MUX(DCLK_VOP_MUX, "dclk_vop_mux", mux_dclk_vop_p, CLK_SET_RATE_PARENT,
|
||||
RV1126_CLKSEL_CON(47), 10, 2, MFLAGS);
|
||||
|
||||
static struct rockchip_clk_branch rv1126_clk_pmu_branches[] __initdata = {
|
||||
/*
|
||||
* Clock-Architecture Diagram 2
|
||||
|
|
@ -714,6 +719,49 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
|
|||
RV1126_CLKSEL_CON(72), 8, 1, MFLAGS, 0, 7, DFLAGS,
|
||||
RV1126_CLKGATE_CON(11), 1, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 9
|
||||
*/
|
||||
/* PD_VO */
|
||||
COMPOSITE(ACLK_PDVO, "aclk_pdvo", mux_gpll_cpll_p, 0,
|
||||
RV1126_CLKSEL_CON(45), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1126_CLKGATE_CON(14), 0, GFLAGS),
|
||||
COMPOSITE_NOMUX(HCLK_PDVO, "hclk_pdvo", "aclk_pdvo", 0,
|
||||
RV1126_CLKSEL_CON(45), 8, 5, DFLAGS,
|
||||
RV1126_CLKGATE_CON(14), 1, GFLAGS),
|
||||
COMPOSITE_NOMUX(PCLK_PDVO, "pclk_pdvo", "aclk_pdvo", 0,
|
||||
RV1126_CLKSEL_CON(46), 8, 5, DFLAGS,
|
||||
RV1126_CLKGATE_CON(14), 2, GFLAGS),
|
||||
GATE(ACLK_RGA, "aclk_rga", "aclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(14), 6, GFLAGS),
|
||||
GATE(HCLK_RGA, "hclk_rga", "hclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(14), 7, GFLAGS),
|
||||
COMPOSITE(CLK_RGA_CORE, "clk_rga_core", mux_gpll_cpll_p, 0,
|
||||
RV1126_CLKSEL_CON(46), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1126_CLKGATE_CON(14), 8, GFLAGS),
|
||||
GATE(ACLK_VOP, "aclk_vop", "aclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(14), 9, GFLAGS),
|
||||
GATE(HCLK_VOP, "hclk_vop", "hclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(14), 10, GFLAGS),
|
||||
COMPOSITE(DCLK_VOP_DIV, "dclk_vop_div", mux_gpll_cpll_p, 0,
|
||||
RV1126_CLKSEL_CON(47), 8, 1, MFLAGS, 0, 8, DFLAGS,
|
||||
RV1126_CLKGATE_CON(14), 11, GFLAGS),
|
||||
COMPOSITE_FRACMUX(DCLK_VOP_FRACDIV, "dclk_vop_fracdiv", "dclk_vop_div",
|
||||
CLK_SET_RATE_PARENT, RV1126_CLKSEL_CON(48), 0,
|
||||
RV1126_CLKGATE_CON(14), 12, GFLAGS,
|
||||
&rv1126_dclk_vop_fracmux),
|
||||
GATE(DCLK_VOP, "dclk_vop", "dclk_vop_mux", 0,
|
||||
RV1126_CLKGATE_CON(14), 13, GFLAGS),
|
||||
GATE(PCLK_DSIHOST, "pclk_dsihost", "pclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(14), 14, GFLAGS),
|
||||
GATE(ACLK_IEP, "aclk_iep", "aclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(12), 7, GFLAGS),
|
||||
GATE(HCLK_IEP, "hclk_iep", "hclk_pdvo", 0,
|
||||
RV1126_CLKGATE_CON(12), 8, GFLAGS),
|
||||
COMPOSITE(CLK_IEP_CORE, "clk_iep_core", mux_gpll_cpll_p, 0,
|
||||
RV1126_CLKSEL_CON(54), 7, 1, MFLAGS, 0, 5, DFLAGS,
|
||||
RV1126_CLKGATE_CON(12), 9, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 12
|
||||
*/
|
||||
|
|
@ -905,6 +953,17 @@ static struct rockchip_clk_branch rv1126_clk_branches[] __initdata = {
|
|||
GATE(0, "pclk_pdaudio_niu", "hclk_pdaudio", CLK_IGNORE_UNUSED,
|
||||
RV1126_CLKGATE_CON(9), 3, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 9
|
||||
*/
|
||||
/* PD_VO */
|
||||
GATE(0, "aclk_pdvo_niu", "aclk_pdvo", CLK_IGNORE_UNUSED,
|
||||
RV1126_CLKGATE_CON(14), 3, GFLAGS),
|
||||
GATE(0, "hclk_pdvo_niu", "hclk_pdvo", CLK_IGNORE_UNUSED,
|
||||
RV1126_CLKGATE_CON(14), 4, GFLAGS),
|
||||
GATE(0, "pclk_pdvo_niu", "pclk_pdvo", CLK_IGNORE_UNUSED,
|
||||
RV1126_CLKGATE_CON(14), 5, GFLAGS),
|
||||
|
||||
/*
|
||||
* Clock-Architecture Diagram 12
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
|
|||
BIT(28), /* lock */
|
||||
CLK_SET_RATE_UNGATE);
|
||||
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
|
||||
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(pll_video0_clk, "pll-video0",
|
||||
"osc24M", 0x010,
|
||||
192000000, /* Minimum rate */
|
||||
1008000000, /* Maximum rate */
|
||||
|
|
@ -179,7 +179,9 @@ static struct ccu_nkm pll_mipi_clk = {
|
|||
.common = {
|
||||
.reg = 0x040,
|
||||
.hw.init = CLK_HW_INIT("pll-mipi", "pll-video0",
|
||||
&ccu_nkm_ops, CLK_SET_RATE_UNGATE),
|
||||
&ccu_nkm_ops,
|
||||
CLK_SET_RATE_UNGATE | CLK_SET_RATE_PARENT),
|
||||
.features = CCU_FEATURE_CLOSEST_RATE,
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -536,25 +538,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
|
|||
|
||||
static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
|
||||
static const u8 tcon0_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
|
||||
tcon0_table, 0x118, 24, 3, BIT(31),
|
||||
CLK_SET_RATE_PARENT |
|
||||
CLK_SET_RATE_NO_REPARENT);
|
||||
static SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(tcon0_clk, "tcon0", tcon0_parents,
|
||||
tcon0_table, 0x118, 24, 3, BIT(31),
|
||||
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT);
|
||||
|
||||
static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
|
||||
static const u8 tcon1_table[] = { 0, 2, };
|
||||
static struct ccu_div tcon1_clk = {
|
||||
.enable = BIT(31),
|
||||
.div = _SUNXI_CCU_DIV(0, 4),
|
||||
.mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table),
|
||||
.common = {
|
||||
.reg = 0x11c,
|
||||
.hw.init = CLK_HW_INIT_PARENTS("tcon1",
|
||||
tcon1_parents,
|
||||
&ccu_div_ops,
|
||||
CLK_SET_RATE_PARENT),
|
||||
},
|
||||
};
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(tcon1_clk, "tcon1", tcon1_parents,
|
||||
tcon1_table, 0x11c,
|
||||
0, 4, /* M */
|
||||
24, 2, /* mux */
|
||||
BIT(31), /* gate */
|
||||
CLK_SET_RATE_PARENT);
|
||||
|
||||
static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
|
||||
static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
|
||||
|
|
@ -584,8 +579,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
|
|||
0x144, BIT(31), 0);
|
||||
|
||||
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
|
||||
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
|
||||
0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(hdmi_clk, "hdmi", hdmi_parents,
|
||||
0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
|
||||
0x154, BIT(31), 0);
|
||||
|
|
@ -597,9 +592,9 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
|
|||
|
||||
static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
|
||||
static const u8 dsi_dphy_table[] = { 0, 2, };
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
|
||||
dsi_dphy_parents, dsi_dphy_table,
|
||||
0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
|
||||
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(dsi_dphy_clk, "dsi-dphy",
|
||||
dsi_dphy_parents, dsi_dphy_table,
|
||||
0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
|
||||
|
||||
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
|
||||
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
|
||||
|
|
|
|||
|
|
@ -39,6 +39,18 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
|
|||
}
|
||||
EXPORT_SYMBOL_NS_GPL(ccu_helper_wait_for_lock, SUNXI_CCU);
|
||||
|
||||
bool ccu_is_better_rate(struct ccu_common *common,
|
||||
unsigned long target_rate,
|
||||
unsigned long current_rate,
|
||||
unsigned long best_rate)
|
||||
{
|
||||
if (common->features & CCU_FEATURE_CLOSEST_RATE)
|
||||
return abs(current_rate - target_rate) < abs(best_rate - target_rate);
|
||||
|
||||
return current_rate <= target_rate && current_rate > best_rate;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(ccu_is_better_rate, SUNXI_CCU);
|
||||
|
||||
/*
|
||||
* This clock notifier is called when the frequency of a PLL clock is
|
||||
* changed. In common PLL designs, changes to the dividers take effect
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
|
||||
#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
|
||||
#define CCU_FEATURE_KEY_FIELD BIT(8)
|
||||
#define CCU_FEATURE_CLOSEST_RATE BIT(9)
|
||||
|
||||
/* MMC timing mode switch bit */
|
||||
#define CCU_MMC_NEW_TIMING_MODE BIT(30)
|
||||
|
|
@ -52,6 +53,11 @@ struct sunxi_ccu_desc {
|
|||
|
||||
void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
|
||||
|
||||
bool ccu_is_better_rate(struct ccu_common *common,
|
||||
unsigned long target_rate,
|
||||
unsigned long current_rate,
|
||||
unsigned long best_rate);
|
||||
|
||||
struct ccu_pll_nb {
|
||||
struct notifier_block clk_nb;
|
||||
struct ccu_common *common;
|
||||
|
|
|
|||
|
|
@ -143,6 +143,26 @@ struct ccu_div {
|
|||
}, \
|
||||
}
|
||||
|
||||
#define SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \
|
||||
_parents, _table, \
|
||||
_reg, \
|
||||
_mshift, _mwidth, \
|
||||
_muxshift, _muxwidth, \
|
||||
_gate, _flags) \
|
||||
struct ccu_div _struct = { \
|
||||
.enable = _gate, \
|
||||
.div = _SUNXI_CCU_DIV_FLAGS(_mshift, _mwidth, CLK_DIVIDER_ROUND_CLOSEST), \
|
||||
.mux = _SUNXI_CCU_MUX_TABLE(_muxshift, _muxwidth, _table), \
|
||||
.common = { \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parents, \
|
||||
&ccu_div_ops, \
|
||||
_flags), \
|
||||
.features = CCU_FEATURE_CLOSEST_RATE, \
|
||||
}, \
|
||||
}
|
||||
|
||||
#define SUNXI_CCU_M_WITH_MUX_GATE(_struct, _name, _parents, _reg, \
|
||||
_mshift, _mwidth, _muxshift, _muxwidth, \
|
||||
_gate, _flags) \
|
||||
|
|
@ -152,6 +172,16 @@ struct ccu_div {
|
|||
_muxshift, _muxwidth, \
|
||||
_gate, _flags)
|
||||
|
||||
#define SUNXI_CCU_M_WITH_MUX_GATE_CLOSEST(_struct, _name, _parents, \
|
||||
_reg, _mshift, _mwidth, \
|
||||
_muxshift, _muxwidth, \
|
||||
_gate, _flags) \
|
||||
SUNXI_CCU_M_WITH_MUX_TABLE_GATE_CLOSEST(_struct, _name, \
|
||||
_parents, NULL, \
|
||||
_reg, _mshift, _mwidth, \
|
||||
_muxshift, _muxwidth, \
|
||||
_gate, _flags)
|
||||
|
||||
#define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \
|
||||
_mshift, _mwidth, _muxshift, _muxwidth, \
|
||||
_flags) \
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode)
|
|||
EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode);
|
||||
|
||||
/**
|
||||
* sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode
|
||||
* sunxi_ccu_get_mmc_timing_mode: Get the current MMC clock timing mode
|
||||
* @clk: clock to query
|
||||
*
|
||||
* Return: %0 if the clock is in old timing mode, > %0 if it is in
|
||||
|
|
|
|||
|
|
@ -139,7 +139,7 @@ int ccu_mux_helper_determine_rate(struct ccu_common *common,
|
|||
goto out;
|
||||
}
|
||||
|
||||
if ((req->rate - tmp_rate) < (req->rate - best_rate)) {
|
||||
if (ccu_is_better_rate(common, req->rate, tmp_rate, best_rate)) {
|
||||
best_rate = tmp_rate;
|
||||
best_parent_rate = parent_rate;
|
||||
best_parent = parent;
|
||||
|
|
@ -242,6 +242,17 @@ static int ccu_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
return ccu_mux_helper_set_parent(&cm->common, &cm->mux, index);
|
||||
}
|
||||
|
||||
static int ccu_mux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct ccu_mux *cm = hw_to_ccu_mux(hw);
|
||||
|
||||
if (cm->common.features & CCU_FEATURE_CLOSEST_RATE)
|
||||
return clk_mux_determine_rate_flags(hw, req, CLK_MUX_ROUND_CLOSEST);
|
||||
|
||||
return clk_mux_determine_rate_flags(hw, req, 0);
|
||||
}
|
||||
|
||||
static unsigned long ccu_mux_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
@ -259,7 +270,7 @@ const struct clk_ops ccu_mux_ops = {
|
|||
.get_parent = ccu_mux_get_parent,
|
||||
.set_parent = ccu_mux_set_parent,
|
||||
|
||||
.determine_rate = __clk_mux_determine_rate,
|
||||
.determine_rate = ccu_mux_determine_rate,
|
||||
.recalc_rate = ccu_mux_recalc_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_NS_GPL(ccu_mux_ops, SUNXI_CCU);
|
||||
|
|
|
|||
|
|
@ -46,20 +46,36 @@ struct ccu_mux {
|
|||
struct ccu_common common;
|
||||
};
|
||||
|
||||
#define SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _gate, \
|
||||
_flags, _features) \
|
||||
struct ccu_mux _struct = { \
|
||||
.enable = _gate, \
|
||||
.mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
|
||||
.common = { \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parents, \
|
||||
&ccu_mux_ops, \
|
||||
_flags), \
|
||||
.features = _features, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SUNXI_CCU_MUX_TABLE_WITH_GATE_CLOSEST(_struct, _name, _parents, \
|
||||
_table, _reg, _shift, \
|
||||
_width, _gate, _flags) \
|
||||
SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
|
||||
_table, _reg, _shift, \
|
||||
_width, _gate, _flags, \
|
||||
CCU_FEATURE_CLOSEST_RATE)
|
||||
|
||||
#define SUNXI_CCU_MUX_TABLE_WITH_GATE(_struct, _name, _parents, _table, \
|
||||
_reg, _shift, _width, _gate, \
|
||||
_flags) \
|
||||
struct ccu_mux _struct = { \
|
||||
.enable = _gate, \
|
||||
.mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
|
||||
.common = { \
|
||||
.reg = _reg, \
|
||||
.hw.init = CLK_HW_INIT_PARENTS(_name, \
|
||||
_parents, \
|
||||
&ccu_mux_ops, \
|
||||
_flags), \
|
||||
} \
|
||||
}
|
||||
SUNXI_CCU_MUX_TABLE_WITH_GATE_FEAT(_struct, _name, _parents, \
|
||||
_table, _reg, _shift, \
|
||||
_width, _gate, _flags, 0)
|
||||
|
||||
#define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \
|
||||
_shift, _width, _gate, _flags) \
|
||||
|
|
|
|||
|
|
@ -16,8 +16,47 @@ struct _ccu_nkm {
|
|||
unsigned long m, min_m, max_m;
|
||||
};
|
||||
|
||||
static unsigned long ccu_nkm_find_best_with_parent_adj(struct ccu_common *common,
|
||||
struct clk_hw *parent_hw,
|
||||
unsigned long *parent, unsigned long rate,
|
||||
struct _ccu_nkm *nkm)
|
||||
{
|
||||
unsigned long best_rate = 0, best_parent_rate = *parent, tmp_parent = *parent;
|
||||
unsigned long best_n = 0, best_k = 0, best_m = 0;
|
||||
unsigned long _n, _k, _m;
|
||||
|
||||
for (_k = nkm->min_k; _k <= nkm->max_k; _k++) {
|
||||
for (_n = nkm->min_n; _n <= nkm->max_n; _n++) {
|
||||
for (_m = nkm->min_m; _m <= nkm->max_m; _m++) {
|
||||
unsigned long tmp_rate;
|
||||
|
||||
tmp_parent = clk_hw_round_rate(parent_hw, rate * _m / (_n * _k));
|
||||
|
||||
tmp_rate = tmp_parent * _n * _k / _m;
|
||||
|
||||
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate) ||
|
||||
(tmp_parent == *parent && tmp_rate == best_rate)) {
|
||||
best_rate = tmp_rate;
|
||||
best_parent_rate = tmp_parent;
|
||||
best_n = _n;
|
||||
best_k = _k;
|
||||
best_m = _m;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
nkm->n = best_n;
|
||||
nkm->k = best_k;
|
||||
nkm->m = best_m;
|
||||
|
||||
*parent = best_parent_rate;
|
||||
|
||||
return best_rate;
|
||||
}
|
||||
|
||||
static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
|
||||
struct _ccu_nkm *nkm)
|
||||
struct _ccu_nkm *nkm, struct ccu_common *common)
|
||||
{
|
||||
unsigned long best_rate = 0;
|
||||
unsigned long best_n = 0, best_k = 0, best_m = 0;
|
||||
|
|
@ -30,9 +69,7 @@ static unsigned long ccu_nkm_find_best(unsigned long parent, unsigned long rate,
|
|||
|
||||
tmp_rate = parent * _n * _k / _m;
|
||||
|
||||
if (tmp_rate > rate)
|
||||
continue;
|
||||
if ((rate - tmp_rate) < (rate - best_rate)) {
|
||||
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) {
|
||||
best_rate = tmp_rate;
|
||||
best_n = _n;
|
||||
best_k = _k;
|
||||
|
|
@ -106,7 +143,7 @@ static unsigned long ccu_nkm_recalc_rate(struct clk_hw *hw,
|
|||
}
|
||||
|
||||
static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
|
||||
struct clk_hw *hw,
|
||||
struct clk_hw *parent_hw,
|
||||
unsigned long *parent_rate,
|
||||
unsigned long rate,
|
||||
void *data)
|
||||
|
|
@ -124,7 +161,11 @@ static unsigned long ccu_nkm_round_rate(struct ccu_mux_internal *mux,
|
|||
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
||||
rate *= nkm->fixed_post_div;
|
||||
|
||||
rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm);
|
||||
if (!clk_hw_can_set_rate_parent(&nkm->common.hw))
|
||||
rate = ccu_nkm_find_best(*parent_rate, rate, &_nkm, &nkm->common);
|
||||
else
|
||||
rate = ccu_nkm_find_best_with_parent_adj(&nkm->common, parent_hw, parent_rate, rate,
|
||||
&_nkm);
|
||||
|
||||
if (nkm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
||||
rate /= nkm->fixed_post_div;
|
||||
|
|
@ -159,7 +200,7 @@ static int ccu_nkm_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
_nkm.min_m = 1;
|
||||
_nkm.max_m = nkm->m.max ?: 1 << nkm->m.width;
|
||||
|
||||
ccu_nkm_find_best(parent_rate, rate, &_nkm);
|
||||
ccu_nkm_find_best(parent_rate, rate, &_nkm, &nkm->common);
|
||||
|
||||
spin_lock_irqsave(nkm->common.lock, flags);
|
||||
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ static unsigned long ccu_nm_calc_rate(unsigned long parent,
|
|||
return rate;
|
||||
}
|
||||
|
||||
static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate,
|
||||
struct _ccu_nm *nm)
|
||||
static unsigned long ccu_nm_find_best(struct ccu_common *common, unsigned long parent,
|
||||
unsigned long rate, struct _ccu_nm *nm)
|
||||
{
|
||||
unsigned long best_rate = 0;
|
||||
unsigned long best_n = 0, best_m = 0;
|
||||
|
|
@ -39,10 +39,7 @@ static unsigned long ccu_nm_find_best(unsigned long parent, unsigned long rate,
|
|||
unsigned long tmp_rate = ccu_nm_calc_rate(parent,
|
||||
_n, _m);
|
||||
|
||||
if (tmp_rate > rate)
|
||||
continue;
|
||||
|
||||
if ((rate - tmp_rate) < (rate - best_rate)) {
|
||||
if (ccu_is_better_rate(common, rate, tmp_rate, best_rate)) {
|
||||
best_rate = tmp_rate;
|
||||
best_n = _n;
|
||||
best_m = _m;
|
||||
|
|
@ -159,7 +156,7 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
_nm.min_m = 1;
|
||||
_nm.max_m = nm->m.max ?: 1 << nm->m.width;
|
||||
|
||||
rate = ccu_nm_find_best(*parent_rate, rate, &_nm);
|
||||
rate = ccu_nm_find_best(&nm->common, *parent_rate, rate, &_nm);
|
||||
|
||||
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
|
||||
rate /= nm->fixed_post_div;
|
||||
|
|
@ -210,7 +207,7 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
&_nm.m, &_nm.n);
|
||||
} else {
|
||||
ccu_sdm_helper_disable(&nm->common, &nm->sdm);
|
||||
ccu_nm_find_best(parent_rate, rate, &_nm);
|
||||
ccu_nm_find_best(&nm->common, parent_rate, rate, &_nm);
|
||||
}
|
||||
|
||||
spin_lock_irqsave(nm->common.lock, flags);
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ struct ccu_nm {
|
|||
}, \
|
||||
}
|
||||
|
||||
#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
|
||||
#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \
|
||||
_parent, _reg, \
|
||||
_min_rate, _max_rate, \
|
||||
_nshift, _nwidth, \
|
||||
|
|
@ -116,7 +116,8 @@ struct ccu_nm {
|
|||
_frac_en, _frac_sel, \
|
||||
_frac_rate_0, \
|
||||
_frac_rate_1, \
|
||||
_gate, _lock, _flags) \
|
||||
_gate, _lock, _flags, \
|
||||
_features) \
|
||||
struct ccu_nm _struct = { \
|
||||
.enable = _gate, \
|
||||
.lock = _lock, \
|
||||
|
|
@ -129,7 +130,7 @@ struct ccu_nm {
|
|||
.max_rate = _max_rate, \
|
||||
.common = { \
|
||||
.reg = _reg, \
|
||||
.features = CCU_FEATURE_FRACTIONAL, \
|
||||
.features = _features, \
|
||||
.hw.init = CLK_HW_INIT(_name, \
|
||||
_parent, \
|
||||
&ccu_nm_ops, \
|
||||
|
|
@ -137,6 +138,47 @@ struct ccu_nm {
|
|||
}, \
|
||||
}
|
||||
|
||||
#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(_struct, _name, \
|
||||
_parent, _reg, \
|
||||
_min_rate, _max_rate, \
|
||||
_nshift, _nwidth, \
|
||||
_mshift, _mwidth, \
|
||||
_frac_en, _frac_sel, \
|
||||
_frac_rate_0, \
|
||||
_frac_rate_1, \
|
||||
_gate, _lock, _flags) \
|
||||
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \
|
||||
_parent, _reg, \
|
||||
_min_rate, _max_rate, \
|
||||
_nshift, _nwidth, \
|
||||
_mshift, _mwidth, \
|
||||
_frac_en, _frac_sel, \
|
||||
_frac_rate_0, \
|
||||
_frac_rate_1, \
|
||||
_gate, _lock, _flags, \
|
||||
CCU_FEATURE_FRACTIONAL)
|
||||
|
||||
#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_CLOSEST(_struct, _name, \
|
||||
_parent, _reg, \
|
||||
_min_rate, _max_rate, \
|
||||
_nshift, _nwidth, \
|
||||
_mshift, _mwidth, \
|
||||
_frac_en, _frac_sel, \
|
||||
_frac_rate_0, \
|
||||
_frac_rate_1, \
|
||||
_gate, _lock, _flags) \
|
||||
SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX_FEAT(_struct, _name, \
|
||||
_parent, _reg, \
|
||||
_min_rate, _max_rate, \
|
||||
_nshift, _nwidth, \
|
||||
_mshift, _mwidth, \
|
||||
_frac_en, _frac_sel, \
|
||||
_frac_rate_0, \
|
||||
_frac_rate_1, \
|
||||
_gate, _lock, _flags, \
|
||||
CCU_FEATURE_FRACTIONAL |\
|
||||
CCU_FEATURE_CLOSEST_RATE)
|
||||
|
||||
#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
|
||||
_nshift, _nwidth, \
|
||||
_mshift, _mwidth, \
|
||||
|
|
|
|||
|
|
@ -107,15 +107,13 @@ static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
|
|||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!r)
|
||||
return -EINVAL;
|
||||
/* one clock/reset pair per word */
|
||||
count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
|
||||
data->membase = devm_ioremap_resource(&pdev->dev, r);
|
||||
data->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
|
||||
if (IS_ERR(data->membase))
|
||||
return PTR_ERR(data->membase);
|
||||
|
||||
/* one clock/reset pair per word */
|
||||
count = DIV_ROUND_UP((resource_size(r)), SUN9I_MMC_WIDTH);
|
||||
|
||||
clk_data = &data->clk_data;
|
||||
clk_data->clk_num = count;
|
||||
clk_data->clks = devm_kcalloc(&pdev->dev, count, sizeof(struct clk *),
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/string_helpers.h>
|
||||
|
||||
#include <soc/tegra/fuse.h>
|
||||
|
||||
|
|
@ -384,12 +384,10 @@ static struct device_node *tegra_clk_get_of_node(struct clk_hw *hw)
|
|||
struct device_node *np;
|
||||
char *node_name;
|
||||
|
||||
node_name = kstrdup(hw->init->name, GFP_KERNEL);
|
||||
node_name = kstrdup_and_replace(hw->init->name, '_', '-', GFP_KERNEL);
|
||||
if (!node_name)
|
||||
return NULL;
|
||||
|
||||
strreplace(node_name, '_', '-');
|
||||
|
||||
for_each_child_of_node(tegra_car_np, np) {
|
||||
if (!strcmp(np->name, node_name))
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/string_helpers.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
|
|
@ -123,10 +124,9 @@ static struct device_node *ti_find_clock_provider(struct device_node *from,
|
|||
const char *n;
|
||||
char *tmp;
|
||||
|
||||
tmp = kstrdup(name, GFP_KERNEL);
|
||||
tmp = kstrdup_and_replace(name, '-', '_', GFP_KERNEL);
|
||||
if (!tmp)
|
||||
return NULL;
|
||||
strreplace(tmp, '-', '_');
|
||||
|
||||
/* Node named "clock" with "clock-output-names" */
|
||||
for_each_of_allnodes_from(from, np) {
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/clk/ti.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/string_helpers.h>
|
||||
#include <linux/timekeeping.h>
|
||||
#include "clock.h"
|
||||
|
||||
|
|
@ -473,11 +474,11 @@ static const char * __init clkctrl_get_name(struct device_node *np)
|
|||
const int prefix_len = 11;
|
||||
const char *compat;
|
||||
const char *output;
|
||||
const char *end;
|
||||
char *name;
|
||||
|
||||
if (!of_property_read_string_index(np, "clock-output-names", 0,
|
||||
&output)) {
|
||||
const char *end;
|
||||
int len;
|
||||
|
||||
len = strlen(output);
|
||||
|
|
@ -491,13 +492,13 @@ static const char * __init clkctrl_get_name(struct device_node *np)
|
|||
|
||||
of_property_for_each_string(np, "compatible", prop, compat) {
|
||||
if (!strncmp("ti,clkctrl-", compat, prefix_len)) {
|
||||
end = compat + prefix_len;
|
||||
/* Two letter minimum name length for l3, l4 etc */
|
||||
if (strnlen(compat + prefix_len, 16) < 2)
|
||||
if (strnlen(end, 16) < 2)
|
||||
continue;
|
||||
name = kasprintf(GFP_KERNEL, "%s", compat + prefix_len);
|
||||
name = kstrdup_and_replace(end, '-', '_', GFP_KERNEL);
|
||||
if (!name)
|
||||
continue;
|
||||
strreplace(name, '-', '_');
|
||||
|
||||
return name;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@
|
|||
#ifndef __A1_PERIPHERALS_CLKC_H
|
||||
#define __A1_PERIPHERALS_CLKC_H
|
||||
|
||||
#define CLKID_XTAL_IN 0
|
||||
#define CLKID_FIXPLL_IN 1
|
||||
#define CLKID_USB_PHY_IN 2
|
||||
#define CLKID_USB_CTRL_IN 3
|
||||
|
|
@ -70,6 +71,8 @@
|
|||
#define CLKID_CPU_CTRL 58
|
||||
#define CLKID_ROM 59
|
||||
#define CLKID_PROC_I2C 60
|
||||
#define CLKID_DSPA_SEL 61
|
||||
#define CLKID_DSPB_SEL 62
|
||||
#define CLKID_DSPA_EN 63
|
||||
#define CLKID_DSPA_EN_NIC 64
|
||||
#define CLKID_DSPB_EN 65
|
||||
|
|
@ -81,6 +84,7 @@
|
|||
#define CLKID_12M 71
|
||||
#define CLKID_FCLK_DIV2_DIVN 72
|
||||
#define CLKID_GEN 73
|
||||
#define CLKID_SARADC_SEL 74
|
||||
#define CLKID_SARADC 75
|
||||
#define CLKID_PWM_A 76
|
||||
#define CLKID_PWM_B 77
|
||||
|
|
@ -95,21 +99,70 @@
|
|||
#define CLKID_SD_EMMC 86
|
||||
#define CLKID_PSRAM 87
|
||||
#define CLKID_DMC 88
|
||||
#define CLKID_SYS_A_SEL 89
|
||||
#define CLKID_SYS_A_DIV 90
|
||||
#define CLKID_SYS_A 91
|
||||
#define CLKID_SYS_B_SEL 92
|
||||
#define CLKID_SYS_B_DIV 93
|
||||
#define CLKID_SYS_B 94
|
||||
#define CLKID_DSPA_A_SEL 95
|
||||
#define CLKID_DSPA_A_DIV 96
|
||||
#define CLKID_DSPA_A 97
|
||||
#define CLKID_DSPA_B_SEL 98
|
||||
#define CLKID_DSPA_B_DIV 99
|
||||
#define CLKID_DSPA_B 100
|
||||
#define CLKID_DSPB_A_SEL 101
|
||||
#define CLKID_DSPB_A_DIV 102
|
||||
#define CLKID_DSPB_A 103
|
||||
#define CLKID_DSPB_B_SEL 104
|
||||
#define CLKID_DSPB_B_DIV 105
|
||||
#define CLKID_DSPB_B 106
|
||||
#define CLKID_RTC_32K_IN 107
|
||||
#define CLKID_RTC_32K_DIV 108
|
||||
#define CLKID_RTC_32K_XTAL 109
|
||||
#define CLKID_RTC_32K_SEL 110
|
||||
#define CLKID_CECB_32K_IN 111
|
||||
#define CLKID_CECB_32K_DIV 112
|
||||
#define CLKID_CECB_32K_SEL_PRE 113
|
||||
#define CLKID_CECB_32K_SEL 114
|
||||
#define CLKID_CECA_32K_IN 115
|
||||
#define CLKID_CECA_32K_DIV 116
|
||||
#define CLKID_CECA_32K_SEL_PRE 117
|
||||
#define CLKID_CECA_32K_SEL 118
|
||||
#define CLKID_DIV2_PRE 119
|
||||
#define CLKID_24M_DIV2 120
|
||||
#define CLKID_GEN_SEL 121
|
||||
#define CLKID_GEN_DIV 122
|
||||
#define CLKID_SARADC_DIV 123
|
||||
#define CLKID_PWM_A_SEL 124
|
||||
#define CLKID_PWM_A_DIV 125
|
||||
#define CLKID_PWM_B_SEL 126
|
||||
#define CLKID_PWM_B_DIV 127
|
||||
#define CLKID_PWM_C_SEL 128
|
||||
#define CLKID_PWM_C_DIV 129
|
||||
#define CLKID_PWM_D_SEL 130
|
||||
#define CLKID_PWM_D_DIV 131
|
||||
#define CLKID_PWM_E_SEL 132
|
||||
#define CLKID_PWM_E_DIV 133
|
||||
#define CLKID_PWM_F_SEL 134
|
||||
#define CLKID_PWM_F_DIV 135
|
||||
#define CLKID_SPICC_SEL 136
|
||||
#define CLKID_SPICC_DIV 137
|
||||
#define CLKID_SPICC_SEL2 138
|
||||
#define CLKID_TS_DIV 139
|
||||
#define CLKID_SPIFC_SEL 140
|
||||
#define CLKID_SPIFC_DIV 141
|
||||
#define CLKID_SPIFC_SEL2 142
|
||||
#define CLKID_USB_BUS_SEL 143
|
||||
#define CLKID_USB_BUS_DIV 144
|
||||
#define CLKID_SD_EMMC_SEL 145
|
||||
#define CLKID_SD_EMMC_DIV 146
|
||||
#define CLKID_SD_EMMC_SEL2 147
|
||||
#define CLKID_PSRAM_SEL 148
|
||||
#define CLKID_PSRAM_DIV 149
|
||||
#define CLKID_PSRAM_SEL2 150
|
||||
#define CLKID_DMC_SEL 151
|
||||
#define CLKID_DMC_DIV 152
|
||||
#define CLKID_DMC_SEL2 153
|
||||
|
||||
#endif /* __A1_PERIPHERALS_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -10,7 +10,12 @@
|
|||
#ifndef __A1_PLL_CLKC_H
|
||||
#define __A1_PLL_CLKC_H
|
||||
|
||||
#define CLKID_FIXED_PLL_DCO 0
|
||||
#define CLKID_FIXED_PLL 1
|
||||
#define CLKID_FCLK_DIV2_DIV 2
|
||||
#define CLKID_FCLK_DIV3_DIV 3
|
||||
#define CLKID_FCLK_DIV5_DIV 4
|
||||
#define CLKID_FCLK_DIV7_DIV 5
|
||||
#define CLKID_FCLK_DIV2 6
|
||||
#define CLKID_FCLK_DIV3 7
|
||||
#define CLKID_FCLK_DIV5 8
|
||||
|
|
|
|||
|
|
@ -37,6 +37,26 @@
|
|||
#define AUD_CLKID_SPDIFIN_CLK 56
|
||||
#define AUD_CLKID_PDM_DCLK 57
|
||||
#define AUD_CLKID_PDM_SYSCLK 58
|
||||
#define AUD_CLKID_MST_A_MCLK_SEL 59
|
||||
#define AUD_CLKID_MST_B_MCLK_SEL 60
|
||||
#define AUD_CLKID_MST_C_MCLK_SEL 61
|
||||
#define AUD_CLKID_MST_D_MCLK_SEL 62
|
||||
#define AUD_CLKID_MST_E_MCLK_SEL 63
|
||||
#define AUD_CLKID_MST_F_MCLK_SEL 64
|
||||
#define AUD_CLKID_MST_A_MCLK_DIV 65
|
||||
#define AUD_CLKID_MST_B_MCLK_DIV 66
|
||||
#define AUD_CLKID_MST_C_MCLK_DIV 67
|
||||
#define AUD_CLKID_MST_D_MCLK_DIV 68
|
||||
#define AUD_CLKID_MST_E_MCLK_DIV 69
|
||||
#define AUD_CLKID_MST_F_MCLK_DIV 70
|
||||
#define AUD_CLKID_SPDIFOUT_CLK_SEL 71
|
||||
#define AUD_CLKID_SPDIFOUT_CLK_DIV 72
|
||||
#define AUD_CLKID_SPDIFIN_CLK_SEL 73
|
||||
#define AUD_CLKID_SPDIFIN_CLK_DIV 74
|
||||
#define AUD_CLKID_PDM_DCLK_SEL 75
|
||||
#define AUD_CLKID_PDM_DCLK_DIV 76
|
||||
#define AUD_CLKID_PDM_SYSCLK_SEL 77
|
||||
#define AUD_CLKID_PDM_SYSCLK_DIV 78
|
||||
#define AUD_CLKID_MST_A_SCLK 79
|
||||
#define AUD_CLKID_MST_B_SCLK 80
|
||||
#define AUD_CLKID_MST_C_SCLK 81
|
||||
|
|
@ -49,6 +69,30 @@
|
|||
#define AUD_CLKID_MST_D_LRCLK 89
|
||||
#define AUD_CLKID_MST_E_LRCLK 90
|
||||
#define AUD_CLKID_MST_F_LRCLK 91
|
||||
#define AUD_CLKID_MST_A_SCLK_PRE_EN 92
|
||||
#define AUD_CLKID_MST_B_SCLK_PRE_EN 93
|
||||
#define AUD_CLKID_MST_C_SCLK_PRE_EN 94
|
||||
#define AUD_CLKID_MST_D_SCLK_PRE_EN 95
|
||||
#define AUD_CLKID_MST_E_SCLK_PRE_EN 96
|
||||
#define AUD_CLKID_MST_F_SCLK_PRE_EN 97
|
||||
#define AUD_CLKID_MST_A_SCLK_DIV 98
|
||||
#define AUD_CLKID_MST_B_SCLK_DIV 99
|
||||
#define AUD_CLKID_MST_C_SCLK_DIV 100
|
||||
#define AUD_CLKID_MST_D_SCLK_DIV 101
|
||||
#define AUD_CLKID_MST_E_SCLK_DIV 102
|
||||
#define AUD_CLKID_MST_F_SCLK_DIV 103
|
||||
#define AUD_CLKID_MST_A_SCLK_POST_EN 104
|
||||
#define AUD_CLKID_MST_B_SCLK_POST_EN 105
|
||||
#define AUD_CLKID_MST_C_SCLK_POST_EN 106
|
||||
#define AUD_CLKID_MST_D_SCLK_POST_EN 107
|
||||
#define AUD_CLKID_MST_E_SCLK_POST_EN 108
|
||||
#define AUD_CLKID_MST_F_SCLK_POST_EN 109
|
||||
#define AUD_CLKID_MST_A_LRCLK_DIV 110
|
||||
#define AUD_CLKID_MST_B_LRCLK_DIV 111
|
||||
#define AUD_CLKID_MST_C_LRCLK_DIV 112
|
||||
#define AUD_CLKID_MST_D_LRCLK_DIV 113
|
||||
#define AUD_CLKID_MST_E_LRCLK_DIV 114
|
||||
#define AUD_CLKID_MST_F_LRCLK_DIV 115
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_SEL 116
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_SEL 117
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_SEL 118
|
||||
|
|
@ -70,8 +114,24 @@
|
|||
#define AUD_CLKID_TDMOUT_A_LRCLK 134
|
||||
#define AUD_CLKID_TDMOUT_B_LRCLK 135
|
||||
#define AUD_CLKID_TDMOUT_C_LRCLK 136
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
|
||||
#define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
|
||||
#define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
|
||||
#define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
|
||||
#define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
|
||||
#define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
|
||||
#define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
|
||||
#define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
|
||||
#define AUD_CLKID_SPDIFOUT_B 151
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK 152
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
|
||||
#define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
|
||||
#define AUD_CLKID_TDM_MCLK_PAD0 155
|
||||
#define AUD_CLKID_TDM_MCLK_PAD1 156
|
||||
#define AUD_CLKID_TDM_LRCLK_PAD0 157
|
||||
|
|
@ -90,5 +150,10 @@
|
|||
#define AUD_CLKID_FRDDR_D 170
|
||||
#define AUD_CLKID_TODDR_D 171
|
||||
#define AUD_CLKID_LOOPBACK_B 172
|
||||
#define AUD_CLKID_CLK81_EN 173
|
||||
#define AUD_CLKID_SYSCLK_A_DIV 174
|
||||
#define AUD_CLKID_SYSCLK_B_DIV 175
|
||||
#define AUD_CLKID_SYSCLK_A_EN 176
|
||||
#define AUD_CLKID_SYSCLK_B_EN 177
|
||||
|
||||
#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
#define CLKID_FCLK_DIV5 5
|
||||
#define CLKID_FCLK_DIV7 6
|
||||
#define CLKID_GP0_PLL 7
|
||||
#define CLKID_MPEG_SEL 8
|
||||
#define CLKID_MPEG_DIV 9
|
||||
#define CLKID_CLK81 10
|
||||
#define CLKID_MPLL0 11
|
||||
#define CLKID_MPLL1 12
|
||||
|
|
@ -67,23 +69,66 @@
|
|||
#define CLKID_AO_I2C 58
|
||||
#define CLKID_SD_EMMC_B_CLK0 59
|
||||
#define CLKID_SD_EMMC_C_CLK0 60
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 61
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 62
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 63
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 64
|
||||
#define CLKID_MPLL0_DIV 65
|
||||
#define CLKID_MPLL1_DIV 66
|
||||
#define CLKID_MPLL2_DIV 67
|
||||
#define CLKID_MPLL3_DIV 68
|
||||
#define CLKID_HIFI_PLL 69
|
||||
#define CLKID_MPLL_PREDIV 70
|
||||
#define CLKID_FCLK_DIV2_DIV 71
|
||||
#define CLKID_FCLK_DIV3_DIV 72
|
||||
#define CLKID_FCLK_DIV4_DIV 73
|
||||
#define CLKID_FCLK_DIV5_DIV 74
|
||||
#define CLKID_FCLK_DIV7_DIV 75
|
||||
#define CLKID_PCIE_PLL 76
|
||||
#define CLKID_PCIE_MUX 77
|
||||
#define CLKID_PCIE_REF 78
|
||||
#define CLKID_PCIE_CML_EN0 79
|
||||
#define CLKID_PCIE_CML_EN1 80
|
||||
#define CLKID_GEN_CLK_SEL 82
|
||||
#define CLKID_GEN_CLK_DIV 83
|
||||
#define CLKID_GEN_CLK 84
|
||||
#define CLKID_SYS_PLL_DCO 85
|
||||
#define CLKID_FIXED_PLL_DCO 86
|
||||
#define CLKID_GP0_PLL_DCO 87
|
||||
#define CLKID_HIFI_PLL_DCO 88
|
||||
#define CLKID_PCIE_PLL_DCO 89
|
||||
#define CLKID_PCIE_PLL_OD 90
|
||||
#define CLKID_VPU_0_DIV 91
|
||||
#define CLKID_VPU_0_SEL 92
|
||||
#define CLKID_VPU_0 93
|
||||
#define CLKID_VPU_1_DIV 94
|
||||
#define CLKID_VPU_1_SEL 95
|
||||
#define CLKID_VPU_1 96
|
||||
#define CLKID_VPU 97
|
||||
#define CLKID_VAPB_0_DIV 98
|
||||
#define CLKID_VAPB_0_SEL 99
|
||||
#define CLKID_VAPB_0 100
|
||||
#define CLKID_VAPB_1_DIV 101
|
||||
#define CLKID_VAPB_1_SEL 102
|
||||
#define CLKID_VAPB_1 103
|
||||
#define CLKID_VAPB_SEL 104
|
||||
#define CLKID_VAPB 105
|
||||
#define CLKID_VCLK 106
|
||||
#define CLKID_VCLK2 107
|
||||
#define CLKID_VCLK_SEL 108
|
||||
#define CLKID_VCLK2_SEL 109
|
||||
#define CLKID_VCLK_INPUT 110
|
||||
#define CLKID_VCLK2_INPUT 111
|
||||
#define CLKID_VCLK_DIV 112
|
||||
#define CLKID_VCLK2_DIV 113
|
||||
#define CLKID_VCLK_DIV2_EN 114
|
||||
#define CLKID_VCLK_DIV4_EN 115
|
||||
#define CLKID_VCLK_DIV6_EN 116
|
||||
#define CLKID_VCLK_DIV12_EN 117
|
||||
#define CLKID_VCLK2_DIV2_EN 118
|
||||
#define CLKID_VCLK2_DIV4_EN 119
|
||||
#define CLKID_VCLK2_DIV6_EN 120
|
||||
#define CLKID_VCLK2_DIV12_EN 121
|
||||
#define CLKID_VCLK_DIV1 122
|
||||
#define CLKID_VCLK_DIV2 123
|
||||
#define CLKID_VCLK_DIV4 124
|
||||
|
|
@ -94,7 +139,10 @@
|
|||
#define CLKID_VCLK2_DIV4 129
|
||||
#define CLKID_VCLK2_DIV6 130
|
||||
#define CLKID_VCLK2_DIV12 131
|
||||
#define CLKID_CTS_ENCL_SEL 132
|
||||
#define CLKID_CTS_ENCL 133
|
||||
#define CLKID_VDIN_MEAS_SEL 134
|
||||
#define CLKID_VDIN_MEAS_DIV 135
|
||||
#define CLKID_VDIN_MEAS 136
|
||||
|
||||
#endif /* __AXG_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -26,10 +26,17 @@
|
|||
#define CLKID_AO_M4_FCLK 13
|
||||
#define CLKID_AO_M4_HCLK 14
|
||||
#define CLKID_AO_CLK81 15
|
||||
#define CLKID_AO_SAR_ADC_DIV 17
|
||||
#define CLKID_AO_SAR_ADC_SEL 16
|
||||
#define CLKID_AO_SAR_ADC_CLK 18
|
||||
#define CLKID_AO_CTS_OSCIN 19
|
||||
#define CLKID_AO_32K_PRE 20
|
||||
#define CLKID_AO_32K_DIV 21
|
||||
#define CLKID_AO_32K_SEL 22
|
||||
#define CLKID_AO_32K 23
|
||||
#define CLKID_AO_CEC_PRE 24
|
||||
#define CLKID_AO_CEC_DIV 25
|
||||
#define CLKID_AO_CEC_SEL 26
|
||||
#define CLKID_AO_CEC 27
|
||||
#define CLKID_AO_CTS_RTC_OSCIN 28
|
||||
|
||||
|
|
|
|||
|
|
@ -16,6 +16,8 @@
|
|||
#define CLKID_FCLK_DIV5 5
|
||||
#define CLKID_FCLK_DIV7 6
|
||||
#define CLKID_GP0_PLL 7
|
||||
#define CLKID_MPEG_SEL 8
|
||||
#define CLKID_MPEG_DIV 9
|
||||
#define CLKID_CLK81 10
|
||||
#define CLKID_MPLL0 11
|
||||
#define CLKID_MPLL1 12
|
||||
|
|
@ -69,7 +71,23 @@
|
|||
#define CLKID_SD_EMMC_A_CLK0 60
|
||||
#define CLKID_SD_EMMC_B_CLK0 61
|
||||
#define CLKID_SD_EMMC_C_CLK0 62
|
||||
#define CLKID_SD_EMMC_A_CLK0_SEL 63
|
||||
#define CLKID_SD_EMMC_A_CLK0_DIV 64
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 65
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 66
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 67
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 68
|
||||
#define CLKID_MPLL0_DIV 69
|
||||
#define CLKID_MPLL1_DIV 70
|
||||
#define CLKID_MPLL2_DIV 71
|
||||
#define CLKID_MPLL3_DIV 72
|
||||
#define CLKID_MPLL_PREDIV 73
|
||||
#define CLKID_HIFI_PLL 74
|
||||
#define CLKID_FCLK_DIV2_DIV 75
|
||||
#define CLKID_FCLK_DIV3_DIV 76
|
||||
#define CLKID_FCLK_DIV4_DIV 77
|
||||
#define CLKID_FCLK_DIV5_DIV 78
|
||||
#define CLKID_FCLK_DIV7_DIV 79
|
||||
#define CLKID_VCLK2_VENCI0 80
|
||||
#define CLKID_VCLK2_VENCI1 81
|
||||
#define CLKID_VCLK2_VENCP0 82
|
||||
|
|
@ -90,26 +108,54 @@
|
|||
#define CLKID_VCLK2_VENCL 97
|
||||
#define CLKID_VCLK2_OTHER1 98
|
||||
#define CLKID_FCLK_DIV2P5 99
|
||||
#define CLKID_FCLK_DIV2P5_DIV 100
|
||||
#define CLKID_FIXED_PLL_DCO 101
|
||||
#define CLKID_SYS_PLL_DCO 102
|
||||
#define CLKID_GP0_PLL_DCO 103
|
||||
#define CLKID_HIFI_PLL_DCO 104
|
||||
#define CLKID_DMA 105
|
||||
#define CLKID_EFUSE 106
|
||||
#define CLKID_ROM_BOOT 107
|
||||
#define CLKID_RESET_SEC 108
|
||||
#define CLKID_SEC_AHB_APB3 109
|
||||
#define CLKID_VPU_0_SEL 110
|
||||
#define CLKID_VPU_0_DIV 111
|
||||
#define CLKID_VPU_0 112
|
||||
#define CLKID_VPU_1_SEL 113
|
||||
#define CLKID_VPU_1_DIV 114
|
||||
#define CLKID_VPU_1 115
|
||||
#define CLKID_VPU 116
|
||||
#define CLKID_VAPB_0_SEL 117
|
||||
#define CLKID_VAPB_0_DIV 118
|
||||
#define CLKID_VAPB_0 119
|
||||
#define CLKID_VAPB_1_SEL 120
|
||||
#define CLKID_VAPB_1_DIV 121
|
||||
#define CLKID_VAPB_1 122
|
||||
#define CLKID_VAPB_SEL 123
|
||||
#define CLKID_VAPB 124
|
||||
#define CLKID_HDMI_PLL_DCO 125
|
||||
#define CLKID_HDMI_PLL_OD 126
|
||||
#define CLKID_HDMI_PLL_OD2 127
|
||||
#define CLKID_HDMI_PLL 128
|
||||
#define CLKID_VID_PLL 129
|
||||
#define CLKID_VID_PLL_SEL 130
|
||||
#define CLKID_VID_PLL_DIV 131
|
||||
#define CLKID_VCLK_SEL 132
|
||||
#define CLKID_VCLK2_SEL 133
|
||||
#define CLKID_VCLK_INPUT 134
|
||||
#define CLKID_VCLK2_INPUT 135
|
||||
#define CLKID_VCLK_DIV 136
|
||||
#define CLKID_VCLK2_DIV 137
|
||||
#define CLKID_VCLK 138
|
||||
#define CLKID_VCLK2 139
|
||||
#define CLKID_VCLK_DIV2_EN 140
|
||||
#define CLKID_VCLK_DIV4_EN 141
|
||||
#define CLKID_VCLK_DIV6_EN 142
|
||||
#define CLKID_VCLK_DIV12_EN 143
|
||||
#define CLKID_VCLK2_DIV2_EN 144
|
||||
#define CLKID_VCLK2_DIV4_EN 145
|
||||
#define CLKID_VCLK2_DIV6_EN 146
|
||||
#define CLKID_VCLK2_DIV12_EN 147
|
||||
#define CLKID_VCLK_DIV1 148
|
||||
#define CLKID_VCLK_DIV2 149
|
||||
#define CLKID_VCLK_DIV4 150
|
||||
|
|
@ -120,33 +166,117 @@
|
|||
#define CLKID_VCLK2_DIV4 155
|
||||
#define CLKID_VCLK2_DIV6 156
|
||||
#define CLKID_VCLK2_DIV12 157
|
||||
#define CLKID_CTS_ENCI_SEL 158
|
||||
#define CLKID_CTS_ENCP_SEL 159
|
||||
#define CLKID_CTS_VDAC_SEL 160
|
||||
#define CLKID_HDMI_TX_SEL 161
|
||||
#define CLKID_CTS_ENCI 162
|
||||
#define CLKID_CTS_ENCP 163
|
||||
#define CLKID_CTS_VDAC 164
|
||||
#define CLKID_HDMI_TX 165
|
||||
#define CLKID_HDMI_SEL 166
|
||||
#define CLKID_HDMI_DIV 167
|
||||
#define CLKID_HDMI 168
|
||||
#define CLKID_MALI_0_SEL 169
|
||||
#define CLKID_MALI_0_DIV 170
|
||||
#define CLKID_MALI_0 171
|
||||
#define CLKID_MALI_1_SEL 172
|
||||
#define CLKID_MALI_1_DIV 173
|
||||
#define CLKID_MALI_1 174
|
||||
#define CLKID_MALI 175
|
||||
#define CLKID_MPLL_50M_DIV 176
|
||||
#define CLKID_MPLL_50M 177
|
||||
#define CLKID_SYS_PLL_DIV16_EN 178
|
||||
#define CLKID_SYS_PLL_DIV16 179
|
||||
#define CLKID_CPU_CLK_DYN0_SEL 180
|
||||
#define CLKID_CPU_CLK_DYN0_DIV 181
|
||||
#define CLKID_CPU_CLK_DYN0 182
|
||||
#define CLKID_CPU_CLK_DYN1_SEL 183
|
||||
#define CLKID_CPU_CLK_DYN1_DIV 184
|
||||
#define CLKID_CPU_CLK_DYN1 185
|
||||
#define CLKID_CPU_CLK_DYN 186
|
||||
#define CLKID_CPU_CLK 187
|
||||
#define CLKID_CPU_CLK_DIV16_EN 188
|
||||
#define CLKID_CPU_CLK_DIV16 189
|
||||
#define CLKID_CPU_CLK_APB_DIV 190
|
||||
#define CLKID_CPU_CLK_APB 191
|
||||
#define CLKID_CPU_CLK_ATB_DIV 192
|
||||
#define CLKID_CPU_CLK_ATB 193
|
||||
#define CLKID_CPU_CLK_AXI_DIV 194
|
||||
#define CLKID_CPU_CLK_AXI 195
|
||||
#define CLKID_CPU_CLK_TRACE_DIV 196
|
||||
#define CLKID_CPU_CLK_TRACE 197
|
||||
#define CLKID_PCIE_PLL_DCO 198
|
||||
#define CLKID_PCIE_PLL_DCO_DIV2 199
|
||||
#define CLKID_PCIE_PLL_OD 200
|
||||
#define CLKID_PCIE_PLL 201
|
||||
#define CLKID_VDEC_1_SEL 202
|
||||
#define CLKID_VDEC_1_DIV 203
|
||||
#define CLKID_VDEC_1 204
|
||||
#define CLKID_VDEC_HEVC_SEL 205
|
||||
#define CLKID_VDEC_HEVC_DIV 206
|
||||
#define CLKID_VDEC_HEVC 207
|
||||
#define CLKID_VDEC_HEVCF_SEL 208
|
||||
#define CLKID_VDEC_HEVCF_DIV 209
|
||||
#define CLKID_VDEC_HEVCF 210
|
||||
#define CLKID_TS_DIV 211
|
||||
#define CLKID_TS 212
|
||||
#define CLKID_SYS1_PLL_DCO 213
|
||||
#define CLKID_SYS1_PLL 214
|
||||
#define CLKID_SYS1_PLL_DIV16_EN 215
|
||||
#define CLKID_SYS1_PLL_DIV16 216
|
||||
#define CLKID_CPUB_CLK_DYN0_SEL 217
|
||||
#define CLKID_CPUB_CLK_DYN0_DIV 218
|
||||
#define CLKID_CPUB_CLK_DYN0 219
|
||||
#define CLKID_CPUB_CLK_DYN1_SEL 220
|
||||
#define CLKID_CPUB_CLK_DYN1_DIV 221
|
||||
#define CLKID_CPUB_CLK_DYN1 222
|
||||
#define CLKID_CPUB_CLK_DYN 223
|
||||
#define CLKID_CPUB_CLK 224
|
||||
#define CLKID_CPUB_CLK_DIV16_EN 225
|
||||
#define CLKID_CPUB_CLK_DIV16 226
|
||||
#define CLKID_CPUB_CLK_DIV2 227
|
||||
#define CLKID_CPUB_CLK_DIV3 228
|
||||
#define CLKID_CPUB_CLK_DIV4 229
|
||||
#define CLKID_CPUB_CLK_DIV5 230
|
||||
#define CLKID_CPUB_CLK_DIV6 231
|
||||
#define CLKID_CPUB_CLK_DIV7 232
|
||||
#define CLKID_CPUB_CLK_DIV8 233
|
||||
#define CLKID_CPUB_CLK_APB_SEL 234
|
||||
#define CLKID_CPUB_CLK_APB 235
|
||||
#define CLKID_CPUB_CLK_ATB_SEL 236
|
||||
#define CLKID_CPUB_CLK_ATB 237
|
||||
#define CLKID_CPUB_CLK_AXI_SEL 238
|
||||
#define CLKID_CPUB_CLK_AXI 239
|
||||
#define CLKID_CPUB_CLK_TRACE_SEL 240
|
||||
#define CLKID_CPUB_CLK_TRACE 241
|
||||
#define CLKID_GP1_PLL_DCO 242
|
||||
#define CLKID_GP1_PLL 243
|
||||
#define CLKID_DSU_CLK_DYN0_SEL 244
|
||||
#define CLKID_DSU_CLK_DYN0_DIV 245
|
||||
#define CLKID_DSU_CLK_DYN0 246
|
||||
#define CLKID_DSU_CLK_DYN1_SEL 247
|
||||
#define CLKID_DSU_CLK_DYN1_DIV 248
|
||||
#define CLKID_DSU_CLK_DYN1 249
|
||||
#define CLKID_DSU_CLK_DYN 250
|
||||
#define CLKID_DSU_CLK_FINAL 251
|
||||
#define CLKID_DSU_CLK 252
|
||||
#define CLKID_CPU1_CLK 253
|
||||
#define CLKID_CPU2_CLK 254
|
||||
#define CLKID_CPU3_CLK 255
|
||||
#define CLKID_SPICC0_SCLK_SEL 256
|
||||
#define CLKID_SPICC0_SCLK_DIV 257
|
||||
#define CLKID_SPICC0_SCLK 258
|
||||
#define CLKID_SPICC1_SCLK_SEL 259
|
||||
#define CLKID_SPICC1_SCLK_DIV 260
|
||||
#define CLKID_SPICC1_SCLK 261
|
||||
#define CLKID_NNA_AXI_CLK_SEL 262
|
||||
#define CLKID_NNA_AXI_CLK_DIV 263
|
||||
#define CLKID_NNA_AXI_CLK 264
|
||||
#define CLKID_NNA_CORE_CLK_SEL 265
|
||||
#define CLKID_NNA_CORE_CLK_DIV 266
|
||||
#define CLKID_NNA_CORE_CLK 267
|
||||
#define CLKID_MIPI_DSI_PXCLK_DIV 268
|
||||
#define CLKID_MIPI_DSI_PXCLK_SEL 269
|
||||
#define CLKID_MIPI_DSI_PXCLK 270
|
||||
|
||||
|
|
|
|||
|
|
@ -15,6 +15,8 @@
|
|||
#define CLKID_FCLK_DIV5 7
|
||||
#define CLKID_FCLK_DIV7 8
|
||||
#define CLKID_GP0_PLL 9
|
||||
#define CLKID_MPEG_SEL 10
|
||||
#define CLKID_MPEG_DIV 11
|
||||
#define CLKID_CLK81 12
|
||||
#define CLKID_MPLL0 13
|
||||
#define CLKID_MPLL1 14
|
||||
|
|
@ -102,35 +104,92 @@
|
|||
#define CLKID_SD_EMMC_C 96
|
||||
#define CLKID_SAR_ADC_CLK 97
|
||||
#define CLKID_SAR_ADC_SEL 98
|
||||
#define CLKID_SAR_ADC_DIV 99
|
||||
#define CLKID_MALI_0_SEL 100
|
||||
#define CLKID_MALI_0_DIV 101
|
||||
#define CLKID_MALI_0 102
|
||||
#define CLKID_MALI_1_SEL 103
|
||||
#define CLKID_MALI_1_DIV 104
|
||||
#define CLKID_MALI_1 105
|
||||
#define CLKID_MALI 106
|
||||
#define CLKID_CTS_AMCLK 107
|
||||
#define CLKID_CTS_AMCLK_SEL 108
|
||||
#define CLKID_CTS_AMCLK_DIV 109
|
||||
#define CLKID_CTS_MCLK_I958 110
|
||||
#define CLKID_CTS_MCLK_I958_SEL 111
|
||||
#define CLKID_CTS_MCLK_I958_DIV 112
|
||||
#define CLKID_CTS_I958 113
|
||||
#define CLKID_32K_CLK 114
|
||||
#define CLKID_32K_CLK_SEL 115
|
||||
#define CLKID_32K_CLK_DIV 116
|
||||
#define CLKID_SD_EMMC_A_CLK0_SEL 117
|
||||
#define CLKID_SD_EMMC_A_CLK0_DIV 118
|
||||
#define CLKID_SD_EMMC_A_CLK0 119
|
||||
#define CLKID_SD_EMMC_B_CLK0_SEL 120
|
||||
#define CLKID_SD_EMMC_B_CLK0_DIV 121
|
||||
#define CLKID_SD_EMMC_B_CLK0 122
|
||||
#define CLKID_SD_EMMC_C_CLK0_SEL 123
|
||||
#define CLKID_SD_EMMC_C_CLK0_DIV 124
|
||||
#define CLKID_SD_EMMC_C_CLK0 125
|
||||
#define CLKID_VPU_0_SEL 126
|
||||
#define CLKID_VPU_0_DIV 127
|
||||
#define CLKID_VPU_0 128
|
||||
#define CLKID_VPU_1_SEL 129
|
||||
#define CLKID_VPU_1_DIV 130
|
||||
#define CLKID_VPU_1 131
|
||||
#define CLKID_VPU 132
|
||||
#define CLKID_VAPB_0_SEL 133
|
||||
#define CLKID_VAPB_0_DIV 134
|
||||
#define CLKID_VAPB_0 135
|
||||
#define CLKID_VAPB_1_SEL 136
|
||||
#define CLKID_VAPB_1_DIV 137
|
||||
#define CLKID_VAPB_1 138
|
||||
#define CLKID_VAPB_SEL 139
|
||||
#define CLKID_VAPB 140
|
||||
#define CLKID_HDMI_PLL_PRE_MULT 141
|
||||
#define CLKID_MPLL0_DIV 142
|
||||
#define CLKID_MPLL1_DIV 143
|
||||
#define CLKID_MPLL2_DIV 144
|
||||
#define CLKID_MPLL_PREDIV 145
|
||||
#define CLKID_FCLK_DIV2_DIV 146
|
||||
#define CLKID_FCLK_DIV3_DIV 147
|
||||
#define CLKID_FCLK_DIV4_DIV 148
|
||||
#define CLKID_FCLK_DIV5_DIV 149
|
||||
#define CLKID_FCLK_DIV7_DIV 150
|
||||
#define CLKID_VDEC_1_SEL 151
|
||||
#define CLKID_VDEC_1_DIV 152
|
||||
#define CLKID_VDEC_1 153
|
||||
#define CLKID_VDEC_HEVC_SEL 154
|
||||
#define CLKID_VDEC_HEVC_DIV 155
|
||||
#define CLKID_VDEC_HEVC 156
|
||||
#define CLKID_GEN_CLK_SEL 157
|
||||
#define CLKID_GEN_CLK_DIV 158
|
||||
#define CLKID_GEN_CLK 159
|
||||
#define CLKID_FIXED_PLL_DCO 160
|
||||
#define CLKID_HDMI_PLL_DCO 161
|
||||
#define CLKID_HDMI_PLL_OD 162
|
||||
#define CLKID_HDMI_PLL_OD2 163
|
||||
#define CLKID_SYS_PLL_DCO 164
|
||||
#define CLKID_GP0_PLL_DCO 165
|
||||
#define CLKID_VID_PLL 166
|
||||
#define CLKID_VID_PLL_SEL 167
|
||||
#define CLKID_VID_PLL_DIV 168
|
||||
#define CLKID_VCLK_SEL 169
|
||||
#define CLKID_VCLK2_SEL 170
|
||||
#define CLKID_VCLK_INPUT 171
|
||||
#define CLKID_VCLK2_INPUT 172
|
||||
#define CLKID_VCLK_DIV 173
|
||||
#define CLKID_VCLK2_DIV 174
|
||||
#define CLKID_VCLK 175
|
||||
#define CLKID_VCLK2 176
|
||||
#define CLKID_VCLK_DIV2_EN 177
|
||||
#define CLKID_VCLK_DIV4_EN 178
|
||||
#define CLKID_VCLK_DIV6_EN 179
|
||||
#define CLKID_VCLK_DIV12_EN 180
|
||||
#define CLKID_VCLK2_DIV2_EN 181
|
||||
#define CLKID_VCLK2_DIV4_EN 182
|
||||
#define CLKID_VCLK2_DIV6_EN 183
|
||||
#define CLKID_VCLK2_DIV12_EN 184
|
||||
#define CLKID_VCLK_DIV1 185
|
||||
#define CLKID_VCLK_DIV2 186
|
||||
#define CLKID_VCLK_DIV4 187
|
||||
|
|
@ -141,10 +200,16 @@
|
|||
#define CLKID_VCLK2_DIV4 192
|
||||
#define CLKID_VCLK2_DIV6 193
|
||||
#define CLKID_VCLK2_DIV12 194
|
||||
#define CLKID_CTS_ENCI_SEL 195
|
||||
#define CLKID_CTS_ENCP_SEL 196
|
||||
#define CLKID_CTS_VDAC_SEL 197
|
||||
#define CLKID_HDMI_TX_SEL 198
|
||||
#define CLKID_CTS_ENCI 199
|
||||
#define CLKID_CTS_ENCP 200
|
||||
#define CLKID_CTS_VDAC 201
|
||||
#define CLKID_HDMI_TX 202
|
||||
#define CLKID_HDMI_SEL 203
|
||||
#define CLKID_HDMI_DIV 204
|
||||
#define CLKID_HDMI 205
|
||||
#define CLKID_ACODEC 206
|
||||
|
||||
|
|
|
|||
|
|
@ -100,29 +100,126 @@
|
|||
#define CLKID_MPLL0 93
|
||||
#define CLKID_MPLL1 94
|
||||
#define CLKID_MPLL2 95
|
||||
#define CLKID_MPLL0_DIV 96
|
||||
#define CLKID_MPLL1_DIV 97
|
||||
#define CLKID_MPLL2_DIV 98
|
||||
#define CLKID_CPU_IN_SEL 99
|
||||
#define CLKID_CPU_IN_DIV2 100
|
||||
#define CLKID_CPU_IN_DIV3 101
|
||||
#define CLKID_CPU_SCALE_DIV 102
|
||||
#define CLKID_CPU_SCALE_OUT_SEL 103
|
||||
#define CLKID_MPLL_PREDIV 104
|
||||
#define CLKID_FCLK_DIV2_DIV 105
|
||||
#define CLKID_FCLK_DIV3_DIV 106
|
||||
#define CLKID_FCLK_DIV4_DIV 107
|
||||
#define CLKID_FCLK_DIV5_DIV 108
|
||||
#define CLKID_FCLK_DIV7_DIV 109
|
||||
#define CLKID_NAND_SEL 110
|
||||
#define CLKID_NAND_DIV 111
|
||||
#define CLKID_NAND_CLK 112
|
||||
#define CLKID_PLL_FIXED_DCO 113
|
||||
#define CLKID_HDMI_PLL_DCO 114
|
||||
#define CLKID_PLL_SYS_DCO 115
|
||||
#define CLKID_CPU_CLK_DIV2 116
|
||||
#define CLKID_CPU_CLK_DIV3 117
|
||||
#define CLKID_CPU_CLK_DIV4 118
|
||||
#define CLKID_CPU_CLK_DIV5 119
|
||||
#define CLKID_CPU_CLK_DIV6 120
|
||||
#define CLKID_CPU_CLK_DIV7 121
|
||||
#define CLKID_CPU_CLK_DIV8 122
|
||||
#define CLKID_APB_SEL 123
|
||||
#define CLKID_APB 124
|
||||
#define CLKID_PERIPH_SEL 125
|
||||
#define CLKID_PERIPH 126
|
||||
#define CLKID_AXI_SEL 127
|
||||
#define CLKID_AXI 128
|
||||
#define CLKID_L2_DRAM 130
|
||||
#define CLKID_L2_DRAM_SEL 129
|
||||
#define CLKID_HDMI_PLL_LVDS_OUT 131
|
||||
#define CLKID_HDMI_PLL_HDMI_OUT 132
|
||||
#define CLKID_VID_PLL_IN_SEL 133
|
||||
#define CLKID_VID_PLL_IN_EN 134
|
||||
#define CLKID_VID_PLL_PRE_DIV 135
|
||||
#define CLKID_VID_PLL_POST_DIV 136
|
||||
#define CLKID_VID_PLL_FINAL_DIV 137
|
||||
#define CLKID_VCLK_IN_SEL 138
|
||||
#define CLKID_VCLK_IN_EN 139
|
||||
#define CLKID_VCLK_DIV1 140
|
||||
#define CLKID_VCLK_DIV2_DIV 141
|
||||
#define CLKID_VCLK_DIV2 142
|
||||
#define CLKID_VCLK_DIV4_DIV 143
|
||||
#define CLKID_VCLK_DIV4 144
|
||||
#define CLKID_VCLK_DIV6_DIV 145
|
||||
#define CLKID_VCLK_DIV6 146
|
||||
#define CLKID_VCLK_DIV12_DIV 147
|
||||
#define CLKID_VCLK_DIV12 148
|
||||
#define CLKID_VCLK2_IN_SEL 149
|
||||
#define CLKID_VCLK2_IN_EN 150
|
||||
#define CLKID_VCLK2_DIV1 151
|
||||
#define CLKID_VCLK2_DIV2_DIV 152
|
||||
#define CLKID_VCLK2_DIV2 153
|
||||
#define CLKID_VCLK2_DIV4_DIV 154
|
||||
#define CLKID_VCLK2_DIV4 155
|
||||
#define CLKID_VCLK2_DIV6_DIV 156
|
||||
#define CLKID_VCLK2_DIV6 157
|
||||
#define CLKID_VCLK2_DIV12_DIV 158
|
||||
#define CLKID_VCLK2_DIV12 159
|
||||
#define CLKID_CTS_ENCT_SEL 160
|
||||
#define CLKID_CTS_ENCT 161
|
||||
#define CLKID_CTS_ENCP_SEL 162
|
||||
#define CLKID_CTS_ENCP 163
|
||||
#define CLKID_CTS_ENCI_SEL 164
|
||||
#define CLKID_CTS_ENCI 165
|
||||
#define CLKID_HDMI_TX_PIXEL_SEL 166
|
||||
#define CLKID_HDMI_TX_PIXEL 167
|
||||
#define CLKID_CTS_ENCL_SEL 168
|
||||
#define CLKID_CTS_ENCL 169
|
||||
#define CLKID_CTS_VDAC0_SEL 170
|
||||
#define CLKID_CTS_VDAC0 171
|
||||
#define CLKID_HDMI_SYS_SEL 172
|
||||
#define CLKID_HDMI_SYS_DIV 173
|
||||
#define CLKID_HDMI_SYS 174
|
||||
#define CLKID_MALI_0_SEL 175
|
||||
#define CLKID_MALI_0_DIV 176
|
||||
#define CLKID_MALI_0 177
|
||||
#define CLKID_MALI_1_SEL 178
|
||||
#define CLKID_MALI_1_DIV 179
|
||||
#define CLKID_MALI_1 180
|
||||
#define CLKID_GP_PLL_DCO 181
|
||||
#define CLKID_GP_PLL 182
|
||||
#define CLKID_VPU_0_SEL 183
|
||||
#define CLKID_VPU_0_DIV 184
|
||||
#define CLKID_VPU_0 185
|
||||
#define CLKID_VPU_1_SEL 186
|
||||
#define CLKID_VPU_1_DIV 187
|
||||
#define CLKID_VPU_1 189
|
||||
#define CLKID_VPU 190
|
||||
#define CLKID_VDEC_1_SEL 191
|
||||
#define CLKID_VDEC_1_1_DIV 192
|
||||
#define CLKID_VDEC_1_1 193
|
||||
#define CLKID_VDEC_1_2_DIV 194
|
||||
#define CLKID_VDEC_1_2 195
|
||||
#define CLKID_VDEC_1 196
|
||||
#define CLKID_VDEC_HCODEC_SEL 197
|
||||
#define CLKID_VDEC_HCODEC_DIV 198
|
||||
#define CLKID_VDEC_HCODEC 199
|
||||
#define CLKID_VDEC_2_SEL 200
|
||||
#define CLKID_VDEC_2_DIV 201
|
||||
#define CLKID_VDEC_2 202
|
||||
#define CLKID_VDEC_HEVC_SEL 203
|
||||
#define CLKID_VDEC_HEVC_DIV 204
|
||||
#define CLKID_VDEC_HEVC_EN 205
|
||||
#define CLKID_VDEC_HEVC 206
|
||||
#define CLKID_CTS_AMCLK_SEL 207
|
||||
#define CLKID_CTS_AMCLK_DIV 208
|
||||
#define CLKID_CTS_AMCLK 209
|
||||
#define CLKID_CTS_MCLK_I958_SEL 210
|
||||
#define CLKID_CTS_MCLK_I958_DIV 211
|
||||
#define CLKID_CTS_MCLK_I958 212
|
||||
#define CLKID_CTS_I958 213
|
||||
#define CLKID_VCLK_EN 214
|
||||
#define CLKID_VCLK2_EN 215
|
||||
#define CLKID_VID_PLL_LVDS_EN 216
|
||||
#define CLKID_HDMI_PLL_DCO_IN 217
|
||||
|
||||
#endif /* __MESON8B_CLKC_H */
|
||||
|
|
|
|||
|
|
@ -109,6 +109,8 @@ char *kstrdup_quotable(const char *src, gfp_t gfp);
|
|||
char *kstrdup_quotable_cmdline(struct task_struct *task, gfp_t gfp);
|
||||
char *kstrdup_quotable_file(struct file *file, gfp_t gfp);
|
||||
|
||||
char *kstrdup_and_replace(const char *src, char old, char new, gfp_t gfp);
|
||||
|
||||
char **kasprintf_strarray(gfp_t gfp, const char *prefix, size_t n);
|
||||
void kfree_strarray(char **array, size_t n);
|
||||
|
||||
|
|
|
|||
|
|
@ -719,6 +719,21 @@ char *kstrdup_quotable_file(struct file *file, gfp_t gfp)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(kstrdup_quotable_file);
|
||||
|
||||
/*
|
||||
* Returns duplicate string in which the @old characters are replaced by @new.
|
||||
*/
|
||||
char *kstrdup_and_replace(const char *src, char old, char new, gfp_t gfp)
|
||||
{
|
||||
char *dst;
|
||||
|
||||
dst = kstrdup(src, gfp);
|
||||
if (!dst)
|
||||
return NULL;
|
||||
|
||||
return strreplace(dst, old, new);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kstrdup_and_replace);
|
||||
|
||||
/**
|
||||
* kasprintf_strarray - allocate and fill array of sequential strings
|
||||
* @gfp: flags for the slab allocator
|
||||
|
|
|
|||
Loading…
Reference in a new issue