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asm-generic: New generic ticket-based spinlock
This contains a new ticket-based spinlock that uses only generic atomics and doesn't require as much from the memory system as qspinlock does in order to be fair. It also includes a bit of documentation about the qspinlock and qrwlock fairness requirements. This will soon be used by a handful of architectures that don't meet the qspinlock requirements. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmJ8BZETHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYiWC2D/4qA9r9Niv/Vw9/H08+kefmYsVLjoZ7 n9tbS5+Rj/8TCwVpqQSkJix16XGVP760KT4XmmljJMNjKiHP4Vg8ZsNfewK6gxer Dk1MkrTEUk+yzCheyCFramwBmvz+tV1qDSq+/Lgl2jMDwlKRidVW3mGkeh4y+QRF Xvc3voW689ZGtnsPNjdAsXRKJrhTsdAXaj57RSiPXKGTJS5Ll+FO6pgNMW7fkAL3 XnWRVM03WpvNh70RcSV3jfZN2CSTRaw8d44CEOkGtbFTe9qwFkuSqhpTyCyfJ+NL 0Z3K4ZUypcjgC4lkxXJzvQhe5Vi3S7GFypzMeyAinjNegrXWY7Ke09mYClVPplwO kt2GTCmHcCMItZI9G7DLtYkNozlvNtCD0Qb63UptBxzqIedcKtNg+kY2Ovmnbi0A PeGN5OiARlpiwtYnJMh3fq5muMakDBm+You8u0tB0eKvBorvElteBwqwOg2zdhka iuoLtOtgD/Sx6UWvVeApx+vhlJ9WdOXDD9AZjsgbZDYvk+MX0lj8jvnS8jidDmAr j6jQ9qm2Ak7cUtZnz9hQKlDakqzNX8TsS7B91QV5nrJxwGJHCeqry066A4Sxmf4T mkNPfUfaBh1eBSaLzX+kaSMyFqNBeBopQNsH72zGKoYCYIJJxoOLBZbKuypJSVyf e0DDge2doJSwHg== =Ti7k -----END PGP SIGNATURE----- Merge tag 'generic-ticket-spinlocks-v6' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux into asm-generic asm-generic: New generic ticket-based spinlock This contains a new ticket-based spinlock that uses only generic atomics and doesn't require as much from the memory system as qspinlock does in order to be fair. It also includes a bit of documentation about the qspinlock and qrwlock fairness requirements. This will soon be used by a handful of architectures that don't meet the qspinlock requirements. * tag 'generic-ticket-spinlocks-v6' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux: csky: Move to generic ticket-spinlock RISC-V: Move to queued RW locks RISC-V: Move to generic spinlocks openrisc: Move to ticket-spinlock asm-generic: qrwlock: Document the spinlock fairness requirements asm-generic: qspinlock: Indicate the use of mixed-size atomics asm-generic: ticket-lock: New generic ticket-based spinlock
This commit is contained in:
Arnd Bergmann
commit
03a679a1a4
15 changed files with 147 additions and 321 deletions
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@ -3,7 +3,10 @@ generic-y += asm-offsets.h
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generic-y += extable.h
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generic-y += gpio.h
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generic-y += kvm_para.h
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generic-y += spinlock.h
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generic-y += spinlock_types.h
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generic-y += qrwlock.h
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generic-y += qrwlock_types.h
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generic-y += parport.h
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generic-y += user.h
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generic-y += vmlinux.lds.h
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@ -1,89 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_SPINLOCK_H
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#define __ASM_CSKY_SPINLOCK_H
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#include <linux/spinlock_types.h>
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#include <asm/barrier.h>
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/*
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* Ticket-based spin-locking.
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*/
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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arch_spinlock_t lockval;
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u32 ticket_next = 1 << TICKET_NEXT;
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u32 *p = &lock->lock;
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u32 tmp;
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asm volatile (
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"1: ldex.w %0, (%2) \n"
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" mov %1, %0 \n"
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" add %0, %3 \n"
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" stex.w %0, (%2) \n"
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" bez %0, 1b \n"
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: "=&r" (tmp), "=&r" (lockval)
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: "r"(p), "r"(ticket_next)
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: "cc");
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while (lockval.tickets.next != lockval.tickets.owner)
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lockval.tickets.owner = READ_ONCE(lock->tickets.owner);
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smp_mb();
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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u32 tmp, contended, res;
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u32 ticket_next = 1 << TICKET_NEXT;
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u32 *p = &lock->lock;
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do {
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asm volatile (
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" ldex.w %0, (%3) \n"
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" movi %2, 1 \n"
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" rotli %1, %0, 16 \n"
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" cmpne %1, %0 \n"
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" bt 1f \n"
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" movi %2, 0 \n"
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" add %0, %0, %4 \n"
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" stex.w %0, (%3) \n"
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"1: \n"
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: "=&r" (res), "=&r" (tmp), "=&r" (contended)
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: "r"(p), "r"(ticket_next)
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: "cc");
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} while (!res);
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if (!contended)
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smp_mb();
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return !contended;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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WRITE_ONCE(lock->tickets.owner, lock->tickets.owner + 1);
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}
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static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
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{
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return lock.tickets.owner == lock.tickets.next;
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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return !arch_spin_value_unlocked(READ_ONCE(*lock));
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}
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static inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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struct __raw_tickets tickets = READ_ONCE(lock->tickets);
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return (tickets.next - tickets.owner) > 1;
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}
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#define arch_spin_is_contended arch_spin_is_contended
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#include <asm/qrwlock.h>
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#endif /* __ASM_CSKY_SPINLOCK_H */
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_CSKY_SPINLOCK_TYPES_H
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#define __ASM_CSKY_SPINLOCK_TYPES_H
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#ifndef __LINUX_SPINLOCK_TYPES_RAW_H
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# error "please don't include this file directly"
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#endif
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#define TICKET_NEXT 16
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typedef struct {
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union {
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u32 lock;
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struct __raw_tickets {
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/* little endian */
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u16 owner;
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u16 next;
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} tickets;
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};
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} arch_spinlock_t;
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#define __ARCH_SPIN_LOCK_UNLOCKED { { 0 } }
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#include <asm-generic/qrwlock_types.h>
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#endif /* __ASM_CSKY_SPINLOCK_TYPES_H */
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@ -30,7 +30,6 @@ config OPENRISC
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select HAVE_DEBUG_STACKOVERFLOW
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select OR1K_PIC
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select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_USE_QUEUED_RWLOCKS
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select OMPIC if SMP
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select ARCH_WANT_FRAME_POINTERS
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@ -1,9 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0
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generic-y += extable.h
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generic-y += kvm_para.h
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generic-y += mcs_spinlock.h
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generic-y += qspinlock_types.h
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generic-y += qspinlock.h
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generic-y += spinlock_types.h
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generic-y += spinlock.h
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generic-y += qrwlock_types.h
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generic-y += qrwlock.h
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generic-y += user.h
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@ -1,27 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* et al.
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*/
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#ifndef __ASM_OPENRISC_SPINLOCK_H
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#define __ASM_OPENRISC_SPINLOCK_H
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#include <asm/qspinlock.h>
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#include <asm/qrwlock.h>
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif
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@ -1,7 +0,0 @@
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#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
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#define _ASM_OPENRISC_SPINLOCK_TYPES_H
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#include <asm/qspinlock_types.h>
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#include <asm/qrwlock_types.h>
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#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
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@ -39,6 +39,7 @@ config RISCV
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select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU
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select ARCH_SUPPORTS_HUGETLBFS if MMU
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select ARCH_USE_MEMTEST
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
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select ARCH_WANT_FRAME_POINTERS
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select ARCH_WANT_GENERAL_HUGETLB
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@ -3,5 +3,9 @@ generic-y += early_ioremap.h
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generic-y += flat.h
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generic-y += kvm_para.h
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generic-y += parport.h
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generic-y += spinlock.h
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generic-y += spinlock_types.h
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generic-y += qrwlock.h
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generic-y += qrwlock_types.h
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generic-y += user.h
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generic-y += vmlinux.lds.h
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@ -1,135 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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* Copyright (C) 2017 SiFive
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*/
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#ifndef _ASM_RISCV_SPINLOCK_H
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#define _ASM_RISCV_SPINLOCK_H
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#include <linux/kernel.h>
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#include <asm/current.h>
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#include <asm/fence.h>
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/*
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* Simple spin lock operations. These provide no fairness guarantees.
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*/
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/* FIXME: Replace this with a ticket lock, like MIPS. */
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#define arch_spin_is_locked(x) (READ_ONCE((x)->lock) != 0)
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_store_release(&lock->lock, 0);
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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int tmp = 1, busy;
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__asm__ __volatile__ (
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" amoswap.w %0, %2, %1\n"
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RISCV_ACQUIRE_BARRIER
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: "=r" (busy), "+A" (lock->lock)
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: "r" (tmp)
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: "memory");
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return !busy;
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}
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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while (1) {
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if (arch_spin_is_locked(lock))
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continue;
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if (arch_spin_trylock(lock))
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break;
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}
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}
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/***********************************************************/
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static inline void arch_read_lock(arch_rwlock_t *lock)
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{
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int tmp;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bltz %1, 1b\n"
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" addi %1, %1, 1\n"
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" sc.w %1, %1, %0\n"
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" bnez %1, 1b\n"
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RISCV_ACQUIRE_BARRIER
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: "+A" (lock->lock), "=&r" (tmp)
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:: "memory");
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}
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static inline void arch_write_lock(arch_rwlock_t *lock)
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{
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int tmp;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bnez %1, 1b\n"
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" li %1, -1\n"
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" sc.w %1, %1, %0\n"
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" bnez %1, 1b\n"
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RISCV_ACQUIRE_BARRIER
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: "+A" (lock->lock), "=&r" (tmp)
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:: "memory");
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}
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static inline int arch_read_trylock(arch_rwlock_t *lock)
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{
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int busy;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bltz %1, 1f\n"
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" addi %1, %1, 1\n"
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" sc.w %1, %1, %0\n"
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" bnez %1, 1b\n"
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RISCV_ACQUIRE_BARRIER
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"1:\n"
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: "+A" (lock->lock), "=&r" (busy)
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:: "memory");
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return !busy;
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}
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static inline int arch_write_trylock(arch_rwlock_t *lock)
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{
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int busy;
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__asm__ __volatile__(
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"1: lr.w %1, %0\n"
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" bnez %1, 1f\n"
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" li %1, -1\n"
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" sc.w %1, %1, %0\n"
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" bnez %1, 1b\n"
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RISCV_ACQUIRE_BARRIER
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"1:\n"
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: "+A" (lock->lock), "=&r" (busy)
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:: "memory");
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return !busy;
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}
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static inline void arch_read_unlock(arch_rwlock_t *lock)
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{
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__asm__ __volatile__(
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RISCV_RELEASE_BARRIER
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" amoadd.w x0, %1, %0\n"
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: "+A" (lock->lock)
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: "r" (-1)
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: "memory");
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}
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static inline void arch_write_unlock(arch_rwlock_t *lock)
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{
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smp_store_release(&lock->lock, 0);
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}
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#endif /* _ASM_RISCV_SPINLOCK_H */
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@ -1,25 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_SPINLOCK_TYPES_H
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#define _ASM_RISCV_SPINLOCK_TYPES_H
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#ifndef __LINUX_SPINLOCK_TYPES_RAW_H
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# error "please don't include this file directly"
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#endif
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typedef struct {
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volatile unsigned int lock;
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} arch_spinlock_t;
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#define __ARCH_SPIN_LOCK_UNLOCKED { 0 }
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typedef struct {
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volatile unsigned int lock;
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} arch_rwlock_t;
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#define __ARCH_RW_LOCK_UNLOCKED { 0 }
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#endif /* _ASM_RISCV_SPINLOCK_TYPES_H */
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@ -2,6 +2,10 @@
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/*
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* Queue read/write lock
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*
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* These use generic atomic and locking routines, but depend on a fair spinlock
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* implementation in order to be fair themselves. The implementation in
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* asm-generic/spinlock.h meets these requirements.
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*
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* (C) Copyright 2013-2014 Hewlett-Packard Development Company, L.P.
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*
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* Authors: Waiman Long <waiman.long@hp.com>
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|
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@ -2,6 +2,35 @@
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/*
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* Queued spinlock
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*
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* A 'generic' spinlock implementation that is based on MCS locks. For an
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* architecture that's looking for a 'generic' spinlock, please first consider
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* ticket-lock.h and only come looking here when you've considered all the
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* constraints below and can show your hardware does actually perform better
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* with qspinlock.
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*
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* qspinlock relies on atomic_*_release()/atomic_*_acquire() to be RCsc (or no
|
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* weaker than RCtso if you're power), where regular code only expects atomic_t
|
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* to be RCpc.
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*
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* qspinlock relies on a far greater (compared to asm-generic/spinlock.h) set
|
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* of atomic operations to behave well together, please audit them carefully to
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* ensure they all have forward progress. Many atomic operations may default to
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* cmpxchg() loops which will not have good forward progress properties on
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* LL/SC architectures.
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*
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* One notable example is atomic_fetch_or_acquire(), which x86 cannot (cheaply)
|
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* do. Carefully read the patches that introduced
|
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* queued_fetch_set_pending_acquire().
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*
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* qspinlock also heavily relies on mixed size atomic operations, in specific
|
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* it requires architectures to have xchg16; something which many LL/SC
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* architectures need to implement as a 32bit and+or in order to satisfy the
|
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* forward progress guarantees mentioned above.
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*
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||||
* Further reading on mixed size atomics that might be relevant:
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*
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||||
* http://www.cl.cam.ac.uk/~pes20/popl17/mixed-size.pdf
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||||
*
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* (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.
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* (C) Copyright 2015 Hewlett-Packard Enterprise Development LP
|
||||
*
|
||||
|
|
|
|||
|
|
@ -1,12 +1,92 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
/*
|
||||
* 'Generic' ticket-lock implementation.
|
||||
*
|
||||
* It relies on atomic_fetch_add() having well defined forward progress
|
||||
* guarantees under contention. If your architecture cannot provide this, stick
|
||||
* to a test-and-set lock.
|
||||
*
|
||||
* It also relies on atomic_fetch_add() being safe vs smp_store_release() on a
|
||||
* sub-word of the value. This is generally true for anything LL/SC although
|
||||
* you'd be hard pressed to find anything useful in architecture specifications
|
||||
* about this. If your architecture cannot do this you might be better off with
|
||||
* a test-and-set.
|
||||
*
|
||||
* It further assumes atomic_*_release() + atomic_*_acquire() is RCpc and hence
|
||||
* uses atomic_fetch_add() which is RCsc to create an RCsc hot path, along with
|
||||
* a full fence after the spin to upgrade the otherwise-RCpc
|
||||
* atomic_cond_read_acquire().
|
||||
*
|
||||
* The implementation uses smp_cond_load_acquire() to spin, so if the
|
||||
* architecture has WFE like instructions to sleep instead of poll for word
|
||||
* modifications be sure to implement that (see ARM64 for example).
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __ASM_GENERIC_SPINLOCK_H
|
||||
#define __ASM_GENERIC_SPINLOCK_H
|
||||
/*
|
||||
* You need to implement asm/spinlock.h for SMP support. The generic
|
||||
* version does not handle SMP.
|
||||
*/
|
||||
#ifdef CONFIG_SMP
|
||||
#error need an architecture specific asm/spinlock.h
|
||||
#endif
|
||||
|
||||
#include <linux/atomic.h>
|
||||
#include <asm-generic/spinlock_types.h>
|
||||
|
||||
static __always_inline void arch_spin_lock(arch_spinlock_t *lock)
|
||||
{
|
||||
u32 val = atomic_fetch_add(1<<16, lock);
|
||||
u16 ticket = val >> 16;
|
||||
|
||||
if (ticket == (u16)val)
|
||||
return;
|
||||
|
||||
/*
|
||||
* atomic_cond_read_acquire() is RCpc, but rather than defining a
|
||||
* custom cond_read_rcsc() here we just emit a full fence. We only
|
||||
* need the prior reads before subsequent writes ordering from
|
||||
* smb_mb(), but as atomic_cond_read_acquire() just emits reads and we
|
||||
* have no outstanding writes due to the atomic_fetch_add() the extra
|
||||
* orderings are free.
|
||||
*/
|
||||
atomic_cond_read_acquire(lock, ticket == (u16)VAL);
|
||||
smp_mb();
|
||||
}
|
||||
|
||||
static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock)
|
||||
{
|
||||
u32 old = atomic_read(lock);
|
||||
|
||||
if ((old >> 16) != (old & 0xffff))
|
||||
return false;
|
||||
|
||||
return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */
|
||||
}
|
||||
|
||||
static __always_inline void arch_spin_unlock(arch_spinlock_t *lock)
|
||||
{
|
||||
u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
|
||||
u32 val = atomic_read(lock);
|
||||
|
||||
smp_store_release(ptr, (u16)val + 1);
|
||||
}
|
||||
|
||||
static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock)
|
||||
{
|
||||
u32 val = atomic_read(lock);
|
||||
|
||||
return ((val >> 16) != (val & 0xffff));
|
||||
}
|
||||
|
||||
static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock)
|
||||
{
|
||||
u32 val = atomic_read(lock);
|
||||
|
||||
return (s16)((val >> 16) - (val & 0xffff)) > 1;
|
||||
}
|
||||
|
||||
static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock)
|
||||
{
|
||||
return !arch_spin_is_locked(&lock);
|
||||
}
|
||||
|
||||
#include <asm/qrwlock.h>
|
||||
|
||||
#endif /* __ASM_GENERIC_SPINLOCK_H */
|
||||
|
|
|
|||
17
include/asm-generic/spinlock_types.h
Normal file
17
include/asm-generic/spinlock_types.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef __ASM_GENERIC_SPINLOCK_TYPES_H
|
||||
#define __ASM_GENERIC_SPINLOCK_TYPES_H
|
||||
|
||||
#include <linux/types.h>
|
||||
typedef atomic_t arch_spinlock_t;
|
||||
|
||||
/*
|
||||
* qrwlock_types depends on arch_spinlock_t, so we must typedef that before the
|
||||
* include.
|
||||
*/
|
||||
#include <asm/qrwlock_types.h>
|
||||
|
||||
#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0)
|
||||
|
||||
#endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */
|
||||
Loading…
Reference in a new issue