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mtd: rawnand: atmel: Convert the driver to exec_op()
Both SMC and HSMC are converted to exec_op(). Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200720131356.1579073-6-tudor.ambarus@microchip.com
This commit is contained in:
Boris Brezillon
Miquel Raynal
parent
060c931c94
commit
03b3e0c27d
1 changed files with 267 additions and 0 deletions
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@ -202,6 +202,8 @@ struct atmel_nand_controller_ops {
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int (*ecc_init)(struct nand_chip *chip);
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int (*setup_interface)(struct atmel_nand *nand, int csline,
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const struct nand_interface_config *conf);
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int (*exec_op)(struct atmel_nand *nand,
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const struct nand_operation *op, bool check_only);
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};
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struct atmel_nand_controller_caps {
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@ -259,6 +261,7 @@ struct atmel_hsmc_nand_controller {
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struct regmap *io;
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struct atmel_nfc_op op;
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struct completion complete;
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u32 cfg;
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int irq;
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/* Only used when instantiating from legacy DT bindings. */
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@ -638,6 +641,252 @@ static void atmel_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
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writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
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}
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static void atmel_nand_data_in(struct atmel_nand *nand, void *buf,
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unsigned int len, bool force_8bit)
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{
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struct atmel_nand_controller *nc;
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nc = to_nand_controller(nand->base.controller);
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/*
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* If the controller supports DMA, the buffer address is DMA-able and
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* len is long enough to make DMA transfers profitable, let's trigger
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* a DMA transfer. If it fails, fallback to PIO mode.
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*/
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if (nc->dmac && virt_addr_valid(buf) &&
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len >= MIN_DMA_LEN && !force_8bit &&
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!atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
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DMA_FROM_DEVICE))
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return;
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if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
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ioread16_rep(nand->activecs->io.virt, buf, len / 2);
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else
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ioread8_rep(nand->activecs->io.virt, buf, len);
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}
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static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf,
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unsigned int len, bool force_8bit)
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{
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struct atmel_nand_controller *nc;
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nc = to_nand_controller(nand->base.controller);
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/*
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* If the controller supports DMA, the buffer address is DMA-able and
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* len is long enough to make DMA transfers profitable, let's trigger
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* a DMA transfer. If it fails, fallback to PIO mode.
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*/
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if (nc->dmac && virt_addr_valid(buf) &&
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len >= MIN_DMA_LEN && !force_8bit &&
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!atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
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len, DMA_TO_DEVICE))
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return;
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if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit)
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iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
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else
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iowrite8_rep(nand->activecs->io.virt, buf, len);
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}
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static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms)
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{
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if (nand->activecs->rb.type == ATMEL_NAND_NO_RB)
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return nand_soft_waitrdy(&nand->base, timeout_ms);
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return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio,
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timeout_ms);
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}
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static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand,
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unsigned int timeout_ms)
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{
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struct atmel_hsmc_nand_controller *nc;
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u32 status, mask;
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if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB)
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return atmel_nand_waitrdy(nand, timeout_ms);
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nc = to_hsmc_nand_controller(nand->base.controller);
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mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
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return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR,
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status, status & mask,
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10, timeout_ms * 1000);
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}
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static void atmel_nand_select_target(struct atmel_nand *nand,
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unsigned int cs)
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{
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nand->activecs = &nand->cs[cs];
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}
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static void atmel_hsmc_nand_select_target(struct atmel_nand *nand,
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unsigned int cs)
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{
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struct mtd_info *mtd = nand_to_mtd(&nand->base);
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struct atmel_hsmc_nand_controller *nc;
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u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
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ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
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ATMEL_HSMC_NFC_CFG_RSPARE;
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nand->activecs = &nand->cs[cs];
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nc = to_hsmc_nand_controller(nand->base.controller);
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if (nc->cfg == cfg)
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return;
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regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
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ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
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ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
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ATMEL_HSMC_NFC_CFG_RSPARE |
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ATMEL_HSMC_NFC_CFG_WSPARE,
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cfg);
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nc->cfg = cfg;
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}
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static int atmel_smc_nand_exec_instr(struct atmel_nand *nand,
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const struct nand_op_instr *instr)
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{
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struct atmel_nand_controller *nc;
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unsigned int i;
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nc = to_nand_controller(nand->base.controller);
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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writeb(instr->ctx.cmd.opcode,
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nand->activecs->io.virt + nc->caps->cle_offs);
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return 0;
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case NAND_OP_ADDR_INSTR:
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for (i = 0; i < instr->ctx.addr.naddrs; i++)
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writeb(instr->ctx.addr.addrs[i],
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nand->activecs->io.virt + nc->caps->ale_offs);
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return 0;
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case NAND_OP_DATA_IN_INSTR:
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atmel_nand_data_in(nand, instr->ctx.data.buf.in,
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instr->ctx.data.len,
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instr->ctx.data.force_8bit);
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return 0;
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case NAND_OP_DATA_OUT_INSTR:
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atmel_nand_data_out(nand, instr->ctx.data.buf.out,
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instr->ctx.data.len,
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instr->ctx.data.force_8bit);
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return 0;
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case NAND_OP_WAITRDY_INSTR:
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return atmel_nand_waitrdy(nand,
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instr->ctx.waitrdy.timeout_ms);
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default:
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break;
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}
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return -EINVAL;
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}
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static int atmel_smc_nand_exec_op(struct atmel_nand *nand,
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const struct nand_operation *op,
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bool check_only)
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{
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unsigned int i;
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int ret = 0;
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if (check_only)
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return 0;
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atmel_nand_select_target(nand, op->cs);
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gpiod_set_value(nand->activecs->csgpio, 0);
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for (i = 0; i < op->ninstrs; i++) {
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ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]);
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if (ret)
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break;
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}
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gpiod_set_value(nand->activecs->csgpio, 1);
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return ret;
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}
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static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip,
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const struct nand_subop *subop)
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{
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struct atmel_nand *nand = to_atmel_nand(chip);
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struct atmel_hsmc_nand_controller *nc;
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unsigned int i, j;
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nc = to_hsmc_nand_controller(chip->controller);
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nc->op.cs = nand->activecs->id;
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for (i = 0; i < subop->ninstrs; i++) {
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const struct nand_op_instr *instr = &subop->instrs[i];
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if (instr->type == NAND_OP_CMD_INSTR) {
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nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode;
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continue;
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}
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for (j = nand_subop_get_addr_start_off(subop, i);
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j < nand_subop_get_num_addr_cyc(subop, i); j++) {
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nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j];
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nc->op.naddrs++;
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}
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}
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return atmel_nfc_exec_op(nc, true);
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}
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static int atmel_hsmc_exec_rw(struct nand_chip *chip,
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const struct nand_subop *subop)
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{
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const struct nand_op_instr *instr = subop->instrs;
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struct atmel_nand *nand = to_atmel_nand(chip);
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if (instr->type == NAND_OP_DATA_IN_INSTR)
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atmel_nand_data_in(nand, instr->ctx.data.buf.in,
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instr->ctx.data.len,
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instr->ctx.data.force_8bit);
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else
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atmel_nand_data_out(nand, instr->ctx.data.buf.out,
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instr->ctx.data.len,
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instr->ctx.data.force_8bit);
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return 0;
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}
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static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip,
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const struct nand_subop *subop)
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{
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const struct nand_op_instr *instr = subop->instrs;
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struct atmel_nand *nand = to_atmel_nand(chip);
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return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms);
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}
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static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER(
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NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr,
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NAND_OP_PARSER_PAT_CMD_ELEM(true),
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NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5),
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NAND_OP_PARSER_PAT_CMD_ELEM(true)),
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NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
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NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)),
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NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw,
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NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)),
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NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy,
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NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)),
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);
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static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand,
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const struct nand_operation *op,
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bool check_only)
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{
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int ret;
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if (check_only)
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return nand_op_parser_exec_op(&nand->base,
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&atmel_hsmc_op_parser, op, true);
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atmel_hsmc_nand_select_target(nand, op->cs);
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ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op,
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false);
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return ret;
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}
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static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
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bool oob_required)
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{
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@ -904,6 +1153,7 @@ static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
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struct atmel_hsmc_nand_controller *nc;
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int ret;
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atmel_hsmc_nand_select_target(nand, chip->cur_cs);
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nc = to_hsmc_nand_controller(chip->controller);
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atmel_nfc_copy_to_sram(chip, buf, false);
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@ -964,6 +1214,7 @@ static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
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struct atmel_hsmc_nand_controller *nc;
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int ret;
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atmel_hsmc_nand_select_target(nand, chip->cur_cs);
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nc = to_hsmc_nand_controller(chip->controller);
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/*
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@ -1450,6 +1701,18 @@ static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
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return nc->caps->ops->setup_interface(nand, csline, conf);
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}
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static int atmel_nand_exec_op(struct nand_chip *chip,
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const struct nand_operation *op,
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bool check_only)
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{
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struct atmel_nand *nand = to_atmel_nand(chip);
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struct atmel_nand_controller *nc;
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nc = to_nand_controller(nand->base.controller);
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return nc->caps->ops->exec_op(nand, op, check_only);
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}
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static void atmel_nand_init(struct atmel_nand_controller *nc,
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struct atmel_nand *nand)
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{
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@ -1940,6 +2203,7 @@ static int atmel_nand_attach_chip(struct nand_chip *chip)
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static const struct nand_controller_ops atmel_nand_controller_ops = {
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.attach_chip = atmel_nand_attach_chip,
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.setup_interface = atmel_nand_setup_interface,
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.exec_op = atmel_nand_exec_op,
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};
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static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
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@ -2307,6 +2571,7 @@ static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
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.ecc_init = atmel_hsmc_nand_ecc_init,
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.nand_init = atmel_hsmc_nand_init,
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.setup_interface = atmel_hsmc_nand_setup_interface,
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.exec_op = atmel_hsmc_nand_exec_op,
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};
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static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
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@ -2373,6 +2638,7 @@ static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
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.remove = atmel_smc_nand_controller_remove,
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.ecc_init = atmel_nand_ecc_init,
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.nand_init = atmel_smc_nand_init,
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.exec_op = atmel_smc_nand_exec_op,
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};
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static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
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@ -2388,6 +2654,7 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
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.ecc_init = atmel_nand_ecc_init,
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.nand_init = atmel_smc_nand_init,
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.setup_interface = atmel_smc_nand_setup_interface,
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.exec_op = atmel_smc_nand_exec_op,
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};
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static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
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