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drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval
PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
so don't set that.
Fixes: ad8ebf1221
("drm/i915/gt: Ensure memory quiesced before invalidation")
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.8+
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Cc: Mark Janes <mark.janes@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Acked-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230926142401.25687-1-nirmoy.das@intel.com
This commit is contained in:
parent
1e975e591a
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03d681412b
1 changed files with 10 additions and 1 deletions
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@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
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if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
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bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
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bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
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/*
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* L3 fabric flush is needed for AUX CCS invalidation
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* which happens as part of pipe-control so we can
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* ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
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* deals with Protected Memory which is not needed for
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* AUX CCS invalidation and lead to unwanted side effects.
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*/
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if (mode & EMIT_FLUSH)
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bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
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bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
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bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
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bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
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/* Wa_1409600907:tgl,adl-p */
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