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cxl: Enable NORST bit in PSL_DEBUG register for PSL9 

We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.

Signed-off-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Vaibhav Jain 2018-02-09 09:39:16 +05:30 committed by Michael Ellerman
parent 1ff3b40401
commit 03ebb419b8
1 changed files with 6 additions and 2 deletions
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8
drivers/misc/cxl/pci.c
View File

@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
if (cxl_is_power9_dd1()) {
/* Disabling deadlock counter CAR */
cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
} else
cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
/* Enable NORST */
cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
} else {
/* Enable NORST and DD2 features */
cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
}
return 0;
}