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ARM: DT updates for v4.8 

Device tree contents continue to be the largest branches we submit. This
 time around, some of the contents worth pointing out is:
 
 - New SoC platforms:
   - Freescale i.MX 7Solo
   - Broadcom BCM23550
   - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
   - Hisilicon HI3519
   - Renesas R8A7792
 
 Some of the other delta that is sticking out, line-count wise:
  - Exynos moves of IP blocks under an SoC bus, which causes a large delta due
    to indentation changes
  - A new Tegra K1 board: Apalis
  - A bunch of small updates to many Allwinner platforms; new hardware support,
    some cleanup, etc.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "Device tree contents continue to be the largest branches we submit.
  This time around, some of the contents worth pointing out is:

  New SoC platforms:
   - Freescale i.MX 7Solo
   - Broadcom BCM23550
   - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
   - Hisilicon HI3519
   - Renesas R8A7792

  Some of the other delta that is sticking out, line-count wise:
   - Exynos moves of IP blocks under an SoC bus, which causes a large
     delta due to indentation changes
   - a new Tegra K1 board: Apalis
   - a bunch of small updates to many Allwinner platforms; new hardware
     support, some cleanup, etc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits)
  ARM: dts: sun8i: Add dts file for inet86dz board
  ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet
  ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts
  ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04
  ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply
  ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi
  ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts
  ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts
  ARM: dts: sun5i: reference-design-tablet: Remove mention of q8
  ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc
  ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi
  ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts
  ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi
  ARM: dts: at91: Don't build unnecessary dtbs
  ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions
  ARM: dts: at91: at91sam9g25ek: fix isi endpoint node
  ARM: dts: at91: move isi definition to at91sam9g25ek
  ARM: dts: at91: fix i2c-gpio node name
  ARM: dts: at91: vinco: fix regulator name
  ARM: dts: at91: ariag25 : fix onewire node
  ...
This commit is contained in:
Linus Torvalds 2016-08-01 18:37:45 -04:00
parent 43a0a98aa8 d95eabc7b8
commit 043248cd4e
413 changed files with 21177 additions and 7105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
View File

@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
The enable method is specified by defining the following required
properties in the "cpus" device tree node:
properties in the "cpu" device tree node:
- enable-method = "brcm,bcm11351-cpu-method";
- secondary-boot-reg = <...>;
@ -19,8 +19,6 @@ Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
cpu0: cpu@0 {
device_type = "cpu";
@ -32,5 +30,7 @@ Example:
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
};
};

36
Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt Normal file
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@ -0,0 +1,36 @@
Broadcom Kona Family CPU Enable Method
--------------------------------------
This binding defines the enable method used for starting secondary
CPUs in the following Broadcom SoCs:
BCM23550
The enable method is specified by defining the following required
properties in the "cpu" device tree node:
- enable-method = "brcm,bcm23550";
- secondary-boot-reg = <...>;
The secondary-boot-reg property is a u32 value that specifies the
physical address of the register used to request the ROM holding pen
code release a secondary CPU. The value written to the register is
formed by encoding the target CPU id into the low bits of the
physical start address it should jump to.
Example:
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x3500417c>;
};
};

15
Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt Normal file
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@ -0,0 +1,15 @@
Broadcom BCM23550 device tree bindings
--------------------------------------
This document describes the device tree bindings for boards with the BCM23550
SoC.
Required root node property:
- compatible: brcm,bcm23550
Example:
/ {
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
[...]
}

3
Documentation/devicetree/bindings/arm/cpus.txt
View File

@ -193,6 +193,8 @@ nodes to be present and contain the properties described below.
"allwinner,sun6i-a31"
"allwinner,sun8i-a23"
"arm,realview-smp"
"brcm,bcm11351-cpu-method"
"brcm,bcm23550"
"brcm,bcm-nsp-smp"
"brcm,brahma-b15"
"marvell,armada-375-smp"
@ -204,6 +206,7 @@ nodes to be present and contain the properties described below.
"qcom,gcc-msm8660"
"qcom,kpss-acc-v1"
"qcom,kpss-acc-v2"
"renesas,apmu"
"rockchip,rk3036-smp"
"rockchip,rk3066-smp"
"ste,dbx500-smp"

14
Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt Normal file
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@ -0,0 +1,14 @@
* Hisilicon Hi3519 System Controller Block
This bindings use the following binding:
Documentation/devicetree/bindings/mfd/syscon.txt
Required properties:
- compatible: "hisilicon,hi3519-sysctrl".
- reg: the register region of this block
Examples:
sysctrl: system-controller@12010000 {
compatible = "hisilicon,hi3519-sysctrl", "syscon";
reg = <0x12010000 0x1000>;
};

8
Documentation/devicetree/bindings/arm/olimex.txt
View File

@ -1,5 +1,9 @@
Olimex i.MX Platforms Device Tree Bindings
------------------------------------------
Olimex Device Tree Bindings
---------------------------
SAM9-L9260 Board
Required root node properties:
- compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
i.MX23 Olinuxino Low Cost Board
Required root node properties:

3
Documentation/devicetree/bindings/arm/rockchip.txt
View File

@ -107,6 +107,9 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
- Rockchip RK3229 Evaluation board:
- compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";

1
Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
View File

@ -47,6 +47,7 @@ Required root node properties:
- "hardkernel,odroid-u3" - for Exynos4412-based Hardkernel Odroid U3.
- "hardkernel,odroid-x" - for Exynos4412-based Hardkernel Odroid X.
- "hardkernel,odroid-x2" - for Exynos4412-based Hardkernel Odroid X2.
- "hardkernel,odroid-xu" - for Exynos5410-based Hardkernel Odroid XU.
- "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
- "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
Odroid XU3 Lite board.

2
Documentation/devicetree/bindings/arm/shmobile.txt
View File

@ -39,6 +39,8 @@ Boards:
compatible = "renesas,ape6evm", "renesas,r8a73a4"
- Atmark Techno Armadillo-800 EVA
compatible = "renesas,armadillo800eva"
- Blanche (RTP0RC7792SEB00010S)
compatible = "renesas,blanche", "renesas,r8a7792"
- BOCK-W
compatible = "renesas,bockw", "renesas,r8a7778"
- Genmai (RTK772100BC00000BR)

4
Documentation/devicetree/bindings/arm/tegra.txt
View File

@ -32,7 +32,11 @@ board-specific compatible values:
nvidia,whistler
toradex,apalis_t30
toradex,apalis_t30-eval
toradex,apalis-tk1
toradex,apalis-tk1-eval
toradex,colibri_t20-512
toradex,colibri_t30
toradex,colibri_t30-eval-v3
toradex,iris
Trusted Foundations

4
Documentation/devicetree/bindings/dma/ti-edma.txt
View File

@ -15,7 +15,7 @@ Required properties:
- reg: Memory map of eDMA CC
- reg-names: "edma3_cc"
- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT.
- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
- ti,tptcs: List of TPTCs associated with the eDMA in the following form:
<&tptc_phandle TC_priority_number>. The highest priority is 0.
@ -48,7 +48,7 @@ edma: edma@49000000 {
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;

28
Documentation/devicetree/bindings/firmware/qcom,scm.txt Normal file
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@ -0,0 +1,28 @@
QCOM Secure Channel Manager (SCM)
Qualcomm processors include an interface to communicate to the secure firmware.
This interface allows for clients to request different types of actions. These
can include CPU power up/down, HDCP requests, loading of firmware, and other
assorted actions.
Required properties:
- compatible: must contain one of the following:
* "qcom,scm-apq8064" for APQ8064 platforms
* "qcom,scm-msm8660" for MSM8660 platforms
* "qcom,scm-msm8690" for MSM8690 platforms
* "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
- clocks: One to three clocks may be required based on compatible.
* Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
* Core, iface, and bus clocks required for "qcom,scm"
- clock-names: Must contain "core" for the core clock, "iface" for the interface
clock and "bus" for the bus clock per the requirements of the compatible.
Example for MSM8916:
firmware {
scm {
compatible = "qcom,scm";
clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
};
};

12
Documentation/devicetree/bindings/iio/adc/at91_adc.txt
View File

@ -59,28 +59,24 @@ adc0: adc@fffb0000 {
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "lowres";
trigger@0 {
reg = <0>;
trigger0 {
trigger-name = "external-rising";
trigger-value = <0x1>;
trigger-external;
};
trigger@1 {
reg = <1>;
trigger1 {
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
};
trigger@2 {
reg = <2>;
trigger2 {
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
};
trigger@3 {
reg = <3>;
trigger3 {
trigger-name = "continuous";
trigger-value = <0x6>;
};

2
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
View File

@ -124,7 +124,7 @@ For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
- functions: "usb3-ss", "sata"
For Tegra210, the list of valid PHY nodes is given below:
- utmi: utmi-0, utmi-1, utmi-2, utmi-3
- usb2: usb2-0, usb2-1, usb2-2, usb2-3
- functions: "snps", "xusb", "uart"
- hsic: hsic-0, hsic-1
- functions: "snps", "xusb"

31
Documentation/devicetree/bindings/power/renesas,apmu.txt Normal file
View File

@ -0,0 +1,31 @@
DT bindings for the Renesas Advanced Power Management Unit
Renesas R-Car line of SoCs utilize one or more APMU hardware units
for CPU core power domain control including SMP boot and CPU Hotplug.
Required properties:
- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
Examples with soctypes are:
- "renesas,r8a7790-apmu" (R-Car H2)
- "renesas,r8a7791-apmu" (R-Car M2-W)
- "renesas,r8a7792-apmu" (R-Car V2H)
- "renesas,r8a7793-apmu" (R-Car M2-N)
- "renesas,r8a7794-apmu" (R-Car E2)
- reg: Base address and length of the I/O registers used by the APMU.
- cpus: This node contains a list of CPU cores, which should match the order
of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
Management Unit section of the device's datasheet.
Example:
This shows the r8a7791 APMU that can control CPU0 and CPU1.
apmu@e6152000 {
compatible = "renesas,r8a7791-apmu", "renesas,apmu";
reg = <0 0xe6152000 0 0x188>;
cpus = <&cpu0 &cpu1>;
};

38
Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
View File

@ -2,28 +2,48 @@ TI SOC ECAP based APWM controller
Required properties:
- compatible: Must be "ti,<soc>-ecap".
for am33xx - compatible = "ti,am33xx-ecap";
for da850 - compatible = "ti,da850-ecap", "ti,am33xx-ecap";
for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The PWM channel index ranges from 0 to 4. The only third
cell flag supported by this binding is PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.
Optional properties:
- ti,hwmods: Name of the hwmod associated to the ECAP:
"ecap<x>", <x> being the 0-based instance number from the HW spec
- clocks: Handle to the ECAP's functional clock.
- clock-names: Must be set to "fck".
Example:
ecap0: ecap@0 { /* ECAP on am33xx */
compatible = "ti,am33xx-ecap";
ecap0: ecap@48300100 { /* ECAP on am33xx */
compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
};
ecap0: ecap@48300100 { /* ECAP on am4372 */
compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
ti,hwmods = "ecap0";
clocks = <&l4ls_gclk>;
clock-names = "fck";
};
ecap0: ecap@0 { /* ECAP on da850 */
compatible = "ti,da850-ecap", "ti,am33xx-ecap";
ecap0: ecap@1f06000 { /* ECAP on da850 */
compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
reg = <0x1f06000 0x80>;
};
ecap0: ecap@4843e100 {
compatible = "ti,dra746-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x4843e100 0x80>;
clocks = <&l4_root_clk_div>;
clock-names = "fck";
};

38
Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
View File

@ -2,28 +2,48 @@ TI SOC EHRPWM based PWM controller
Required properties:
- compatible: Must be "ti,<soc>-ehrpwm".
for am33xx - compatible = "ti,am33xx-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
- #pwm-cells: should be 3. See pwm.txt in this directory for a description of
the cells format. The only third cell flag supported by this binding is
PWM_POLARITY_INVERTED.
- reg: physical base address and size of the registers map.
Optional properties:
- ti,hwmods: Name of the hwmod associated to the EHRPWM:
"ehrpwm<x>", <x> being the 0-based instance number from the HW spec
- clocks: Handle to the PWM's time-base and functional clock.
- clock-names: Must be set to "tbclk" and "fck".
Example:
ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */
compatible = "ti,am33xx-ehrpwm";
ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x100>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
};
ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
ti,hwmods = "ehrpwm0";
};
ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */
compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
reg = <0x1f00000 0x2000>;
};
ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x4843e200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
clock-names = "tbclk", "fck";
};

33
Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
View File

@ -1,7 +1,11 @@
TI SOC based PWM Subsystem
Required properties:
- compatible: Must be "ti,am33xx-pwmss";
- compatible: Must be "ti,<soc>-pwmss".
for am33xx - compatible = "ti,am33xx-pwmss";
for am4372 - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
- reg: physical base address and size of the registers map.
- address-cells: Specify the number of u32 entries needed in child nodes.
Should set to 1.
@ -16,7 +20,7 @@ Required properties:
Also child nodes should also populated under PWMSS DT node.
Example:
pwmss0: pwmss@48300000 {
epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
@ -29,3 +33,28 @@ pwmss0: pwmss@48300000 {
/* child nodes go here */
};
epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */
/* child nodes go here */
};
epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
reg = <0x4843e000 0x30>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
ranges;
/* child nodes go here */
};

116
Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt Normal file
View File

@ -0,0 +1,116 @@
Qualcomm WCNSS Binding
This binding describes the Qualcomm WCNSS hardware. It consists of control
block and a BT, WiFi and FM radio block, all using SMD as command channels.
- compatible:
Usage: required
Value type: <string>
Definition: must be: "qcom,wcnss",
- qcom,smd-channel:
Usage: required
Value type: <string>
Definition: standard SMD property specifying the SMD channel used for
communication with the WiFi firmware.
Should be "WCNSS_CTRL".
- qcom,mmio:
Usage: required
Value type: <prop-encoded-array>
Definition: reference to a node specifying the wcnss "ccu" and "dxe"
register blocks. The node must be compatible with one of
the following:
"qcom,riva",
"qcom,pronto"
= SUBNODES
The subnodes of the wcnss node are optional and describe the individual blocks in
the WCNSS.
== Bluetooth
The following properties are defined to the bluetooth node:
- compatible:
Usage: required
Value type: <string>
Definition: must be:
"qcom,wcnss-bt"
== WiFi
The following properties are defined to the WiFi node:
- compatible:
Usage: required
Value type: <string>
Definition: must be one of:
"qcom,wcnss-wlan",
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: should specify the "rx" and "tx" interrupts
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: must contain "rx" and "tx"
- qcom,smem-state:
Usage: required
Value type: <prop-encoded-array>
Definition: should reference the tx-enable and tx-rings-empty SMEM states
- qcom,smem-state-names:
Usage: required
Value type: <stringlist>
Definition: must contain "tx-enable" and "tx-rings-empty"
= EXAMPLE
The following example represents a SMD node, with one edge representing the
"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks
described; as found on the 8974 platform.
smd {
compatible = "qcom,smd";
pronto-edge {
interrupts = <0 142 1>;
qcom,ipc = <&apcs 8 17>;
qcom,smd-edge = <6>;
wcnss {
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
#address-cells = <1>;
#size-cells = <1>;
qcom,mmio = <&pronto>;
bt {
compatible = "qcom,wcnss-bt";
};
wlan {
compatible = "qcom,wcnss-wlan";
interrupts = <0 145 0>, <0 146 0>;
interrupt-names = "tx", "rx";
qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>;
qcom,smem-state-names = "tx-enable", "tx-rings-empty";
};
};
};
};
soc {
pronto: pronto {
compatible = "qcom,pronto";
reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
};
};

14
Documentation/devicetree/bindings/usb/atmel-usb.txt
View File

@ -113,13 +113,13 @@ usb2: gadget@fff78000 {
clock-names = "hclk", "pclk";
atmel,vbus-gpio = <&pioB 19 0>;
ep0 {
ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep1 {
ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -127,7 +127,7 @@ usb2: gadget@fff78000 {
atmel,can-isoc;
};
ep2 {
ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -135,21 +135,21 @@ usb2: gadget@fff78000 {
atmel,can-isoc;
};
ep3 {
ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep4 {
ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep5 {
ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -157,7 +157,7 @@ usb2: gadget@fff78000 {
atmel,can-isoc;
};
ep6 {
ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;

8
Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
View File

@ -104,10 +104,10 @@ Example:
nvidia,xusb-padctl = <&padctl>;
phys = <&{/padctl@0,7009f000/pads/usb2/usb2-1}>, /* mini-PCIe USB */
<&{/padctl@0,7009f000/pads/usb2/usb2-2}>, /* USB A */
<&{/padctl@0,7009f000/pads/pcie/pcie-0}>; /* USB A */
phy-names = "utmi-1", "utmi-2", "usb3-0";
phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
<&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
<&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
phy-names = "usb2-1", "usb2-2", "usb3-0";
avddio-pex-supply = <&vdd_1v05_run>;
dvddio-pex-supply = <&vdd_1v05_run>;

43
arch/arm/boot/dts/Makefile
View File

@ -7,9 +7,10 @@ dtb-$(CONFIG_MACH_ARTPEC6) += \
dtb-$(CONFIG_MACH_ASM9260) += \
alphascale-asm9260-devkit.dtb
# Keep at91 dtb files sorted alphabetically for each SoC
dtb-$(CONFIG_SOC_SAM_V4_V5) += \
dtb-$(CONFIG_SOC_AT91RM9200) += \
at91rm9200ek.dtb \
mpa1600.dtb \
mpa1600.dtb
dtb-$(CONFIG_SOC_AT91SAM9) += \
animeo_ip.dtb \
at91-qil_a9260.dtb \
aks-cdu.dtb \
@ -17,8 +18,10 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \
evk-pro3.dtb \
tny_a9260.dtb \
usb_a9260.dtb \
at91sam9260ek.dtb \
at91sam9261ek.dtb \
at91sam9263ek.dtb \
at91-sam9_l9260.dtb \
tny_a9263.dtb \
usb_a9263.dtb \
at91-foxg20.dtb \
@ -85,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
bcm47094-dlink-dir-885l.dtb \
bcm94708.dtb \
bcm94709.dtb \
bcm953012er.dtb \
bcm953012k.dtb
dtb-$(CONFIG_ARCH_BCM_63XX) += \
bcm963138dvt.dtb
@ -95,8 +99,11 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
bcm958305k.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
bcm28155-ap.dtb \
bcm21664-garnet.dtb
bcm21664-garnet.dtb \
bcm23550-sparrow.dtb
dtb-$(CONFIG_ARCH_BCM_NSP) += \
bcm958525xmc.dtb \
bcm958625hr.dtb \
bcm958625k.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
@ -104,6 +111,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2q-marvell-dmp.dtb
dtb-$(CONFIG_ARCH_BRCMSTB) += \
bcm7445-bcm97445svmb.dtb
dtb-$(CONFIG_ARCH_CLPS711X) += \
ep7211-edb7211.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-enbw-cmc.dtb \
da850-evm.dtb
@ -134,6 +143,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5250-snow-rev5.dtb \
exynos5250-spring.dtb \
exynos5260-xyref5260.dtb \
exynos5410-odroidxu.dtb \
exynos5410-smdk5410.dtb \
exynos5420-arndale-octa.dtb \
exynos5420-peach-pit.dtb \
@ -146,8 +156,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
exynos5800-peach-pi.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
highbank.dtb \
ecx-2000.dtb
@ -155,6 +163,10 @@ dtb-$(CONFIG_ARCH_HIP01) += \
hip01-ca9x2.dtb
dtb-$(CONFIG_ARCH_HIP04) += \
hip04-d01.dtb
dtb-$(CONFIG_ARCH_HISI) += \
hi3519-demb.dtb
dtb-$(CONFIG_ARCH_HIX5HD2) += \
hisi-x5hd2-dkb.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += \
integratorap.dtb \
integratorcp.dtb
@ -356,6 +368,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw54xx.dtb \
imx6q-gw551x.dtb \
imx6q-gw552x.dtb \
imx6q-h100.dtb \
imx6q-hummingboard.dtb \
imx6q-icore-rqs.dtb \
imx6q-marsboard.dtb \
@ -377,6 +390,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-tx6q-1110.dtb \
imx6q-tx6q-11x0-mb7.dtb \
imx6q-udoo.dtb \
imx6q-utilite-pro.dtb \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb \
imx6qp-nitrogen6_max.dtb \
@ -399,9 +413,11 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-mainboard.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-nitrogen7.dtb \
imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb
imx7d-sdb.dtb \
imx7s-colibri-eval-v3.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
ls1021a-twr.dtb
@ -416,7 +432,9 @@ dtb-$(CONFIG_SOC_VF610) += \
dtb-$(CONFIG_ARCH_MXS) += \
imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-sansa.dtb \
imx23-stmp378x_devb.dtb \
imx23-xfi3.dtb \
imx28-apf28.dtb \
imx28-apf28dev.dtb \
imx28-apx4devkit.dtb \
@ -572,7 +590,8 @@ dtb-$(CONFIG_ARCH_PRIMA2) += \
dtb-$(CONFIG_ARCH_OXNAS) += \
wd-mbwe.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8064-arrow-db600c.dtb \
qcom-apq8060-dragonboard.dtb \
qcom-apq8064-arrow-sd-600eval.dtb \
qcom-apq8064-cm-qs600.dtb \
qcom-apq8064-ifc6410.dtb \
qcom-apq8064-sony-xperia-yuga.dtb \
@ -602,6 +621,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3066a-rayeager.dtb \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-evb.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-firefly-beta.dtb \
@ -638,6 +658,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a7790-lager.dtb \
r8a7791-koelsch.dtb \
r8a7791-porter.dtb \
r8a7792-blanche.dtb \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
@ -728,6 +749,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31s-yones-toptech-bs1078-v2.dtb
dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-bananapi.dtb \
sun7i-a20-bananapi-m1-plus.dtb \
sun7i-a20-bananapro.dtb \
sun7i-a20-cubieboard2.dtb \
sun7i-a20-cubietruck.dtb \
@ -752,8 +774,10 @@ dtb-$(CONFIG_MACH_SUN7I) += \
dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-inet86dz.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
sun8i-a23-ippo-q8h-v1.2.dtb \
sun8i-a23-polaroid-mid2407pxe03.dtb \
sun8i-a23-polaroid-mid2809pxe04.dtb \
sun8i-a23-q8-tablet.dtb \
sun8i-a33-et-q8-v1.6.dtb \
@ -763,10 +787,12 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-one.dtb \
sun8i-h3-orangepi-pc.dtb \
sun8i-h3-orangepi-plus.dtb
sun8i-h3-orangepi-plus.dtb \
sun8i-r16-parrot.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb
@ -794,6 +820,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
tegra114-roth.dtb \
tegra114-tn7.dtb
dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
tegra124-apalis-eval.dtb \
tegra124-jetson-tk1.dtb \
tegra124-nyan-big.dtb \
tegra124-nyan-blaze.dtb \

2
arch/arm/boot/dts/aks-cdu.dts
View File

@ -57,7 +57,7 @@
};
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
num-ports = <2>;
status = "okay";
};

12
arch/arm/boot/dts/am335x-bone-common.dtsi
View File

@ -18,6 +18,10 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
chosen {
stdout-path = &uart0;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&user_leds_s0>;
@ -318,7 +322,7 @@
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1325000>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
@ -359,12 +363,8 @@
phy-mode = "mii";
};
&cpsw_emac1 {
phy_id = <&davinci_mdio>, <1>;
phy-mode = "mii";
};
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;

11
arch/arm/boot/dts/am335x-boneblack.dts
View File

@ -33,6 +33,17 @@
status = "okay";
};
&cpu0_opp_table {
/*
* All PG 2.0 silicon may not support 1GHz but some of the early
* BeagleBone Blacks have PG 2.0 silicon which is guaranteed
* to support 1GHz OPP so enable it for PG 2.0 on this board.
*/
oppnitro@1000000000 {
opp-supported-hw = <0x06 0x0100>;
};
};
&am33xx_pinmux {
nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
pinctrl-single,pins = <

2
arch/arm/boot/dts/am335x-evm.dts
View File

@ -640,7 +640,7 @@
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};

2
arch/arm/boot/dts/am335x-evmsk.dts
View File

@ -560,7 +560,7 @@
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
regulator-name = "vdd_mpu";
regulator-min-microvolt = <912500>;
regulator-max-microvolt = <1312500>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};

7
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -206,6 +206,13 @@
gpio-controller;
#gpio-cells = <2>;
};
pca9536: gpio@41 {
compatible = "ti,pca9536";
reg = <0x41>;
gpio-controller;
#gpio-cells = <2>;
};
};
#include "tps65910.dtsi"

126
arch/arm/boot/dts/am33xx.dtsi
View File

@ -45,19 +45,9 @@
device_type = "cpu";
reg = <0>;
/*
* To consider voltage drop between PMIC and SoC,
* tolerance value is reduced to 2% from 4% and
* voltage value is increased as a precaution.
*/
operating-points = <
/* kHz uV */
720000 1285000
600000 1225000
500000 1125000
275000 1125000
>;
voltage-tolerance = <2>; /* 2 percentage */
operating-points-v2 = <&cpu0_opp_table>;
ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
ti,syscon-rev = <&scm_conf 0x600>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
@ -66,6 +56,78 @@
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
/*
* The three following nodes are marked with opp-suspend
* because the can not be enabled simultaneously on a
* single SoC.
*/
opp50@300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000 931000 969000>;
opp-supported-hw = <0x06 0x0010>;
opp-suspend;
};
opp100@275000000 {
opp-hz = /bits/ 64 <275000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0x00FF>;
opp-suspend;
};
opp100@300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0020>;
opp-suspend;
};
opp100@500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0xFFFF>;
};
opp100@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0040>;
};
opp120@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x01 0xFFFF>;
};
opp120@720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x06 0x0080>;
};
oppturbo@720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x01 0xFFFF>;
};
oppturbo@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x06 0x0100>;
};
oppnitro@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1325000 1298500 1351500>;
opp-supported-hw = <0x04 0x0200>;
};
};
pmu {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
@ -187,7 +249,7 @@
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "emda3_mperr",
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
@ -679,20 +741,24 @@
0x48300200 0x48300200 0x80>; /* EHRPWM */
ecap0: ecap@48300100 {
compatible = "ti,am33xx-ecap";
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <31>;
interrupt-names = "ecap0";
ti,hwmods = "ecap0";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am33xx-ehrpwm";
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
ti,hwmods = "ehrpwm0";
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -709,20 +775,24 @@
0x48302200 0x48302200 0x80>; /* EHRPWM */
ecap1: ecap@48302100 {
compatible = "ti,am33xx-ecap";
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <47>;
interrupt-names = "ecap1";
ti,hwmods = "ecap1";
status = "disabled";
};
ehrpwm1: pwm@48302200 {
compatible = "ti,am33xx-ehrpwm";
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
ti,hwmods = "ehrpwm1";
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -739,20 +809,24 @@
0x48304200 0x48304200 0x80>; /* EHRPWM */
ecap2: ecap@48304100 {
compatible = "ti,am33xx-ecap";
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <61>;
interrupt-names = "ecap2";
ti,hwmods = "ecap2";
status = "disabled";
};
ehrpwm2: pwm@48304200 {
compatible = "ti,am33xx-ehrpwm";
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
ti,hwmods = "ehrpwm2";
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};

2
arch/arm/boot/dts/am3517-craneboard.dts
View File

@ -20,7 +20,7 @@
reg = <0x80000000 0x10000000>; /* 256 MB */
};
vbat: fixedregulator@0 {
vbat: fixedregulator {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <5000000>;

111
arch/arm/boot/dts/am4372.dtsi
View File

@ -44,10 +44,49 @@
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>;
ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
ti,syscon-rev = <&scm_conf 0x600>;
clock-latency = <300000>; /* From omap-cpufreq driver */
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp50@300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000 931000 969000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
opp100@600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0xFF 0x04>;
};
opp120@720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0xFF 0x08>;
};
oppturbo@800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0xFF 0x10>;
};
oppnitro@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1325000 1298500 1351500>;
opp-supported-hw = <0xFF 0x20>;
};
};
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
@ -199,7 +238,7 @@
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "emda3_mperr",
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
@ -671,18 +710,24 @@
status = "disabled";
ecap0: ecap@48300100 {
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
ti,hwmods = "ecap0";
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
ti,hwmods = "ehrpwm0";
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -697,18 +742,24 @@
status = "disabled";
ecap1: ecap@48302100 {
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
ti,hwmods = "ecap1";
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm1: pwm@48302200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
ti,hwmods = "ehrpwm1";
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -723,18 +774,24 @@
status = "disabled";
ecap2: ecap@48304100 {
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
compatible = "ti,am4372-ecap",
"ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
ti,hwmods = "ecap2";
clocks = <&l4ls_gclk>;
clock-names = "fck";
status = "disabled";
};
ehrpwm2: pwm@48304200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
ti,hwmods = "ehrpwm2";
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -749,10 +806,13 @@
status = "disabled";
ehrpwm3: pwm@48306200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48306200 0x80>;
ti,hwmods = "ehrpwm3";
clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -767,10 +827,13 @@
status = "disabled";
ehrpwm4: pwm@48308200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48308200 0x80>;
ti,hwmods = "ehrpwm4";
clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -785,10 +848,13 @@
status = "disabled";
ehrpwm5: pwm@4830a200 {
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
compatible = "ti,am4372-ehrpwm",
"ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x4830a200 0x80>;
ti,hwmods = "ehrpwm5";
clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -842,6 +908,13 @@
dma-names = "tx", "rx";
};
rng: rng@48310000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48310000 0x2000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
};
mcasp0: mcasp@48038000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp0";

6
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -897,7 +897,7 @@
pinctrl-0 = <&dss_pins>;
port {
dpi_out: endpoint@0 {
dpi_out: endpoint {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};
@ -975,3 +975,7 @@
clock-names = "ext-clk", "int-clk";
status = "okay";
};
&cpu {
cpu0-supply = <&dcdc2>;
};

1
arch/arm/boot/dts/am437x-idk-evm.dts
View File

@ -382,6 +382,7 @@
};
&mac {
slaves = <1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;

2
arch/arm/boot/dts/am437x-sbc-t43.dts
View File

@ -145,7 +145,7 @@
pinctrl-0 = <&dss_pinctrl_default>;
port {
dpi_lcd_out: endpoint@0 {
dpi_lcd_out: endpoint {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};

2
arch/arm/boot/dts/am43x-epos-evm.dts
View File

@ -754,7 +754,7 @@
pinctrl-0 = <&dss_pins>;
port {
dpi_out: endpoint@0 {
dpi_out: endpoint {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};

8
arch/arm/boot/dts/am43xx-clocks.dtsi
View File

@ -104,6 +104,14 @@
clock-div = <1>;
};
rng_fck: rng_fck {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
clocks = <&sys_clkin_ck>;
clock-mult = <1>;
clock-div = <1>;
};
ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";

2
arch/arm/boot/dts/am57xx-sbc-am57x.dts
View File

@ -128,7 +128,7 @@
vdda_video-supply = <&ldoln_reg>;
port {
dpi_lcd_out: endpoint@0 {
dpi_lcd_out: endpoint {
remote-endpoint = <&lcd_in>;
data-lines = <24>;
};

11
arch/arm/boot/dts/animeo_ip.dts
View File

@ -32,15 +32,6 @@
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
slow_xtal {
clock-frequency = <32768>;
};
@ -114,7 +105,7 @@
};
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
num-ports = <2>;
atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
status = "okay";

16
arch/arm/boot/dts/armada-388-clearfog.dts
View File

@ -239,22 +239,6 @@
status = "okay";
};
mdio@72004 {
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy_dedicated: ethernet-phy@0 {
/*
* Annoyingly, the marvell phy driver
* configures the LED register, rather
* than preserving reset-loaded setting.
* We undo that rubbish here.
*/
marvell,reg-init = <3 16 0 0x101e>;
reg = <0>;
};
};
pinctrl@18000 {
clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
marvell,pins = "mpp46";

11
arch/arm/boot/dts/at91-ariag25.dts
View File

@ -34,15 +34,6 @@
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
@ -178,7 +169,7 @@
};
onewire@0 {
onewire {
compatible = "w1-gpio";
gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";

9
arch/arm/boot/dts/at91-cosino.dtsi
View File

@ -26,15 +26,6 @@
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};

13
arch/arm/boot/dts/at91-foxg20.dts
View File

@ -23,15 +23,6 @@
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <18432000>;
};
slow_xtal {
clock-frequency = <32768>;
};
@ -128,13 +119,13 @@
};
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
num-ports = <2>;
status = "okay";
};
};
i2c@0 {
i2c-gpio-0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
i2c-gpio,delay-us = <5>; /* ~85 kHz */

4
arch/arm/boot/dts/at91-kizbox.dts
View File

@ -54,7 +54,7 @@
};
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
num-ports = <1>;
status = "okay";
};
@ -96,7 +96,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
status = "okay";
rtc: pcf8563@51 {

13
arch/arm/boot/dts/at91-qil_a9260.dts
View File

@ -20,15 +20,6 @@
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
main_clock: clock@0 {
compatible = "atmel,osc", "fixed-clock";
clock-frequency = <12000000>;
};
slow_xtal {
clock-frequency = <32768>;
};
@ -111,7 +102,7 @@
};
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
num-ports = <2>;
status = "okay";
};
@ -187,7 +178,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
status = "okay";
};
};

121
arch/arm/boot/dts/at91-sam9_l9260.dts Normal file
View File

@ -0,0 +1,121 @@
/*
* at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board
*
* Copyright (C) 2016 Raashid Muhammed <raashidmuhammed@zilogic.com>
*
* Licensed under GPLv2 or later.
*/
/dts-v1/;
#include "at91sam9260.dtsi"
/ {
model = "Olimex sam9-l9260";
compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9";
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};
};
ahb {
apb {
mmc0: mmc@fffa8000 {
pinctrl-0 = <
&pinctrl_board_mmc0
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
status = "okay";
slot@1 {
reg = <1>;
bus-width = <4>;
cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>;
wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>;
};
};
macb0: ethernet@fffc4000 {
pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>;
phy-mode = "mii";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
ethernet-phy@1 {
reg = <0x1>;
};
};
spi0: spi@fffc8000 {
cs-gpios = <&pioC 11 0>, <0>, <0>, <0>;
status = "okay";
flash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <15000000>;
reg = <0>;
};
};
dbgu: serial@fffff200 {
status = "okay";
};
pinctrl@fffff400 {
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
<AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH /* CD pin */
AT91_PIOC 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* WP pin */
};
};
};
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt = <1>;
status = "okay";
};
usb0: ohci@500000 {
status = "okay";
};
};
i2c-gpio-0 {
status = "okay";
};
leds {
compatible = "gpio-leds";
pwr_led {
label = "sam9-l9260:yellow:pwr";
gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "cpu0";
};
status_led {
label = "sam9-l9260:green:status";
gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "timer";
};
};
};

41
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -158,56 +158,64 @@
i2c-sda-hold-time-ns = <350>;
status = "okay";
pmic: act8865@5b {
compatible = "active-semi,act8865";
pmic@5b {
compatible = "active-semi,act8945a";
reg = <0x5b>;
active-semi,vsel-high;
active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>;
active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>;
active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>;
active-semi,input-voltage-threshold-microvolt = <6600>;
active-semi,precondition-timeout = <40>;
active-semi,total-timeout = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>;
status = "okay";
regulators {
vdd_1v35_reg: DCDC_REG1 {
vdd_1v35_reg: REG_DCDC1 {
regulator-name = "VDD_1V35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
};
vdd_1v2_reg: DCDC_REG2 {
vdd_1v2_reg: REG_DCDC2 {
regulator-name = "VDD_1V2";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
vdd_3v3_reg: DCDC_REG3 {
vdd_3v3_reg: REG_DCDC3 {
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_fuse_reg: LDO_REG1 {
vdd_fuse_reg: REG_LDO1 {
regulator-name = "VDD_FUSE";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
vdd_3v3_lp_reg: LDO_REG2 {
vdd_3v3_lp_reg: REG_LDO2 {
regulator-name = "VDD_3V3_LP";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_led_reg: LDO_REG3 {
vdd_led_reg: REG_LDO3 {
regulator-name = "VDD_LED";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vdd_sdhc_1v8_reg: LDO_REG4 {
vdd_sdhc_1v8_reg: REG_LDO4 {
regulator-name = "VDD_SDHC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -309,6 +317,21 @@
bias-disable;
};
pinctrl_charger_chglev: charger_chglev {
pinmux = <PIN_PA12__GPIO>;
bias-disable;
};
pinctrl_charger_irq: charger_irq {
pinmux = <PIN_PB13__GPIO>;
bias-disable;
};
pinctrl_charger_lbo: charger_lbo {
pinmux = <PIN_PC8__GPIO>;
bias-pull-up;
};
pinctrl_flx0_default: flx0_default {
pinmux = <PIN_PB28__FLEXCOM0_IO0>,
<PIN_PB29__FLEXCOM0_IO1>;

2
arch/arm/boot/dts/at91-sama5d3_xplained.dts
View File

@ -297,7 +297,7 @@
};
};
vcc_mmc0_reg: fixedregulator@0 {
vcc_mmc0_reg: fixedregulator_mmc0 {
compatible = "regulator-fixed";
gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
regulator-name = "mmc0-card-supply";

11
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
View File

@ -20,8 +20,11 @@
};
clocks {
main_clock: main_clock {
compatible = "atmel,osc", "fixed-clock";
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <12000000>;
};
@ -106,7 +109,7 @@
};
};
vcc_3v3_reg: fixedregulator@0 {
vcc_3v3_reg: fixedregulator_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC 3V3";
regulator-min-microvolt = <3300000>;
@ -115,7 +118,7 @@
regulator-always-on;
};
vcc_mmc0_reg: fixedregulator@1 {
vcc_mmc0_reg: fixedregulator_mmc0 {
compatible = "regulator-fixed";
gpio = <&pioE 15 GPIO_ACTIVE_HIGH>;
regulator-name = "RST_n MCI0";

2
arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
View File

@ -159,7 +159,7 @@
};
};
vcc_mmc1_reg: fixedregulator@2 {
vcc_mmc1_reg: fixedregulator_mmc1 {
compatible = "regulator-fixed";
gpio = <&pioE 17 GPIO_ACTIVE_LOW>;
regulator-name = "VDD MCI1";

4
arch/arm/boot/dts/at91-sama5d4_xplained.dts
View File

@ -252,7 +252,7 @@
};
};
vcc_3v3_reg: fixedregulator@0 {
vcc_3v3_reg: fixedregulator_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC 3V3";
regulator-min-microvolt = <3300000>;
@ -261,7 +261,7 @@
regulator-always-on;
};
vcc_mmc1_reg: fixedregulator@1 {
vcc_mmc1_reg: fixedregulator_mmc1 {
compatible = "regulator-fixed";
gpio = <&pioE 4 GPIO_ACTIVE_LOW>;
regulator-name = "VDD MCI1";

20
arch/arm/boot/dts/at91-sama5d4ek.dts
View File

@ -69,26 +69,6 @@
ahb {
apb {
lcd_bus@f0000000 {
status = "okay";
lcd@f0000000 {
status = "okay";
};
lcdovl1@f0000140 {
status = "okay";
};
lcdovl2@f0000240 {
status = "okay";
};
lcdheo1@f0000340 {
status = "okay";
};
};
adc0: adc@fc034000 {
pinctrl-names = "default";
pinctrl-0 = <

2
arch/arm/boot/dts/at91-vinco.dts
View File

@ -245,7 +245,7 @@
};
vcc_3v3_reg: fixedregulator@0 {
vcc_3v3_reg: fixedregulator_3v3 {
compatible = "regulator-fixed";
regulator-name = "VCC 3V3";
regulator-min-microvolt = <3300000>;

2
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -948,7 +948,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
&pioA 26 GPIO_ACTIVE_HIGH /* scl */

16
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -938,25 +938,21 @@
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres";
trigger@0 {
reg = <0>;
trigger0 {
trigger-name = "timer-counter-0";
trigger-value = <0x1>;
};
trigger@1 {
reg = <1>;
trigger1 {
trigger-name = "timer-counter-1";
trigger-value = <0x3>;
};
trigger@2 {
reg = <2>;
trigger2 {
trigger-name = "timer-counter-2";
trigger-value = <0x5>;
};
trigger@3 {
reg = <3>;
trigger3 {
trigger-name = "external";
trigger-value = <0xd>;
trigger-external;
@ -1007,7 +1003,7 @@
status = "disabled";
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
reg = <0x00500000 0x100000>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
@ -1017,7 +1013,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
&pioA 24 GPIO_ACTIVE_HIGH /* scl */

211
arch/arm/boot/dts/at91sam9260ek.dts Normal file
View File

@ -0,0 +1,211 @@
/*
* Device Tree file for Atmel at91sam9260 Evaluation Kit
*
* Copyright (C) 2016 Atmel,
* 2016 Nicolas Ferre <nicolas.ferre@atmel.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "at91sam9260.dtsi"
/ {
model = "Atmel at91sam9260ek";
compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9";
chosen {
stdout-path = &dbgu;
};
memory {
reg = <0x20000000 0x4000000>;
};
clocks {
slow_xtal {
clock-frequency = <32768>;
};
main_xtal {
clock-frequency = <18432000>;
};
};
ahb {
apb {
usb1: gadget@fffa4000 {
atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
mmc0: mmc@fffa8000 {
pinctrl-0 = <
&pinctrl_board_mmc0_slot1
&pinctrl_mmc0_clk
&pinctrl_mmc0_slot1_cmd_dat0
&pinctrl_mmc0_slot1_dat1_3>;
status = "okay";
slot@1 {
reg = <1>;
bus-width = <4>;
cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
};
};
usart0: serial@fffb0000 {
pinctrl-0 =
<&pinctrl_usart0
&pinctrl_usart0_rts
&pinctrl_usart0_cts
&pinctrl_usart0_dtr_dsr
&pinctrl_usart0_dcd
&pinctrl_usart0_ri>;
status = "okay";
};
usart1: serial@fffb4000 {
status = "okay";
};
ssc0: ssc@fffbc000 {
status = "okay";
pinctrl-0 = <&pinctrl_ssc0_tx>;
};
macb0: ethernet@fffc4000 {
phy-mode = "rmii";
status = "okay";
};
spi0: spi@fffc8000 {
cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
mtd_dataflash@0 {
compatible = "atmel,at45", "atmel,dataflash";
spi-max-frequency = <50000000>;
reg = <1>;
};
};
dbgu: serial@fffff200 {
status = "okay";
};
pinctrl@fffff400 {
board {
pinctrl_board_mmc0_slot1: mmc0_slot1-board {
atmel,pins =
<AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
};
};
shdwc@fffffd10 {
atmel,wakeup-counter = <10>;
atmel,wakeup-rtt-timer;
};
rtc@fffffd20 {
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
status = "okay";
};
watchdog@fffffd40 {
status = "okay";
};
gpbr: syscon@fffffd50 {
status = "okay";
};
};
usb0: ohci@500000 {
num-ports = <2>;
status = "okay";
};
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-on-flash-bbt;
status = "okay";
};
};
gpio_keys {
compatible = "gpio-keys";
btn3 {
label = "Button 3";
gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
linux,code = <0x103>;
gpio-key,wakeup;
};
btn4 {
label = "Button 4";
gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
gpio-key,wakeup;
};
};
i2c-gpio-0 {
status = "okay";
24c512@50 {
compatible = "24c512";
reg = <0x50>;
};
};
leds {
compatible = "gpio-leds";
ds1 {
label = "ds1";
gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
ds5 {
label = "ds5";
gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
};
};
};

2
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -860,7 +860,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c_bitbang>;

2
arch/arm/boot/dts/at91sam9263.dtsi
View File

@ -1019,7 +1019,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
&pioB 5 GPIO_ACTIVE_HIGH /* scl */

2
arch/arm/boot/dts/at91sam9263ek.dts
View File

@ -215,7 +215,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
status = "okay";
24c512@50 {

4
arch/arm/boot/dts/at91sam9g20ek_common.dtsi
View File

@ -170,13 +170,13 @@
};
};
usb0: ohci@00500000 {
usb0: ohci@500000 {
num-ports = <2>;
status = "okay";
};
};
i2c@0 {
i2c-gpio-0 {
status = "okay";
24c512@50 {

26
arch/arm/boot/dts/at91sam9g25ek.dts
View File

@ -26,7 +26,24 @@
i2c0: i2c@f8010000 {
ov2640: camera@0x30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
clocks = <&pck0>;
clock-names = "xvclk";
assigned-clocks = <&pck0>;
assigned-clock-rates = <25000000>;
status = "okay";
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
@ -37,6 +54,15 @@
isi: isi@f8048000 {
status = "okay";
port {
isi_0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
};
};

28
arch/arm/boot/dts/at91sam9g45.dtsi
View File

@ -1044,28 +1044,24 @@
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres";
trigger@0 {
reg = <0>;
trigger0 {
trigger-name = "external-rising";
trigger-value = <0x1>;
trigger-external;
};
trigger@1 {
reg = <1>;
trigger1 {
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
};
trigger@2 {
reg = <2>;
trigger2 {
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
};
trigger@3 {
reg = <3>;
trigger3 {
trigger-name = "continuous";
trigger-value = <0x6>;
};
@ -1169,13 +1165,13 @@
clock-names = "pclk", "hclk";
status = "disabled";
ep0 {
ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep1 {
ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -1183,7 +1179,7 @@
atmel,can-isoc;
};
ep2 {
ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -1191,21 +1187,21 @@
atmel,can-isoc;
};
ep3 {
ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep4 {
ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep5 {
ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -1213,7 +1209,7 @@
atmel,can-isoc;
};
ep6 {
ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -1320,7 +1316,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
&pioA 21 GPIO_ACTIVE_HIGH /* scl */

2
arch/arm/boot/dts/at91sam9n12.dtsi
View File

@ -1030,7 +1030,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
&pioA 31 GPIO_ACTIVE_HIGH /* scl */

30
arch/arm/boot/dts/at91sam9rl.dtsi
View File

@ -265,25 +265,21 @@
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres";
trigger@0 {
reg = <0>;
trigger0 {
trigger-name = "timer-counter-0";
trigger-value = <0x1>;
};
trigger@1 {
reg = <1>;
trigger1 {
trigger-name = "timer-counter-1";
trigger-value = <0x3>;
};
trigger@2 {
reg = <2>;
trigger2 {
trigger-name = "timer-counter-2";
trigger-value = <0x5>;
};
trigger@3 {
reg = <3>;
trigger3 {
trigger-name = "external";
trigger-value = <0x13>;
trigger-external;
@ -301,13 +297,13 @@
clock-names = "pclk", "hclk";
status = "disabled";
ep0 {
ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep1 {
ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -315,7 +311,7 @@
atmel,can-isoc;
};
ep2 {
ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -323,21 +319,21 @@
atmel,can-isoc;
};
ep3 {
ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep4 {
ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep5 {
ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -345,7 +341,7 @@
atmel,can-isoc;
};
ep6 {
ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -1093,7 +1089,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
<&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
@ -1107,7 +1103,7 @@
status = "disabled";
};
i2c@1 {
i2c-gpio-1 {
compatible = "i2c-gpio";
gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
<&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */

4
arch/arm/boot/dts/at91sam9rlek.dts
View File

@ -227,11 +227,11 @@
};
};
i2c@0 {
i2c-gpio-0 {
status = "okay";
};
i2c@1 {
i2c-gpio-1 {
status = "okay";
};
};

32
arch/arm/boot/dts/at91sam9x5.dtsi
View File

@ -1048,29 +1048,25 @@
atmel,adc-res-names = "lowres", "highres";
atmel,adc-use-res = "highres";
trigger@0 {
reg = <0>;
trigger0 {
trigger-name = "external-rising";
trigger-value = <0x1>;
trigger-external;
};
trigger@1 {
reg = <1>;
trigger1 {
trigger-name = "external-falling";
trigger-value = <0x2>;
trigger-external;
};
trigger@2 {
reg = <2>;
trigger2 {
trigger-name = "external-any";
trigger-value = <0x3>;
trigger-external;
};
trigger@3 {
reg = <3>;
trigger3 {
trigger-name = "continuous";
trigger-value = <0x6>;
};
@ -1119,13 +1115,13 @@
clock-names = "hclk", "pclk";
status = "disabled";
ep0 {
ep@0 {
reg = <0>;
atmel,fifo-size = <64>;
atmel,nb-banks = <1>;
};
ep1 {
ep@1 {
reg = <1>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -1133,7 +1129,7 @@
atmel,can-isoc;
};
ep2 {
ep@2 {
reg = <2>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <2>;
@ -1141,21 +1137,21 @@
atmel,can-isoc;
};
ep3 {
ep@3 {
reg = <3>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep4 {
ep@4 {
reg = <4>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
atmel,can-dma;
};
ep5 {
ep@5 {
reg = <5>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -1163,7 +1159,7 @@
atmel,can-isoc;
};
ep6 {
ep@6 {
reg = <6>;
atmel,fifo-size = <1024>;
atmel,nb-banks = <3>;
@ -1242,7 +1238,7 @@
};
};
i2c@0 {
i2c-gpio-0 {
compatible = "i2c-gpio";
gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
&pioA 31 GPIO_ACTIVE_HIGH /* scl */
@ -1257,7 +1253,7 @@
status = "disabled";
};
i2c@1 {
i2c-gpio-1 {
compatible = "i2c-gpio";
gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
&pioC 1 GPIO_ACTIVE_HIGH /* scl */
@ -1272,7 +1268,7 @@
status = "disabled";
};
i2c@2 {
i2c-gpio-2 {
compatible = "i2c-gpio";
gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
&pioB 5 GPIO_ACTIVE_HIGH /* scl */

33
arch/arm/boot/dts/at91sam9x5ek.dtsi
View File

@ -60,18 +60,6 @@
status = "okay";
};
isi: isi@f8048000 {
status = "disabled";
port {
isi_0: endpoint@0 {
remote-endpoint = <&ov2640_0>;
bus-width = <8>;
vsync-active = <1>;
hsync-active = <1>;
};
};
};
i2c0: i2c@f8010000 {
status = "okay";
@ -79,27 +67,6 @@
compatible = "wm8731";
reg = <0x1a>;
};
ov2640: camera@0x30 {
compatible = "ovti,ov2640";
reg = <0x30>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
clocks = <&pck0>;
clock-names = "xvclk";
assigned-clocks = <&pck0>;
assigned-clock-rates = <25000000>;
status = "disabled";
port {
ov2640_0: endpoint {
remote-endpoint = <&isi_0>;
bus-width = <8>;
};
};
};
};
adc0: adc@f804c000 {

1
arch/arm/boot/dts/axp209.dtsi
View File

@ -87,6 +87,7 @@
reg_ldo5: ldo5 {
regulator-name = "ldo5";
status = "disabled";
};
};

12
arch/arm/boot/dts/axp22x.dtsi
View File

@ -126,10 +126,12 @@
reg_ldo_io0: ldo_io0 {
regulator-name = "ldo_io0";
status = "disabled";
};
reg_ldo_io1: ldo_io1 {
regulator-name = "ldo_io1";
status = "disabled";
};
reg_rtc_ldo: rtc_ldo {
@ -139,5 +141,15 @@
regulator-max-microvolt = <3000000>;
regulator-name = "rtc_ldo";
};
reg_drivevbus: drivevbus {
regulator-name = "drivevbus";
status = "disabled";
};
};
usb_power_supply: usb_power_supply {
compatible = "x-powers,axp221-usb-power-supply";
status = "disabled";
};
};

53
arch/arm/boot/dts/axp809.dtsi Normal file
View File

@ -0,0 +1,53 @@
/*
* Copyright 2015 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* AXP809 Integrated Power Management Chip
*/
&axp809 {
compatible = "x-powers,axp809";
interrupt-controller;
#interrupt-cells = <1>;
};

11
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -366,5 +366,16 @@
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
adc: adc@180a6000 {
compatible = "brcm,iproc-static-adc";
#io-channel-cells = <1>;
io-channel-ranges;
adc-syscon = <&ts_adc_syscon>;
clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
clock-names = "tsc_clk";
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
};

55
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -57,7 +57,7 @@
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
enable-method = "brcm,bcm-nsp-smp";
secondary-boot-reg = <0xffff042c>;
secondary-boot-reg = <0xffff0fec>;
reg = <0x1>;
};
};
@ -192,6 +192,23 @@
status = "disabled";
};
dma@20000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>;
clock-names = "apb_pclk";
#dma-cells = <1>;
};
nand: nand@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
@ -337,6 +354,18 @@
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
status = "disabled";
msi-parent = <&msi0>;
msi0: msi@18012000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
<GIC_SPI 128 IRQ_TYPE_NONE>,
<GIC_SPI 129 IRQ_TYPE_NONE>,
<GIC_SPI 130 IRQ_TYPE_NONE>;
brcm,pcie-msi-inten;
};
};
pcie1: pcie@18013000 {
@ -361,6 +390,18 @@
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
status = "disabled";
msi-parent = <&msi1>;
msi1: msi@18013000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>,
<GIC_SPI 134 IRQ_TYPE_NONE>,
<GIC_SPI 135 IRQ_TYPE_NONE>,
<GIC_SPI 136 IRQ_TYPE_NONE>;
brcm,pcie-msi-inten;
};
};
pcie2: pcie@18014000 {
@ -385,5 +426,17 @@
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
status = "disabled";
msi-parent = <&msi2>;
msi2: msi@18014000 {
compatible = "brcm,iproc-msi";
msi-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>,
<GIC_SPI 140 IRQ_TYPE_NONE>,
<GIC_SPI 141 IRQ_TYPE_NONE>,
<GIC_SPI 142 IRQ_TYPE_NONE>;
brcm,pcie-msi-inten;
};
};
};

2
arch/arm/boot/dts/bcm11351.dtsi
View File

@ -30,7 +30,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
cpu0: cpu@0 {
device_type = "cpu";
@ -41,6 +40,7 @@
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x3500417c>;
reg = <1>;
};

2
arch/arm/boot/dts/bcm21664.dtsi
View File

@ -30,7 +30,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "brcm,bcm11351-cpu-method";
cpu0: cpu@0 {
device_type = "cpu";
@ -41,6 +40,7 @@
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
enable-method = "brcm,bcm11351-cpu-method";
secondary-boot-reg = <0x35004178>;
reg = <1>;
};

80
arch/arm/boot/dts/bcm23550-sparrow.dts Normal file
View File

@ -0,0 +1,80 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "bcm23550.dtsi"
/ {
model = "BCM23550 Sparrow board";
compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550";
chosen {
stdout-path = "/slaves@3e000000/serial@0:115200n8";
bootargs = "console=ttyS0,115200n8";
};
memory {
reg = <0x80000000 0x20000000>; /* 512 MB */
};
};
&uartb {
status = "okay";
};
&usbotg {
status = "okay";
};
&usbphy {
status = "okay";
};
&sdio1 {
max-frequency = <48000000>;
status = "okay";
};
&sdio2 {
non-removable;
max-frequency = <48000000>;
status = "okay";
};
&sdio4 {
max-frequency = <48000000>;
cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
status = "okay";
};

415
arch/arm/boot/dts/bcm23550.dtsi Normal file
View File

@ -0,0 +1,415 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/* BCM23550 and BCM21664 have almost identical clocks */
#include "dt-bindings/clock/bcm21664.h"
#include "skeleton.dtsi"
/ {
model = "BCM23550 SoC";
compatible = "brcm,bcm23550";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
clock-frequency = <1000000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x35004178>;
reg = <1>;
clock-frequency = <1000000000>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x35004178>;
reg = <2>;
clock-frequency = <1000000000>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "brcm,bcm23550";
secondary-boot-reg = <0x35004178>;
reg = <3>;
clock-frequency = <1000000000>;
};
};
/* Hub bus */
hub@34000000 {
compatible = "simple-bus";
ranges = <0 0x34000000 0x102f83ac>;
#address-cells = <1>;
#size-cells = <1>;
smc@4e000 {
compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
};
resetmgr: reset-controller@1001f00 {
compatible = "brcm,bcm21664-resetmgr";
reg = <0x01001f00 0x24>;
};
gpio: gpio@1003000 {
compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
reg = <0x01003000 0x524>;
interrupts =
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
};
timer@1006000 {
compatible = "brcm,kona-timer";
reg = <0x01006000 0x1c>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
};
};
/* Slaves bus */
slaves@3e000000 {
compatible = "simple-bus";
ranges = <0 0x3e000000 0x0001c070>;
#address-cells = <1>;
#size-cells = <1>;
uartb: serial@0 {
compatible = "snps,dw-apb-uart";
status = "disabled";
reg = <0x00000000 0x118>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uartb2: serial@1000 {
compatible = "snps,dw-apb-uart";
status = "disabled";
reg = <0x00001000 0x118>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
uartb3: serial@2000 {
compatible = "snps,dw-apb-uart";
status = "disabled";
reg = <0x00002000 0x118>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
};
bsc1: i2c@16000 {
compatible = "brcm,kona-i2c";
reg = <0x00016000 0x70>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
status = "disabled";
};
bsc2: i2c@17000 {
compatible = "brcm,kona-i2c";
reg = <0x00017000 0x70>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
status = "disabled";
};
bsc3: i2c@18000 {
compatible = "brcm,kona-i2c";
reg = <0x00018000 0x70>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
status = "disabled";
};
bsc4: i2c@1c000 {
compatible = "brcm,kona-i2c";
reg = <0x0001c000 0x70>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
status = "disabled";
};
};
/* Apps bus */
apps@3e300000 {
compatible = "simple-bus";
ranges = <0 0x3e300000 0x01b77000>;
#address-cells = <1>;
#size-cells = <1>;
usbotg: usb@e20000 {
compatible = "snps,dwc2";
reg = <0x00e20000 0x10000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usb_otg_ahb_clk>;
clock-names = "otg";
phys = <&usbphy>;
phy-names = "usb2-phy";
status = "disabled";
};
usbphy: usb-phy@e30000 {
compatible = "brcm,kona-usb2-phy";
reg = <0x00e30000 0x28>;
#phy-cells = <0>;
status = "disabled";
};
sdio1: sdio@e80000 {
compatible = "brcm,kona-sdhci";
reg = <0x00e80000 0x801c>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
status = "disabled";
};
sdio2: sdio@e90000 {
compatible = "brcm,kona-sdhci";
reg = <0x00e90000 0x801c>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
status = "disabled";
};
sdio3: sdio@ea0000 {
compatible = "brcm,kona-sdhci";
reg = <0x00ea0000 0x801c>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
status = "disabled";
};
sdio4: sdio@eb0000 {
compatible = "brcm,kona-sdhci";
reg = <0x00eb0000 0x801c>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
status = "disabled";
};
cdc: cdc@1b0e000 {
compatible = "brcm,bcm23550-cdc";
reg = <0x01b0e000 0x78>;
};
gic: interrupt-controller@1b21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x01b21000 0x1000>,
<0x01b22000 0x1000>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
* Fixed clocks are defined before CCUs whose
* clocks may depend on them.
*/
ref_32k_clk: ref_32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
bbl_32k_clk: bbl_32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
ref_13m_clk: ref_13m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
var_13m_clk: var_13m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <13000000>;
};
dft_19_5m_clk: dft_19_5m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <19500000>;
};
ref_crystal_clk: ref_crystal {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <26000000>;
};
ref_52m_clk: ref_52m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
};
var_52m_clk: var_52m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
};
usb_otg_ahb_clk: usb_otg_ahb {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <52000000>;
};
ref_96m_clk: ref_96m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
};
var_96m_clk: var_96m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <96000000>;
};
ref_104m_clk: ref_104m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104000000>;
};
var_104m_clk: var_104m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <104000000>;
};
ref_156m_clk: ref_156m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <156000000>;
};
var_156m_clk: var_156m {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <156000000>;
};
root_ccu: root_ccu {
compatible = BCM21664_DT_ROOT_CCU_COMPAT;
reg = <0x35001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "frac_1m";
};
aon_ccu: aon_ccu {
compatible = BCM21664_DT_AON_CCU_COMPAT;
reg = <0x35002000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "hub_timer";
};
slave_ccu: slave_ccu {
compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
reg = <0x3e011000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "uartb",
"uartb2",
"uartb3",
"bsc1",
"bsc2",
"bsc3",
"bsc4";
};
master_ccu: master_ccu {
compatible = BCM21664_DT_MASTER_CCU_COMPAT;
reg = <0x3f001000 0x0f00>;
#clock-cells = <1>;
clock-output-names = "sdio1",
"sdio2",
"sdio3",
"sdio4",
"sdio1_sleep",
"sdio2_sleep",
"sdio3_sleep",
"sdio4_sleep";
};
};
};

1
arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
View File

@ -1,6 +1,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
/ {
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";

1
arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
View File

@ -1,6 +1,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9512.dtsi"
/ {
compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";

1
arch/arm/boot/dts/bcm2835-rpi-b.dts
View File

@ -1,6 +1,7 @@
/dts-v1/;
#include "bcm2835.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9512.dtsi"
/ {
compatible = "raspberrypi,model-b", "brcm,bcm2835";

1
arch/arm/boot/dts/bcm2836-rpi-2-b.dts
View File

@ -1,6 +1,7 @@
/dts-v1/;
#include "bcm2836.dtsi"
#include "bcm2835-rpi.dtsi"
#include "bcm283x-rpi-smsc9514.dtsi"
/ {
compatible = "raspberrypi,2-model-b", "brcm,bcm2836";

19
arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi Normal file
View File

@ -0,0 +1,19 @@
/ {
aliases {
ethernet = &ethernet;
};
};
&usb {
usb1@1 {
compatible = "usb424,9512";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet: usbether@1 {
compatible = "usb424,ec00";
reg = <1>;
};
};
};

19
arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi Normal file
View File

@ -0,0 +1,19 @@
/ {
aliases {
ethernet = &ethernet;
};
};
&usb {
usb1@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet: usbether@1 {
compatible = "usb424,ec00";
reg = <1>;
};
};
};

2
arch/arm/boot/dts/bcm283x.dtsi
View File

@ -287,6 +287,8 @@
compatible = "brcm,bcm2835-usb";
reg = <0x7e980000 0x10000>;
interrupts = <1 9>;
#address-cells = <1>;
#size-cells = <0>;
};
v3d: v3d@7ec00000 {

4
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
View File

@ -147,3 +147,7 @@
&usb3 {
vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
};
&spi_nor {
status = "okay";
};

4
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View File

@ -90,3 +90,7 @@
&usb3 {
vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
};
&spi_nor {
status = "okay";
};

4
arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
View File

@ -82,3 +82,7 @@
};
};
};
&spi_nor {
status = "okay";
};

40
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
View File

@ -126,3 +126,43 @@
&spi_nor {
status = "okay";
};
&srab {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "lan4";
};
port@1 {
reg = <1>;
label = "lan3";
};
port@2 {
reg = <2>;
label = "lan2";
};
port@3 {
reg = <3>;
label = "lan1";
};
port@4 {
reg = <4>;
label = "wan";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

4
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View File

@ -131,3 +131,7 @@
&usb2 {
vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
};
&spi_nor {
status = "okay";
};

6
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
View File

@ -10,7 +10,7 @@
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
#include "bcm5301x-nand-cs0-bch1.dtsi"
/ {
compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708";
@ -113,3 +113,7 @@
&usb3 {
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
};
&spi_nor {
status = "okay";
};

15
arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi Normal file
View File

@ -0,0 +1,15 @@
/*
* Broadcom Northstar NAND.
*
* Copyright (C) 2016 Rafał Miłecki <rafal.milecki@gmail.com>
*
* Licensed under the ISC license.
*/
#include "bcm5301x-nand-cs0.dtsi"
&nandcs {
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
};

16
arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi
View File

@ -9,16 +9,10 @@
* Licensed under the GNU/GPL. See COPYING for details.
*/
/ {
nand@18028000 {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
#include "bcm5301x-nand-cs0.dtsi"
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};
};
&nandcs {
nand-ecc-algo = "bch";
nand-ecc-strength = <8>;
nand-ecc-step-size = <512>;
};

18
arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi Normal file
View File

@ -0,0 +1,18 @@
/*
* Broadcom Northstar NAND.
*
* Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
*
* Licensed under the GNU/GPL. See COPYING for details.
*/
/ {
nand@18028000 {
nandcs: nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};

47
arch/arm/boot/dts/bcm5301x.dtsi
View File

@ -153,6 +153,21 @@
/* ChipCommon */
<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
/* Switch Register Access Block */
<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
/* PCIe Controller 0 */
<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
@ -239,6 +254,22 @@
status = "disabled";
};
};
gmac0: ethernet@24000 {
reg = <0x24000 0x800>;
};
gmac1: ethernet@25000 {
reg = <0x25000 0x800>;
};
gmac2: ethernet@26000 {
reg = <0x26000 0x800>;
};
gmac3: ethernet@27000 {
reg = <0x27000 0x800>;
};
};
lcpll0: lcpll0@1800c100 {
@ -260,6 +291,22 @@
"sata2";
};
srab: srab@18007000 {
compatible = "brcm,bcm5301x-srab";
reg = <0x18007000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
/* ports are defined in board DTS */
};
rng: rng@18004000 {
compatible = "brcm,bcm5301x-rng";
reg = <0x18004000 0x14>;
};
nand: nand@18028000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;

104
arch/arm/boot/dts/bcm953012er.dts Normal file
View File

@ -0,0 +1,104 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm4708.dtsi"
#include "bcm5301x-nand-cs0-bch8.dtsi"
/ {
model = "NorthStar Enterprise Router (BCM953012ER)";
compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x00000000 0x8000000>;
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
};
restart {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
};
};
};
&uart0 {
status = "okay";
};
&spi_nor {
status = "okay";
};
&srab {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "port0";
};
port@1 {
reg = <1>;
label = "port1";
};
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&gmac0>;
};
};
};

109
arch/arm/boot/dts/bcm958525xmc.dts Normal file
View File

@ -0,0 +1,109 @@
/*
* BSD LICENSE
*
* Copyright(c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm-nsp.dtsi"
/ {
model = "NorthStar Plus XMC (BCM958525xmc)";
compatible = "brcm,bcm58525", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
partition@0 {
label = "nboot";
reg = <0x00000000 0x00200000>;
read-only;
};
partition@200000 {
label = "nenv";
reg = <0x00200000 0x00400000>;
};
partition@600000 {
label = "nsystem";
reg = <0x00600000 0x00a00000>;
};
partition@1000000 {
label = "nrootfs";
reg = <0x01000000 0x03000000>;
};
partition@4000000 {
label = "ncustfs";
reg = <0x04000000 0x3c000000>;
};
};
};
/* XHCI, SATA, MMC, and Ethernet support needed to be complete */
&uart0 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
};

111
arch/arm/boot/dts/bcm958625hr.dts Normal file
View File

@ -0,0 +1,111 @@
/*
* BSD LICENSE
*
* Copyright (c) 2016 Broadcom. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Broadcom Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/dts-v1/;
#include "bcm-nsp.dtsi"
/ {
model = "NorthStar Plus SVK (BCM958625HR)";
compatible = "brcm,bcm58625", "brcm,nsp";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory {
reg = <0x60000000 0x20000000>;
};
};
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-strength = <24>;
nand-ecc-step-size = <1024>;
brcm,nand-oob-sector-size = <27>;
partition@0 {
label = "nboot";
reg = <0x00000000 0x00200000>;
read-only;
};
partition@200000 {
label = "nenv";
reg = <0x00200000 0x00400000>;
};
partition@600000 {
label = "nsystem";
reg = <0x00600000 0x00a00000>;
};
partition@1000000 {
label = "nrootfs";
reg = <0x01000000 0x03000000>;
};
partition@4000000 {
label = "ncustfs";
reg = <0x04000000 0x3c000000>;
};
};
};
&uart0 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&nand_sel>;
nand_sel: nand_sel {
function = "nand";
groups = "nand_grp";
};
};

2
arch/arm/boot/dts/compulab-sb-som.dtsi
View File

@ -40,7 +40,7 @@
};
};
hdmi_conn: connector@0 {
hdmi_conn: connector {
compatible = "hdmi-connector";
label = "hdmi";

2
arch/arm/boot/dts/dm814x.dtsi
View File

@ -448,7 +448,7 @@
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
interrupt-names = "edma3_ccint", "emda3_mperr",
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;

242
arch/arm/boot/dts/dra7.dtsi
View File

@ -73,6 +73,49 @@
interrupt-parent = <&gic>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
operating-points-v2 = <&cpu0_opp_table>;
ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>;
ti,syscon-rev = <&scm_wkup 0x204>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp_nom@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
opp_od@1176000000 {
opp-hz = /bits/ 64 <1176000000>;
opp-microvolt = <1160000 885000 1160000>;
opp-supported-hw = <0xFF 0x02>;
};
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
@ -233,6 +276,11 @@
prm_clockdomains: clockdomains {
};
};
scm_wkup: scm_conf@c000 {
compatible = "syscon";
reg = <0xc000 0x1000>;
};
};
axi@0 {
@ -276,7 +324,7 @@
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
pcie@51000000 {
pcie@51800000 {
compatible = "ti,dra7-pcie";
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@ -304,6 +352,53 @@
};
};
ocmcram1: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x80000>;
ranges = <0x0 0x40300000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
/*
* This is a placeholder for an optional reserved
* region for use by secure software. The size
* of this region is not known until runtime so it
* is set as zero to either be updated to reserve
* space or left unchanged to leave all SRAM for use.
* On HS parts that that require the reserved region
* either the bootloader can update the size to
* the required amount or the node can be overridden
* from the board dts file for the secure platform.
*/
sram-hs@0 {
compatible = "ti,secure-ram";
reg = <0x0 0x0>;
};
};
/*
* NOTE: ocmcram2 and ocmcram3 are not available on all
* DRA7xx and AM57xx variants. Confirm availability in
* the data manual for the exact part number in use
* before enabling these nodes in the board dts file.
*/
ocmcram2: ocmcram@40400000 {
status = "disabled";
compatible = "mmio-sram";
reg = <0x40400000 0x100000>;
ranges = <0x0 0x40400000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
ocmcram3: ocmcram@40500000 {
status = "disabled";
compatible = "mmio-sram";
reg = <0x40500000 0x100000>;
ranges = <0x0 0x40500000 0x100000>;
#address-cells = <1>;
#size-cells = <1>;
};
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
@ -341,7 +436,7 @@
interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma3_ccint", "emda3_mperr",
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
@ -1744,6 +1839,149 @@
clock-names = "fck", "sys_clk";
};
};
epwmss0: epwmss@4843e000 {
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
reg = <0x4843e000 0x30>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
ehrpwm0: pwm@4843e200 {
compatible = "ti,dra746-ehrpwm",
"ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x4843e200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ecap0: ecap@4843e100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x4843e100 0x80>;
clocks = <&l4_root_clk_div>;
clock-names = "fck";
status = "disabled";
};
};
epwmss1: epwmss@48440000 {
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
reg = <0x48440000 0x30>;
ti,hwmods = "epwmss1";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
ehrpwm1: pwm@48440200 {
compatible = "ti,dra746-ehrpwm",
"ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x48440200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ecap1: ecap@48440100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x48440100 0x80>;
clocks = <&l4_root_clk_div>;
clock-names = "fck";
status = "disabled";
};
};
epwmss2: epwmss@48442000 {
compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
reg = <0x48442000 0x30>;
ti,hwmods = "epwmss2";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges;
ehrpwm2: pwm@48442200 {
compatible = "ti,dra746-ehrpwm",
"ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x48442200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
clock-names = "tbclk", "fck";
status = "disabled";
};
ecap2: ecap@48442100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x48442100 0x80>;
clocks = <&l4_root_clk_div>;
clock-names = "fck";
status = "disabled";
};
};
aes1: aes@4b500000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes1";
reg = <0x4b500000 0xa0>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
aes2: aes@4b700000 {
compatible = "ti,omap4-aes";
ti,hwmods = "aes2";
reg = <0x4b700000 0xa0>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
des: des@480a5000 {
compatible = "ti,omap4-des";
ti,hwmods = "des";
reg = <0x480a5000 0xa0>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
dma-names = "tx", "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
sham: sham@53100000 {
compatible = "ti,omap5-sham";
ti,hwmods = "sham";
reg = <0x4b101000 0x300>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&edma_xbar 119 0>;
dma-names = "rx";
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
rng: rng@48090000 {
compatible = "ti,omap4-rng";
ti,hwmods = "rng";
reg = <0x48090000 0x2000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
};
thermal_zones: thermal-zones {

12
arch/arm/boot/dts/dra72-evm-common.dtsi
View File

@ -18,7 +18,7 @@
display0 = &hdmi0;
};
evm_3v3: fixedregulator-evm_3v3 {
evm_3v3_sw: fixedregulator-evm_3v3 {
compatible = "regulator-fixed";
regulator-name = "evm_3v3";
regulator-min-microvolt = <3300000>;
@ -29,7 +29,7 @@
/* TPS77018DBVT */
compatible = "regulator-fixed";
regulator-name = "aic_dvdd";
vin-supply = <&evm_3v3>;
vin-supply = <&evm_3v3_sw>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
@ -414,9 +414,9 @@
status = "okay";
/* Regulators */
AVDD-supply = <&evm_3v3>;
IOVDD-supply = <&evm_3v3>;
DRVDD-supply = <&evm_3v3>;
AVDD-supply = <&evm_3v3_sw>;
IOVDD-supply = <&evm_3v3_sw>;
DRVDD-supply = <&evm_3v3_sw>;
DVDD-supply = <&aic_dvdd>;
};
};
@ -597,7 +597,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&evm_3v3>;
vmmc-supply = <&evm_3v3_sw>;
bus-width = <8>;
ti,non-removable;
max-frequency = <192000000>;

16
arch/arm/boot/dts/dra72x.dtsi
View File

@ -12,22 +12,6 @@
/ {
compatible = "ti,dra722", "ti,dra72", "ti,dra7";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0>;
/* cooling options */
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
};
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupt-parent = <&wakeupgen>;

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